Patent Application
20240222293
As transistor density increases, interconnect density for connections between dies and substrates is increasing as well. Interconnect design in substrate packages can improve power delivery and overall system performance. Thinner traces can provide more density, but thinner traces can carry less current as well as less heat. Thicker traces can carry more current and heat, but thicker traces may be less dense.
Efficient interconnect design in substrate packaging to improve power delivery and overall system performance is an area of interest. One approach for power delivery improvement is to have asymmetric copper plating, with thinner, denser copper plating for the front side that connects to a die and thicker, less dense copper plating for the back side that connects to a higher-level interconnect or motherboard. Traces or power lines with thicker copper plating on the back side layers can serve the purpose of reducing current resistance, increasing maximum current, providing increased heat dissipation lines for thermal management, which improves power delivery, reduces latency, and allows for increase of the overall clock speed.
In one embodiment disclosed herein, as described in more detail below, a substrate for an integrated circuit has one or more layers with thinner copper traces on one part and one or more layers with thicker copper traces on another part. In the illustrative embodiment, the two parts of the substrate are created separately and joined together using a hybrid bond approach. In some embodiments, one part of the substrate is built up on a core. In other embodiments, a core is not used. In some embodiments, a magnetic core increases the inductance of an inductor, allowing for, e.g., improved voltage regulation. In other embodiments, a magnetic core may not be present.
In the following description, specific details are set forth, but embodiments of the technologies described herein may be practiced without these specific details. Well-known circuits, structures, and techniques have not been shown in detail to avoid obscuring an understanding of this description. Phrases such as “an embodiment,” “various embodiments,” “some embodiments,” and the like may include features, structures, or characteristics, but not every embodiment necessarily includes the particular features, structures, or characteristics. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described. Additionally, it should be appreciated that items included in a list in the form of “at least one A, B, and C” can mean (A); (B); (C); (A and B); (A and C); (B and C); or (A, B, and C). Similarly, items listed in the form of “at least one of A, B, or C” can mean (A); (B); (C); (A and B); (A and C); (B and C); or (A, B, and C).
In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding thereof. It may be evident, however, that the novel embodiments can be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form in order to facilitate a description thereof. The intention is to cover all modifications, equivalents, and alternatives within the scope of the claims.
Some embodiments may have some, all, or none of the features described for other embodiments. “First,” “second,” “third,” and the like describe a common object and indicate different instances of like objects being referred to. Such adjectives do not imply objects so described must be in a given sequence, either temporally or spatially, in ranking, or any other manner. “Connected” may indicate elements are in direct physical or electrical contact, and “coupled” may indicate elements co-operate or interact, but they may or may not be in direct physical or electrical contact. Furthermore, the terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present disclosure, are synonymous. Terms modified by the word “substantially” include arrangements, orientations, spacings, or positions that vary slightly from the meaning of the unmodified term. For example, a substrate assembly feature, such as a through width, that is described as having substantially a listed dimension can vary within a few percent of the listed dimension.
As used herein, the phrase “communicatively coupled” refers to the ability of a component to send a signal to or receive a signal from another component. The signal can be any type of signal, such as an input signal, an output signal, or a power signal. A component can send or receive a signal to another component to which it is communicatively coupled via a wired or wireless communication medium (e.g., conductive traces, conductive contacts, air). Examples of components that are communicatively coupled include integrated circuit dies located in the same package that communicate via an embedded bridge in a package substrate and an integrated circuit component attached to a printed circuit board that send signals to or receives signals from other integrated circuit components or electronic devices attached to the printed circuit board.
It will be understood that in the examples shown and described further below, the figures may not be drawn to scale and may not include all possible layers and/or circuit components. In addition, it will be understood that although certain figures illustrate transistor designs with source/drain regions, electrodes, etc. having orthogonal (e.g., perpendicular) boundaries, embodiments herein may implement such boundaries in a substantially orthogonal manner (e.g., within +/−5 or 10 degrees of orthogonality) due to fabrication methods used to create such devices or for other reasons.
As used herein, the phrase “located on” in the context of a first layer or component located on a second layer or component refers to the first layer or component being directly physically attached to the second part or component (no layers or components between the first and second layers or components) or physically attached to the second layer or component with one or more intervening layers or components.
As used herein, the term “adjacent” refers to layers or components that are in physical contact with each other. That is, there is no layer or component between the stated adjacent layers or components. For example, a layer X that is adjacent to a layer Y refers to a layer that is in physical contact with layer Y.
As used herein, the terms “upper”/“lower” or “above”/“below” may refer to relative locations of an object (e.g., the surfaces described above), especially in light of examples shown in the attached figures, rather than an absolute location of an object. For example, an upper surface of an apparatus may be on an opposite side of the apparatus from a lower surface of the object, and the upper surface may be facing upward generally only when viewed in a particular way. As another example, a first object above a second object may be on or near an “upper” surface of the second object rather than near a “lower” surface of the object, and the first object may be truly above the second object only when the two objects are viewed in a particular way.
References are made to the drawings, which are not necessarily drawn to scale, wherein similar or same numbers may be used to designate the same or similar parts in different figures. The use of similar or same numbers in different figures does not mean all figures including similar or same numbers constitute a single or same embodiment. Like numerals having different letter suffixes may represent different instances of similar components. The drawings illustrate generally, by way of example, but not by way of limitation, various embodiments discussed in the present document. Different parts of the drawings with the same hatchings refer to the same component or material unless labeled otherwise.
Referring now to
The substrate 102 also includes layers 132A-D. Each layer 132A, 132B, 132C, 132D similarly includes a corresponding dielectric layer 110A, 110B, 110C, 110D and one or more conductive traces 118. The conductive traces 118 may also act as pads for vias 120. Vias 120 may connect traces in one layer 110 to another layer 110. The traces 112, 118 provide interconnects for, e.g., delivering power to the die 104 and providing input and output signals to and from the die 104 and/or other components connected to the substrate 102. The traces 112, 118 may route signals along and between layers 130A-D, 132A-D.
In the illustrative embodiment, the traces 118 are thinner and may be finer pitch than the traces 112. In particular, in the illustrative embodiment, the traces 118 have a thickness of 15 micrometers, and the traces 112 have a thickness of 25 micrometers. The traces 118 may have a width of 9 micrometers and a spacing of 12 micrometers between traces 118. The traces 112 may have a width of 20 micrometers and a spacing of 20 micrometers between traces 118. In some places, such as where the traces 118, 112 act as pads for vias 120, 114, the traces 112, 118 may be wider than 9 or 12 micrometers, respectively.
More generally, the traces 118 on layers 132A-D are thinner than the traces 112 on layers 130A-C. For example, the traces 118 may be 30-90% of the thickness of the traces 112. The traces 112 may have any suitable thickness, such as 15-100 micrometers. The traces 118 may also have any suitable thickness, such as 10-90 micrometers. In the illustrative embodiment, the traces 118 are copper. In other embodiments, the traces 118 (and other components described as copper herein) may be made of another metal or conductive material.
In the illustrative embodiment, the layers 130A-D are joined with the layers 132A-D by a hybrid bond 108. The hybrid bond 108 includes one or more metal-metal fusion (or direct) bonds 124, one or more metal-dielectric bonds 126, and one or more dielectric bonds 128. In the illustrative embodiment, the bonds 126, 128 with a dielectric include benzocyclobutene (BCB). In other embodiments, the bonds 126, 128 with a dielectric may include silicon oxide or silicon nitride. The formation of the hybrid bond 108 is described in more detail below in regard to the method 300 described in
In the illustrative embodiment, the dielectric layers 110D, 106D may be solder resist lamination. The dielectric layers 106A-C, 110A-C may be any suitable dielectric, such as Ajinomoto build-up film (ABF). The layers 130A-D, 132A-D may be any suitable thickness, such as 10-100 micrometers. In some embodiments, the layers 132A-D may be thinner than layers 130A-D, such as 40-90% of the thickness of the layers 130A-D. The vias/pads 134 may be embodied as a Cu—Ni—Sn alloy with a microball 122 of solder on top of it. The vias/pads 116 may be embodied as a Ni—Pd—Au alloy. The substrate 102 may include any suitable number of layers 130, 132, such as 1-6 layers. The number of layers 130 may be different from the number of layers 132.
It should be appreciated that the substrate 102 does include a substrate core. As described in more detail below, parts of the substrate are built up on glass carriers and combined using a hybrid bond. The lack of a substrate core can reduce the overall thickness of the substrate 102.
Referring now to
The method 300 begins in block 302, in which a laser release film 804 and a temporary bond film 806 are placed on a carrier substrate 802, as shown in
In block 304, a copper seed layer 808 is grown on the temporary bond film 806, as shown in
In block 316, a solder resist lamination layer 110D is deposited. In block 318, via openings are laser drilled or lithographically patterned. In block 320, the via openings are cleaned and filled with a conductive material such as a Cu—Ni—Sn alloy, as shown in
Referring now to
In block 328, the copper seed layer 808 is etched away, as shown in
Referring now to
In block 348, a solder resist lamination layer 106D is deposited. In block 350, via openings are laser drilled or lithographically patterned. In block 352, the via openings are cleaned and filled with a conductive material such as a Ni—Pd—Au alloy, as shown in
Referring now to
In block 358, the copper seed layer 808 is etched away, as shown in
Referring now to
In block 368, the substrate parts are aligned. The substrate parts may be aligned using fiducial marks on the substrate parts. To improve the overlay precision, the substrate parts can be built with design considerations and mask bias to match the overall shrinkage of the two substrate parts. The substrate parts may then be clamped together.
In block 370, the substrate parts may be placed in a vacuum furnace at a temperature of around 150° C. for 30 minutes for diffusion bonding of the copper traces 112, 118 and adhesive bonding of the copper traces 112, 118 with the dielectric bond layer 1702 as well as for dielectric bonding of the dielectric bond layer 1702. In the illustrative embodiment, the bonding of the copper traces 112, 118 is the spontaneous adhesion of hydrophilic surfaces followed by copper diffusion across the bonding interface 108. The substrate 102 can be annealed at a temperature of 200° C. for 30 minutes to remove any residual stress and promote grain growth to improve both the interfacial strength and electrical conductivity. In other embodiments, a different bonding procedure may be used, such as applying different temperatures for different amounts of times. In general, the substrate 102 may be held at one or more temperatures of, e.g., 100-300° C. for a duration of 20 minutes to three hours.
After the two substrate parts are bonded together, the protective caps 1402 may be removed from the substrate 102. The substrate 102 may be integrated with other components such as a die 104, as shown in
Referring now to
The substrate 3002 includes a substrate core 3004. As described in more detail below, part of the substrate 1002 is built up on the substrate core 3004. The substrate core 3004 may provide more support and/or rigidity to the substrate 3002. The substrate core 3004 may be any suitable substrate core, such as resin with glass fiber, FR-4, CEM-1, etc. One or more vias 3008 pass through the substrate core 3004. The vias 3008 may be filled with copper or other metal. Traces or pads 3006 may be present on one side of the substrate core 3004. The substrate core 3004 is joined with another substrate part through a hybrid bond 108 in a similar manner as the substrate 102 described above.
Referring now to
The method 3100 begins in block 3102, in which one or more vias 3204 are laser drilled in a substrate core 3004, as shown in
In block 3106, a copper seed layer is grown in the vias, such as by using electroless plating. In block 3108, the vias are plated with copper, such as by using electrolytic plating, as shown in
In block 3112, the rest of the part of the substrate is created on the substrate core 3004, as shown in
In block 3114, another part of the substrate is formed on a glass carrier, as discussed above in regard to blocks 334-362 in the method 300, a description of which will not be repeated in the interest of clarity.
In block 3116, the parts of the substrate are bonded together, as shown in
Referring now to
The magnetic lining 3708 may include any suitable magnetic material. In an illustrative embodiment, the magnetic lining 3708 may be embodied as iron-cobalt and/or iron-nickel ferromagnetic alloy powders or nanoflakes mixed with an adjustable amount of carrier polymers such as polyimide or an epoxy resin and an organic solvent. The magnetic lining 3708 may have a narrow hysteresis loop with near-zero coercive magnetic field, which may be desirable for inductor applications. The iron-cobalt and/or iron-nickel particles may have a relative permeability on the order of 1,000, with the magnetic lining 3708 having a relative permeability on the order of 100. More generally, the magnetic lining 3708 may have a relative permeability of, e.g., 10-1,000.
Referring now to
The method 3900 begins in block 3902, in which one or more vias are laser drilled in a substrate core 3004. In block 3904, a magnetic paste 4002 may be deposited and cured, as shown in
In block 3906, vias 4102 are laser drilled through the magnetic paste 4002, leaving magnetic linings 3708 behind, as shown in
In block 3916, the rest of the part of the substrate is created on the substrate core 3004, as shown in
In block 3918, another part of the substrate is formed on a glass carrier, as discussed above in regard to blocks 334-362 in the method 300, a description of which will not be repeated in the interest of clarity.
In block 3920, the parts of the substrate are bonded together, as shown in
Referring now to
Referring now to
The method 4700 begins in block 4702, in which part of the substrate is created on glass carrier 802, as shown in
In block 4704, vias 4902 are drilled through some or all of the layers 110A-C, as shown in
In block 4708, a solder resist lamination layer 110D may be deposited as the last layer, with pads/vias with a conductive material such as a Cu—Ni—Sn alloy, as shown in
In block 4714, another part of the substrate is formed on a glass carrier 802 with relatively thick traces. Part of the creation of the part of the substrate may be similar to blocks 334-338 in the method 300, a description of which will not be repeated in the interest of clarity. A magnetic cap 4504 may be formed in the solder resist lamination layer 106D in a similar manner as the magnetic cap 4506, a description of which will not be repeated in the interest of clarity. The part of the substrate with the magnetic cap 4504 is shown in
In block 4716, the parts of the substrate are bonded together, as shown in
The integrated circuit device 5700 may include one or more device layers 5704 disposed on the die substrate 5702. The device layer 5704 may include features of one or more transistors 5740 (e.g., metal oxide semiconductor field-effect transistors (MOSFETs)) formed on the die substrate 5702. The transistors 5740 may include, for example, one or more source and/or drain (S/D) regions 5720, a gate 5722 to control current flow between the S/D regions 5720, and one or more S/D contacts 5724 to route electrical signals to/from the S/D regions 5720. The transistors 5740 may include additional features not depicted for the sake of clarity, such as device isolation regions, gate contacts, and the like. The transistors 5740 are not limited to the type and configuration depicted in
Returning to
The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric to improve its quality when a high-k material is used.
The gate electrode may be formed on the gate dielectric and may include at least one p-type work function metal or n-type work function metal, depending on whether the transistor 5740 is to be a p-type metal oxide semiconductor (PMOS) or an n-type metal oxide semiconductor (NMOS) transistor. In some implementations, the gate electrode may consist of a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer.
For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any of the metals discussed below with reference to an NMOS transistor (e.g., for work function tuning). For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals discussed above with reference to a PMOS transistor (e.g., for work function tuning).
In some embodiments, when viewed as a cross-section of the transistor 5740 along the source-channel-drain direction, the gate electrode may consist of a U-shaped structure that includes a bottom portion substantially parallel to the surface of the die substrate 5702 and two sidewall portions that are substantially perpendicular to the top surface of the die substrate 5702. In other embodiments, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the die substrate 5702 and does not include sidewall portions substantially perpendicular to the top surface of the die substrate 5702. In other embodiments, the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.
In some embodiments, a pair of sidewall spacers may be formed on opposing sides of the gate stack to bracket the gate stack. The sidewall spacers may be formed from materials such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In some embodiments, a plurality of spacer pairs may be used; for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.
The S/D regions 5720 may be formed within the die substrate 5702 adjacent to the gate 5722 of individual transistors 5740. The S/D regions 5720 may be formed using an implantation/diffusion process or an etching/deposition process, for example. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the die substrate 5702 to form the S/D regions 5720. An annealing process that activates the dopants and causes them to diffuse farther into the die substrate 5702 may follow the ion-implantation process. In the latter process, the die substrate 5702 may first be etched to form recesses at the locations of the S/D regions 5720. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the S/D regions 5720. In some implementations, the S/D regions 5720 may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In some embodiments, the S/D regions 5720 may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. In further embodiments, one or more layers of metal and/or metal alloys may be used to form the S/D regions 5720.
Electrical signals, such as power and/or input/output (I/O) signals, may be routed to and/or from the devices (e.g., transistors 5740) of the device layer 5704 through one or more interconnect layers disposed on the device layer 5704 (illustrated in
The interconnect structures 5728 may be arranged within the interconnect layers 5706-5710 to route electrical signals according to a wide variety of designs; in particular, the arrangement is not limited to the particular configuration of interconnect structures 5728 depicted in
In some embodiments, the interconnect structures 5728 may include lines 5728a and/or vias 5728b filled with an electrically conductive material such as a metal. The lines 5728a may be arranged to route electrical signals in a direction of a plane that is substantially parallel with a surface of the die substrate 5702 upon which the device layer 5704 is formed. For example, the lines 5728a may route electrical signals in a direction in and out of the page and/or in a direction across the page. The vias 5728b may be arranged to route electrical signals in a direction of a plane that is substantially perpendicular to the surface of the die substrate 5702 upon which the device layer 5704 is formed. In some embodiments, the vias 5728b may electrically couple lines 5728a of different interconnect layers 5706-5710 together.
The interconnect layers 5706-5710 may include a dielectric material 5726 disposed between the interconnect structures 5728, as shown in
A first interconnect layer 5706 (referred to as Metal 1 or “M1”) may be formed directly on the device layer 5704. In some embodiments, the first interconnect layer 5706 may include lines 5728a and/or vias 5728b, as shown. The lines 5728a of the first interconnect layer 5706 may be coupled with contacts (e.g., the S/D contacts 5724) of the device layer 5704. The vias 5728b of the first interconnect layer 5706 may be coupled with the lines 5728a of a second interconnect layer 5708.
The second interconnect layer 5708 (referred to as Metal 2 or “M2”) may be formed directly on the first interconnect layer 5706. In some embodiments, the second interconnect layer 5708 may include via 5728b to couple the lines 5728 of the second interconnect layer 5708 with the lines 5728a of a third interconnect layer 5710. Although the lines 5728a and the vias 5728b are structurally delineated with a line within individual interconnect layers for the sake of clarity, the lines 5728a and the vias 5728b may be structurally and/or materially contiguous (e.g., simultaneously filled during a dual-damascene process) in some embodiments.
The third interconnect layer 5710 (referred to as Metal 3 or “M3”) (and additional interconnect layers, as desired) may be formed in succession on the second interconnect layer 5708 according to similar techniques and configurations described in connection with the second interconnect layer 5708 or the first interconnect layer 5706. In some embodiments, the interconnect layers that are “higher up” in the metallization stack 5719 in the integrated circuit device 5700 (i.e., farther away from the device layer 5704) may be thicker that the interconnect layers that are lower in the metallization stack 5719, with lines 5728a and vias 5728b in the higher interconnect layers being thicker than those in the lower interconnect layers.
The integrated circuit device 5700 may include a solder resist material 5734 (e.g., polyimide or similar material) and one or more conductive contacts 5736 formed on the interconnect layers 5706-5710. In
In some embodiments in which the integrated circuit device 5700 is a double-sided die, the integrated circuit device 5700 may include another metallization stack (not shown) on the opposite side of the device layer(s) 5704. This metallization stack may include multiple interconnect layers as discussed above with reference to the interconnect layers 5706-5710, to provide conductive pathways (e.g., including conductive lines and vias) between the device layer(s) 5704 and additional conductive contacts (not shown) on the opposite side of the integrated circuit device 5700 from the conductive contacts 5736. These additional conductive contacts may serve as the conductive contacts 112, 116, 118, 134, as appropriate.
In other embodiments in which the integrated circuit device 5700 is a double-sided die, the integrated circuit device 5700 may include one or more through silicon vias (TSVs) through the die substrate 5702; these TSVs may make contact with the device layer(s) 5704, and may provide conductive pathways between the device layer(s) 5704 and additional conductive contacts (not shown) on the opposite side of the integrated circuit device 5700 from the conductive contacts 5736. These additional conductive contacts may serve as the conductive contacts 112, 116, 118, 134, as appropriate. In some embodiments, TSVs extending through the substrate can be used for routing power and ground signals from conductive contacts on the opposite side of the integrated circuit device 5700 from the conductive contacts 5736 to the transistors 5740 and any other components integrated into the die 5700, and the metallization stack 5719 can be used to route I/O signals from the conductive contacts 5736 to transistors 5740 and any other components integrated into the die 5700.
Multiple integrated circuit devices 5700 may be stacked with one or more TSVs in the individual stacked devices providing connection between one of the devices to any of the other devices in the stack. For example, one or more high-bandwidth memory (HBM) integrated circuit dies can be stacked on top of a base integrated circuit die and TSVs in the HBM dies can provide connection between the individual HBM and the base integrated circuit die. Conductive contacts can provide additional connections between adjacent integrated circuit dies in the stack. In some embodiments, the conductive contacts can be fine-pitch solder bumps (microbumps).
In some embodiments, the circuit board 5902 may be a printed circuit board (PCB) including multiple metal (or interconnect) layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. The individual metal layers comprise conductive traces. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 5902. In other embodiments, the circuit board 5902 may be a non-PCB substrate. In some embodiments the circuit board 5902 may be, for example, the substrates 102, 3002, 3702, 4502. The integrated circuit device assembly 5900 illustrated in
The package-on-interposer structure 5936 may include an integrated circuit component 5920 coupled to an interposer 5904 by coupling components 5918. The coupling components 5918 may take any suitable form for the application, such as the forms discussed above with reference to the coupling components 5916. Although a single integrated circuit component 5920 is shown in
The integrated circuit component 5920 may be a packaged or unpacked integrated circuit product that includes one or more integrated circuit dies (e.g., the die 5602 of
In embodiments where the integrated circuit component 5920 comprises multiple integrated circuit dies, they dies can be of the same type (a homogeneous multi-die integrated circuit component) or of two or more different types (a heterogeneous multi-die integrated circuit component). A multi-die integrated circuit component can be referred to as a multi-chip package (MCP) or multi-chip module (MCM).
In addition to comprising one or more processor units, the integrated circuit component 5920 can comprise additional components, such as embedded DRAM, stacked high bandwidth memory (HBM), shared cache memories, input/output (I/O) controllers, or memory controllers. Any of these additional components can be located on the same integrated circuit die as a processor unit, or on one or more integrated circuit dies separate from the integrated circuit dies comprising the processor units. These separate integrated circuit dies can be referred to as “chiplets”. In embodiments where an integrated circuit component comprises multiple integrated circuit dies, interconnections between dies can be provided by the package substrate, one or more silicon interposers, one or more silicon bridges embedded in the package substrate (such as Intel® embedded multi-die interconnect bridges (EMIBs)), or combinations thereof.
Generally, the interposer 5904 may spread connections to a wider pitch or reroute a connection to a different connection. For example, the interposer 5904 may couple the integrated circuit component 5920 to a set of ball grid array (BGA) conductive contacts of the coupling components 5916 for coupling to the circuit board 5902. In the embodiment illustrated in
In some embodiments, the interposer 5904 may be formed as a PCB, including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. In some embodiments, the interposer 5904 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, an epoxy resin with inorganic fillers, a ceramic material, or a polymer material such as polyimide. In some embodiments, the interposer 5904 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. The interposer 5904 may include metal interconnects 5908 and vias 5910, including but not limited to through hole vias 5910-1 (that extend from a first face 5950 of the interposer 5904 to a second face 5954 of the interposer 5904), blind vias 5910-2 (that extend from the first or second faces 5950 or 5954 of the interposer 5904 to an internal metal layer), and buried vias 5910-3 (that connect internal metal layers).
In some embodiments, the interposer 5904 can comprise a silicon interposer. Through silicon vias (TSV) extending through the silicon interposer can connect connections on a first face of a silicon interposer to an opposing second face of the silicon interposer. In some embodiments, an interposer 5904 comprising a silicon interposer can further comprise one or more routing layers to route connections on a first face of the interposer 5904 to an opposing second face of the interposer 5904.
The interposer 5904 may further include embedded devices 5914, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer 5904. The package-on-interposer structure 5936 may take the form of any of the package-on-interposer structures known in the art.
The integrated circuit device assembly 5900 may include an integrated circuit component 5924 coupled to the first face 5940 of the circuit board 5902 by coupling components 5922. The coupling components 5922 may take the form of any of the embodiments discussed above with reference to the coupling components 5916, and the integrated circuit component 5924 may take the form of any of the embodiments discussed above with reference to the integrated circuit component 5920.
The integrated circuit device assembly 5900 illustrated in
Additionally, in various embodiments, the electrical device 6000 may not include one or more of the components illustrated in
The electrical device 6000 may include one or more processor units 6002 (e.g., one or more processor units). As used herein, the terms “processor unit”, “processing unit” or “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The processor unit 6002 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), general-purpose GPUs (GPGPUs), accelerated processing units (APUs), field-programmable gate arrays (FPGAs), neural network processing units (NPUs), data processor units (DPUs), accelerators (e.g., graphics accelerator, compression accelerator, artificial intelligence accelerator), controller cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, controllers, or any other suitable type of processor units. As such, the processor unit can be referred to as an XPU (or xPU).
The electrical device 6000 may include a memory 6004, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM), static random-access memory (SRAM)), non-volatile memory (e.g., read-only memory (ROM), flash memory, chalcogenide-based phase-change non-voltage memories), solid state memory, and/or a hard drive. In some embodiments, the memory 6004 may include memory that is located on the same integrated circuit die as the processor unit 6002. This memory may be used as cache memory (e.g., Level 1 (L1), Level 2 (L2), Level 3 (L3), Level 4 (L4), Last Level Cache (LLC)) and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM).
In some embodiments, the electrical device 6000 can comprise one or more processor units 6002 that are heterogeneous or asymmetric to another processor unit 6002 in the electrical device 6000. There can be a variety of differences between the processing units 6002 in a system in terms of a spectrum of metrics of merit including architectural, microarchitectural, thermal, power consumption characteristics, and the like. These differences can effectively manifest themselves as asymmetry and heterogeneity among the processor units 6002 in the electrical device 6000.
In some embodiments, the electrical device 6000 may include a communication component 6012 (e.g., one or more communication components). For example, the communication component 6012 can manage wireless communications for the transfer of data to and from the electrical device 6000. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term “wireless” does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
The communication component 6012 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultra mobile broadband (UMB) project (also referred to as “3GPP2”), etc.). IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE 802.16 standards. The communication component 6012 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication component 6012 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication component 6012 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication component 6012 may operate in accordance with other wireless protocols in other embodiments. The electrical device 6000 may include an antenna 6022 to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions).
In some embodiments, the communication component 6012 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., IEEE 802.3 Ethernet standards). As noted above, the communication component 6012 may include multiple communication components. For instance, a first communication component 6012 may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication component 6012 may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication component 6012 may be dedicated to wireless communications, and a second communication component 6012 may be dedicated to wired communications.
The electrical device 6000 may include battery/power circuitry 6014. The battery/power circuitry 6014 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the electrical device 6000 to an energy source separate from the electrical device 6000 (e.g., AC line power).
The electrical device 6000 may include a display device 6006 (or corresponding interface circuitry, as discussed above). The display device 6006 may include one or more embedded or wired or wirelessly connected external visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.
The electrical device 6000 may include an audio output device 6008 (or corresponding interface circuitry, as discussed above). The audio output device 6008 may include any embedded or wired or wirelessly connected external device that generates an audible indicator, such speakers, headsets, or earbuds.
The electrical device 6000 may include an audio input device 6024 (or corresponding interface circuitry, as discussed above). The audio input device 6024 may include any embedded or wired or wirelessly connected device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output). The electrical device 6000 may include a Global Navigation Satellite System (GNSS) device 6018 (or corresponding interface circuitry, as discussed above), such as a Global Positioning System (GPS) device. The GNSS device 6018 may be in communication with a satellite-based system and may determine a geolocation of the electrical device 6000 based on information received from one or more GNSS satellites, as known in the art.
The electrical device 6000 may include an other output device 6010 (or corresponding interface circuitry, as discussed above). Examples of the other output device 6010 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.
The electrical device 6000 may include an other input device 6020 (or corresponding interface circuitry, as discussed above). Examples of the other input device 6020 may include an accelerometer, a gyroscope, a compass, an image capture device (e.g., monoscopic or stereoscopic camera), a trackball, a trackpad, a touchpad, a keyboard, a cursor control device such as a mouse, a stylus, a touchscreen, proximity sensor, microphone, a bar code reader, a Quick Response (QR) code reader, electrocardiogram (ECG) sensor, PPG (photoplethysmogram) sensor, galvanic skin response sensor, any other sensor, or a radio frequency identification (RFID) reader.
The electrical device 6000 may have any desired form factor, such as a hand-held or mobile electrical device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a 2-in-1 convertible computer, a portable all-in-one computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra mobile personal computer, a portable gaming console, etc.), a desktop electrical device, a server, a rack-level computing solution (e.g., blade, tray or sled computing systems), a workstation or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a stationary gaming console, smart television, a vehicle control unit, a digital camera, a digital video recorder, a wearable electrical device or an embedded computing system (e.g., computing systems that are part of a vehicle, smart home appliance, consumer electronics product or equipment, manufacturing equipment). In some embodiments, the electrical device 6000 may be any other electronic device that processes data. In some embodiments, the electrical device 6000 may comprise multiple discrete physical components. Given the range of devices that the electrical device 6000 can be manifested as in various embodiments, in some embodiments, the electrical device 6000 can be referred to as a computing device or a computing system.
Illustrative examples of the technologies disclosed herein are provided below. An embodiment of the technologies may include any one or more, and any combination of, the examples described below.
Example 1 includes a device comprising a substrate comprising a first plurality of layers, wherein individual layers of the first plurality of layers comprises a plurality of conductive traces with a first height; and a second plurality of layers adjacent the first plurality of layers, wherein individual layers of the second plurality of layers comprises a plurality of conductive traces with a second height, wherein the second height is at least 1.5 times the first height, wherein, at an interface between the first plurality of layers and the second plurality of layers, a hybrid bond joins the first plurality of layers and the second plurality of layers, wherein the hybrid bond comprises one or more direct bonds between one or more conductive traces of the first plurality of layers and one or more conductive traces of the second plurality of layers.
Example 2 includes the subject matter of Example 1, and wherein the first plurality of layers comprises a substrate core, wherein one or more vias are defined in the substrate core, wherein individual vias of the one or more vias extend from a top surface of the substrate core to a bottom surface of the substrate core.
Example 3 includes the subject matter of any of Examples 1 and 2, and wherein individual vias of the one or more vias are filled with a magnetic lining surrounding a conductive material.
Example 4 includes the subject matter of any of Examples 1-3, and wherein the substrate does not include a substrate core, wherein one or more vias are defined through the first plurality of layers and the second plurality of layers, wherein individual vias of the one or more vias are filled with a magnetic material.
Example 5 includes the subject matter of any of Examples 1-4, and wherein one or more vias are defined in the substrate, wherein individual vias of the one or more vias are at least partially filled with a magnetic material.
Example 6 includes the subject matter of any of Examples 1-5, and wherein the magnetic material has a relative permeability over 100.
Example 7 includes the subject matter of any of Examples 1-6, and further including a die mounted on the substrate, wherein the substrate comprises one or more traces that are to provide power to the die.
Example 8 includes the subject matter of any of Examples 1-7, and wherein the magnetic material stabilizes a voltage and/or current provided by the one or more traces that are to provide power to the die.
Example 9 includes the subject matter of any of Examples 1-8, and wherein the hybrid bond further comprises a dielectric bond between a dielectric material of the first plurality of layers and a dielectric material of the second plurality of layers.
Example 10 includes the subject matter of any of Examples 1-9, and wherein the hybrid bond further comprises a bond between one or more conductive traces of the first plurality of layers and the dielectric material of the second plurality of layers.
Example 11 includes the subject matter of any of Examples 1-10, and wherein the dielectric material comprises carbon and hydrogen.
Example 12 includes the subject matter of any of Examples 1-11, and wherein the dielectric material comprises silicon and oxygen.
Example 13 includes the subject matter of any of Examples 1-12, and wherein the dielectric material comprises silicon and nitrogen.
Example 14 includes the subject matter of any of Examples 1-13, and wherein the first height is between 12 and 18 micrometers, wherein the second height is between 22 and 28 micrometers.
Example 15 includes the subject matter of any of Examples 1-14, and wherein individual conductive traces of the plurality of conductive traces of the first plurality of layers comprise copper, wherein individual conductive traces of the plurality of conductive traces of the second plurality of layers comprise copper.
Example 16 includes the subject matter of any of Examples 1-15, and further including a die mounted on the substrate, wherein the die is a processor die.
Example 17 includes the subject matter of any of Examples 1-16, and wherein the device is a compute device comprising a memory coupled to the processor die.
Example 18 includes a device comprising a substrate comprising a first plurality of layers, wherein individual layers of the first plurality of layers comprises a plurality of conductive traces with a first height; and a second plurality of layers adjacent the first plurality of layers, wherein individual layers of the second plurality of layers comprises a plurality of conductive traces with a second height, wherein the second height is at least 1.5 times the first height, means for joining the first plurality of layers and the second plurality of layers.
Example 19 includes the subject matter of Example 18, and wherein the means for joining the first plurality of layers and the second plurality of layers comprises a metal-metal fusion bond.
Example 20 includes the subject matter of any of Examples 18 and 19, and wherein the means for joining the first plurality of layers and the second plurality of layers comprises a copper-copper fusion bond.
Example 21 includes the subject matter of any of Examples 18-20, and further including a die mounted on the substrate, wherein the substrate comprises one or more traces that are to provide power to the die, wherein the substrate further comprises means for increasing an inductance of the one or more traces that are to provide power to the die.
Example 22 includes the subject matter of any of Examples 18-21, and wherein the first plurality of layers comprises a substrate core, wherein one or more vias are defined in the substrate core, wherein individual vias of the one or more vias extend from a top surface of the substrate core to a bottom surface of the substrate core.
Example 23 includes the subject matter of any of Examples 18-22, and wherein individual vias of the one or more vias are filled with a magnetic lining surrounding a conductive material.
Example 24 includes the subject matter of any of Examples 18-23, and wherein the substrate does not include a substrate core, wherein one or more vias are defined through the first plurality of layers and the second plurality of layers, wherein individual vias of the one or more vias are filled with a magnetic material.
Example 25 includes the subject matter of any of Examples 18-24, and wherein one or more vias are defined in the substrate, wherein individual vias of the one or more vias are at least partially filled with a magnetic material.
Example 26 includes the subject matter of any of Examples 18-25, and wherein the magnetic material has a relative permeability over 100.
Example 27 includes the subject matter of any of Examples 18-26, and further including a die mounted on the substrate, wherein the substrate comprises one or more traces that are to provide power to the die.
Example 28 includes the subject matter of any of Examples 18-27, and wherein the magnetic material stabilizes a voltage and/or current provided by the one or more traces that are to provide power to the die.
Example 29 includes the subject matter of any of Examples 18-28, and wherein the hybrid bond further comprises a dielectric bond between a dielectric material of the first plurality of layers and a dielectric material of the second plurality of layers.
Example 30 includes the subject matter of any of Examples 18-29, and wherein the hybrid bond further comprises a bond between one or more conductive traces of the first plurality of layers and the dielectric material of the second plurality of layers.
Example 31 includes the subject matter of any of Examples 18-30, and wherein the dielectric material comprises carbon and hydrogen.
Example 32 includes the subject matter of any of Examples 18-31, and wherein the dielectric material comprises silicon and oxygen.
Example 33 includes the subject matter of any of Examples 18-32, and wherein the dielectric material comprises silicon and nitrogen.
Example 34 includes the subject matter of any of Examples 18-33, and wherein the first height is between 12 and 18 micrometers, wherein the second height is between 22 and 28 micrometers.
Example 35 includes the subject matter of any of Examples 18-34, and wherein individual conductive traces of the plurality of conductive traces of the first plurality of layers comprise copper, wherein individual conductive traces of the plurality of conductive traces of the second plurality of layers comprise copper.
Example 36 includes the subject matter of any of Examples 18-35, and further including a die mounted on the substrate, wherein the die is a processor die.
Example 37 includes the subject matter of any of Examples 18-36, and wherein the device is a compute device comprising a memory coupled to the processor die.
Example 38 includes a method comprising forming a first plurality of layers for a substrate, wherein forming the first plurality of layers comprises forming a plurality of conductive traces with a first height; forming a second plurality of layers for the substrate, wherein forming the first plurality of layers comprises forming a plurality of conductive traces with a second height, wherein the second height is at least 1.5 times the first height; and joining the first plurality of layers to the second plurality of layers using hybrid bonding.
Example 39 includes the subject matter of Example 38, and wherein forming the first plurality of layers comprises forming the first plurality of layers on a substrate core.
Example 40 includes the subject matter of any of Examples 38 and 39, and further including forming one or more vias in the substrate core; forming a magnetic lining in the substrate core; and filling the magnetic lining with a conductive material.
Example 41 includes the subject matter of any of Examples 38-40, and wherein forming the first plurality of layers comprises forming the first plurality of layers on a glass carrier; and separating the first plurality of layers from the glass carrier.
Example 42 includes the subject matter of any of Examples 38-41, and further including drilling one or more vias through the first plurality of layers; filling the one or more vias through the first plurality of layers with a magnetic material; drilling one or more vias through the second plurality of layers; and filling the one or more vias through the second plurality of layers with a magnetic material.
Example 43 includes the subject matter of any of Examples 38-42, and wherein the first plurality of layers comprises a substrate core, wherein one or more vias are defined in the substrate core, wherein individual vias of the one or more vias extend from a top surface of the substrate core to a bottom surface of the substrate core.
Example 44 includes the subject matter of any of Examples 38-43, and wherein individual vias of the one or more vias are filled with a magnetic lining surrounding a conductive material.
Example 45 includes the subject matter of any of Examples 38-44, and wherein the substrate does not include a substrate core, wherein one or more vias are defined through the first plurality of layers and the second plurality of layers, wherein individual vias of the one or more vias are filled with a magnetic material.
Example 46 includes the subject matter of any of Examples 38-45, and wherein one or more vias are defined in the substrate, wherein individual vias of the one or more vias are at least partially filled with a magnetic material.
Example 47 includes the subject matter of any of Examples 38-46, and wherein the magnetic material has a relative permeability over 100.
Example 48 includes the subject matter of any of Examples 38-47, and wherein a die is mounted on the substrate, wherein the substrate comprises one or more traces that are to provide power to the die.
Example 49 includes the subject matter of any of Examples 38-48, and wherein the magnetic material stabilizes a voltage and/or current provided by the one or more traces that are to provide power to the die.
Example 50 includes the subject matter of any of Examples 38-49, and wherein the hybrid bond comprises a dielectric bond between a dielectric material of the first plurality of layers and a dielectric material of the second plurality of layers.
Example 51 includes the subject matter of any of Examples 38-50, and wherein the hybrid bond further comprises a bond between one or more conductive traces of the first plurality of layers and the dielectric material of the second plurality of layers.
Example 52 includes the subject matter of any of Examples 38-51, and wherein the dielectric material comprises carbon and hydrogen.
Example 53 includes the subject matter of any of Examples 38-52, and wherein the dielectric material comprises silicon and oxygen.
Example 54 includes the subject matter of any of Examples 38-53, and wherein the dielectric material comprises silicon and nitrogen.
Example 55 includes the subject matter of any of Examples 38-54, and wherein the first height is between 12 and 18 micrometers, wherein the second height is between 22 and 28 micrometers.
Example 56 includes the subject matter of any of Examples 38-55, and wherein individual conductive traces of the plurality of conductive traces of the first plurality of layers comprise copper, wherein individual conductive traces of the plurality of conductive traces of the second plurality of layers comprise copper.
