Patent Grant
9928883
The subject matter of the present application relates to microelectronic packages, circuit panels, and microelectronic assemblies incorporating one or more microelectronic package and a circuit panel.
Semiconductor chips are commonly provided as individual, prepackaged units. A standard chip has a flat, rectangular body with a large front face having contacts connected to the internal circuitry of the chip. Each individual chip typically is contained in a package having external terminals connected to the contacts of the chip. In turn, the terminals, i.e., the external connection points of the package, are configured to electrically connect to a circuit panel, such as a printed circuit board. In many conventional designs, the chip package occupies an area of the circuit panel considerably larger than the area of the chip itself. As used in this disclosure with reference to a flat chip having a front face, the “area of the chip” should be understood as referring to the area of the front face.
Size is a significant consideration in any physical arrangement of chips. The demand for more compact physical arrangements of chips has become even more intense with the rapid progress of portable electronic devices. Merely by way of example, devices commonly referred to as “smart phones” integrate the functions of a cellular telephone with powerful data processors, memory, and ancillary devices such as global positioning system receivers, electronic cameras, and local area network connections along with high-resolution displays and associated image processing chips. Such devices can provide capabilities such as full internet connectivity, entertainment including full-resolution video, navigation, electronic banking and more, all in a pocket-size device.
Complex portable devices require packing numerous chips into a small space. Moreover, some of the chips have many input and output connections, commonly referred to as “I/Os.” These I/Os must be interconnected with the I/Os of other chips. The components that form the interconnections should not greatly increase the size of the assembly. Similar needs arise in other applications as, for example, in data servers such as those used in internet search engines where increased performance and size reduction are needed.
Semiconductor chips containing memory storage arrays, particularly dynamic random access memory chips (DRAMs) and flash memory chips, are commonly packaged in single- or multiple-chip packages and assemblies. Each package has many electrical connections for carrying signals, power, and ground between terminals and the chips therein. The electrical connections can include different kinds of conductors such as horizontal conductors, e.g., traces, beam leads, etc., that extend in a horizontal direction relative to a contact-bearing surface of a chip, vertical conductors such as vias, which extend in a vertical direction relative to the surface of the chip, and wire bonds that extend in both horizontal and vertical directions relative to the surface of the chip.
Conventional microelectronic packages can incorporate a microelectronic element that is configured to predominantly provide memory storage array function, i.e., a microelectronic element that embodies a greater number of active devices to provide memory storage array function than any other function. The microelectronic element may be or may include a DRAM chip, or a stacked electrically interconnected assembly of such semiconductor chips.
In light of the foregoing, certain improvements in the design of microelectronic packages and microelectronic assemblies including circuit panels and/or other microelectronic components can be made in order to improve the functional flexibility or electrical performance thereof, particularly in microelectronic packages and microelectronic assemblies having circuit panels and/or other microelectronic components to which microelectronic packages can be mounted and electrically interconnected with one another.
A microelectronic package can include, a substrate having first and second opposed surfaces, first, second, and third microelectronic elements each having a surface facing the first surface of the substrate, terminals exposed at the second surface and configured for connecting the microelectronic package to at least one component external to the microelectronic package, and leads electrically connected between contacts of each microelectronic element and the terminals. The substrate can have first and second opposed edges extending between the first and second surfaces, and first, second, and third spaced-apart apertures each extending between the first and second surfaces. The apertures can have first, second, and third parallel axes each extending in directions of the lengths of the apertures, respectively. The third axis can be disposed between the first and second axes. The second surface can have a central region between the first and second axes.
The first, second, and third microelectronic elements can each have contacts exposed at the surface of the respective microelectronic element and aligned with one of the first, second, or third apertures, respectively. Each microelectronic element can have memory storage array function. Each lead can have a portion aligned with at least one of the apertures. The terminals can include first terminals configured to carry address information. The first terminals can include first and second sets thereof. The first set of the first terminals can be electrically connected with the first and third microelectronic elements and not electrically connected with the second microelectronic element. The second set of the first terminals can be electrically connected with the second microelectronic element and not electrically connected with the first or third microelectronic elements.
In one embodiment, the terminals can include second terminals configured to carry second information. The second information can be other than the information carried by the first terminals. The second information can include data signals. The second terminals can include first, second, and third sets thereof each connected to only one of the first, second, and third microelectronic elements. In a particular example, the third set of the second terminals can be electrically connected with the third microelectronic element. The third set of the second terminals can include first and second groups disposed in the central region on first and second opposite sides of the third aperture. In an exemplary embodiment, the second surface of the substrate can have first and second peripheral regions between the central region and the respective first and second edges. The first and second sets of second terminals can be electrically connected with the respective first and second microelectronic elements and can be disposed in the respective first and second peripheral regions.
In one example, the signal assignments of corresponding ones of the second terminals in the first and second sets can be symmetric about a theoretical fourth axis between the first and second sets. The fourth axis can be parallel to the first, second, and third axes. In a particular embodiment, the fourth axis can be located within one ball pitch of the terminals of a centerline of the substrate located equidistant between the first and second opposed edges. In one embodiment, the first and second sets of the second terminals can be disposed at positions within respective first and second grids, and columns of the second terminals in the first and second grids can extend in a direction parallel to the first and second opposed edges of the substrate. In a particular example, the first terminals can be configured to carry all of the address information usable by circuitry within the microelectronic package. In an exemplary embodiment, the first set of first terminals and the second set of first terminals can each be configured to carry all of the same signals.
In one example, the signal assignments of corresponding ones of the first terminals in the first and second sets can be symmetric about a theoretical fourth axis between the first and second sets. The fourth axis can be parallel to the first, second, and third axes. In a particular embodiment, the fourth axis can be located within one ball pitch of the terminals of a centerline of the substrate located equidistant between the first and second opposed edges. In one embodiment, the first and second sets of the first terminals can be disposed at positions within respective first and second grids, and columns of the first terminals in the first and second grids can extend in a direction parallel to the first and second opposed edges of the substrate. In a particular example, each of the microelectronic elements can embody a greater number of active devices to provide memory storage array function than any other function.
In an exemplary embodiment, the surface of each of the first and second microelectronic elements can confront the first surface of the substrate, and the surface of the third microelectronic element can at least partially overlie a rear surface of at least one of the first and second microelectronic elements. In one example, the surfaces of all of the microelectronic elements can be arranged in a single plane parallel to the first surface of the substrate. In a particular embodiment, at least some of the leads can include wire bonds extending through at least one of the apertures. In one embodiment, a system can include a microelectronic package as described above and one or more other electronic components electrically connected to the microelectronic package. In a particular example, the system can also include a housing, the microelectronic package and the one or more other electronic components being assembled with the housing.
A microelectronic assembly can include a circuit panel having first and second opposed surfaces and an address bus comprising a plurality of signal conductors electrically connected with a plurality of mutually exclusive connection regions. Each connection region can include first panel contacts and second panel contacts electrically coupled with the first panel contacts disposed at the first and second surfaces, respectively. The microelectronic assembly can also include first and second microelectronic packages having first terminals mounted to the first panel contacts and the second panel contacts, respectively. Each microelectronic package can have first, second, and third microelectronic elements therein.
Each microelectronic element may be electrically coupled to the address bus via only one of the connection regions. The first and third microelectronic elements of the first microelectronic package and the second microelectronic element of the second microelectronic package may be electrically coupled to the address bus only at a first one of the connection regions. The second microelectronic elements of the first microelectronic package and the first and third microelectronic elements of the second microelectronic package may be electrically coupled to the address bus only at a second one of the connection regions.
In one embodiment, the address bus can be configured to carry all address signals usable by circuitry within the first and second microelectronic packages. In a particular example, each of the microelectronic elements can embody a greater number of active devices to provide memory storage array function than any other function. In an exemplary embodiment, the first terminals of the first and second microelectronic packages can be arranged at positions of first and second grids, and the first and second grids can be aligned with one another in x and y orthogonal directions parallel to the first and second surfaces of the circuit panel. The alignment can be within a distance equal to a minimum pitch between adjacent terminals of the grids.
In one example, the microelectronic assembly can also include third and fourth microelectronic packages having first terminals mounted to the first panel contacts and the second panel contacts, respectively. Each of the third and fourth microelectronic packages can have first, second, and third microelectronic elements therein. Each microelectronic element can be electrically coupled to the address bus via only one of the connection regions. The first and third microelectronic elements of the third microelectronic package and the second microelectronic element of the fourth microelectronic package can be electrically coupled to the address bus only at a third one of the connection regions. The second microelectronic element of the third microelectronic package and the first and third microelectronic elements of the fourth microelectronic package can be electrically coupled to the address bus only at a fourth one of the connection regions.
An electrical characteristic between the first and second connection regions can be within a same tolerance of the electrical characteristic between the second and third connection regions. In a particular embodiment, the electrical characteristic can be an electrical trace length. In one embodiment, the electrical characteristic can be an electrical propagation delay. In a particular example, the electrical characteristic can be a characteristic impedance of the signal conductors. In an exemplary embodiment, the electrical characteristic can be a difference in an electrical load applied to the address bus from the microelectronic elements connected with the respective connection region.
A microelectronic assembly can include a circuit panel having first and second opposed surfaces and an address bus comprising a plurality of signal conductors electrically connected with a plurality of mutually exclusive connection regions. Each connection region can include either or both of first panel contacts and second panel contacts electrically coupled with at least some of the plurality of signal conductors and disposed at the first and second surfaces, respectively. The microelectronic assembly can also include first and second microelectronic packages having first terminals mounted to the first panel contacts and the second panel contacts, respectively. Each microelectronic package can have first, second, and third microelectronic elements therein.
Each microelectronic element may be electrically coupled to the address bus via only one of the connection regions. The first and third microelectronic elements of the first microelectronic package may be electrically coupled to the address bus only at a first one of the connection regions. The second microelectronic element of the first microelectronic package and the second microelectronic element of the second microelectronic package may be electrically coupled to the address bus only at a second one of the connection regions. The first and third microelectronic elements of the second microelectronic package may be electrically coupled to the address bus only at a third one of the connection regions.
In one embodiment, the address bus can be configured to carry all address signals usable by circuitry within the first and second microelectronic packages. In a particular example, each of the microelectronic elements can embody a greater number of active devices to provide memory storage array function than any other function. In an exemplary embodiment, an electrical characteristic between the first and second connection regions can be within a same tolerance of the electrical characteristic between the second and third connection regions. In one example, the electrical characteristic can be an electrical trace length. In a particular embodiment, the electrical characteristic can be an electrical propagation delay. In one embodiment, the electrical characteristic can be a characteristic impedance of the signal conductors. In a particular example, the electrical characteristic can be a difference in an electrical load applied to the address bus from the microelectronic elements connected with the respective connection region.
In an exemplary embodiment, the microelectronic assembly can also include third and fourth microelectronic packages having first terminals mounted to the first panel contacts and the second panel contacts, respectively. Each of the third and fourth microelectronic packages can have first, second, and third microelectronic elements therein. Each microelectronic element can be electrically coupled to the address bus via only one of the connection regions. The first and third microelectronic elements of the third microelectronic package can be electrically coupled to the address bus only at a fourth one of the connection regions. The second microelectronic element of the third microelectronic package and the second microelectronic element of the fourth microelectronic package can be electrically coupled to the address bus only at a fifth one of the connection regions. The first and third microelectronic elements of the fourth microelectronic package may not be electrically coupled to the address bus. In one example, the first and third microelectronic elements of the fourth microelectronic package can be electrically coupled to third panel contacts disposed at the second surface of the circuit panel, and the third panel contacts may not be connected in any electrical path to the address bus within the microelectronic assembly.
In some cases, the dielectric element 20 can consist essentially of a material having a low coefficient of thermal expansion (“CTE”) in a plane of the substrate (in a direction parallel to the first surface 21 of the substrate), i.e., a CTE of less than 12 parts per million per degree Celsius (hereinafter, “ppm/° C.”), such as a semiconductor material e.g., silicon, or a dielectric material such as ceramic material or silicon dioxide, e.g., glass. Alternatively, the substrate 20 may include a sheet-like substrate that can consist essentially of a polymeric material such as polyimide, epoxy, thermoplastic, thermoset plastic, or other suitable polymeric material or that includes or consists essentially of composite polymeric-inorganic material such as a glass reinforced structure of BT resin (bismaleimide triazine) or epoxy-glass, such as FR-4, among others. In one example, such a substrate 20 can consist essentially of a material having a CTE of less than 30 ppm/° C. in the plane of the dielectric element, i.e., in a direction along its surface.
In
A statement that one feature is disposed at a greater height “above a surface” than another feature means that the one feature is at a greater distance in the same orthogonal direction away from the surface than the other feature. Conversely, a statement that one feature is disposed at a lesser height “above a surface” than another feature means that the one feature is at a smaller distance in the same orthogonal direction away from the surface than the other feature.
First, second, and third apertures 26a, 26b, and 26c can extend between the first and second surfaces 21, 22 of the dielectric element 20. As can be seen in
The dielectric element 20 can have a plurality of terminals 25, e.g., conductive pads, lands, or conductive posts at the second surface 22 of the dielectric element 20. As used in this disclosure with reference to a component, e.g., an interposer, microelectronic element, circuit panel, substrate, etc., a statement that an electrically conductive element is “at” a surface of a component indicates that, when the component is not assembled with any other element, the electrically conductive element is available for contact with a theoretical point moving in a direction perpendicular to the surface of the component toward the surface of the component from outside the component. Thus, a terminal or other conductive element which is at a surface of a substrate may project from such surface; may be flush with such surface; or may be recessed relative to such surface in a hole or depression in the substrate.
The terminals 25 can be configured for connecting the microelectronic package 10 to at least one component external to the microelectronic package. The terminals 25 can function as endpoints for the connection of the microelectronic package 10 with corresponding electrically conductive elements of an external component such as the contacts of a circuit panel 60, e.g., printed wiring board, flexible circuit panel, socket, other microelectronic assembly or package, interposer, or passive component assembly, among others. In one example, such a circuit panel can be a motherboard or DIMM module board. In a particular example, the circuit panel 60 can include an element having a CTE less than 30 ppm/° C. In one embodiment, such an element can consist essentially of semiconductor, glass, ceramic or liquid crystal polymer material.
In one example, terminals 25a that are disposed in the central region 23 of the second surface 22 of the dielectric element 20 can be configured to carry address signals. These terminals are referred to herein as “first terminals.” The first terminals 25a comprise terminals configured to carry address information. For example, when the microelectronic elements 30a, 30b, 30c include or are DRAM semiconductor chips, each set 15a, 15b of first terminals 25a can be configured to carry sufficient address information transferred to the microelectronic package 10 that is usable by circuitry within the package, e.g., row address and column address decoders, and bank selection circuitry of one or more of the microelectronic elements 30 to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within a microelectronic element in the package. In a particular embodiment, the first terminals 25a can be configured to carry all the address information used by such circuitry within the microelectronic package 10 to determine an addressable memory location within such memory storage array. In one example, the first terminals 25a can be configured to carry all of the address information usable by circuitry within the microelectronic package 10.
In one example, the first terminals 25a can be configured to carry each of a group of signals of a command-address bus of the microelectronic element; i.e., command signals, address signals, bank address signals, and clock signals that are transferred to the microelectronic package, wherein the command signals include write enable, row address strobe, and column address strobe signals, and the clock signals are clocks used for sampling the address signals. While the clock signals can be of various types, in one embodiment, the clock signals carried by these terminals can be one or more pairs of differential clock signals received as differential or true and complement clock signals.
In a particular example in which the microelectronic elements 30a, 30b, and 30c include DDR3 type chips, the command signals transferred to the microelectronic elements can include write enable (“WE”), row address strobe (“RAS”), and column address strobe signals (“CAS”). In one example in which the microelectronic elements 30a, 30b, and 30c include DDR4 type chips, the command signals transferred to the microelectronic elements can include write enable, row address strobe, column address strobe, activate (“ACT”), and parity (“PAR”) signals. Such contacts and/or terminals in packages containing DDR3 or DDR4 chips that are configured to receive the aforementioned command signals can be included in any of the embodiments described herein.
In a particular embodiment, the first set 15a of first terminals 25a can be configured to carry all the address information used by the circuitry within the microelectronic package 10 to determine an addressable memory location within the first and third microelectronic elements 30a, 30c and the second set 15b of first terminals 25a can be configured to carry all the address information used by the circuitry within the microelectronic package 10 to determine an addressable memory location within the second microelectronic element 30b. In one example, each set 15a, 15b of first terminals 125a can be configured to carry each of a group of signals of a command-address bus of the corresponding microelectronic elements; i.e., command signals, address signals, bank address signals, and clock signals that are transferred to the microelectronic package 10. In some examples (e.g.,
In one example, as can also be seen in
As further seen in
In one example, as can be seen in
In one embodiment, the first and second sets 17a, 17b of second terminals 25b can be electrically connected with the respective first and second microelectronic elements 30a, 30b, and can be disposed in the respective first and second peripheral regions 28a, 28b. In one example, the third set 17c of the second terminals 25b can be electrically connected with the third microelectronic element 30c, and the third set of second terminals can include first and second groups 17d and 17e disposed in the central region 23 of the second surface 22 of the substrate 20 on first and second opposite sides of the third aperture 26c.
In one example, as can also be seen in
Typically, the second terminals are configured to carry all bi-directional data signals for writing of data to and for reading of data from random access addressable locations of at least a main memory storage array within each DRAM microelectronic element. However, in some cases, some of the second terminals can carry uni-directional data signals for input to a microelectronic element for writing of data to a memory storage array, and some of the first terminals can carry uni-directional data signals output from a microelectronic element based on data read from a memory storage array.
In one example, the second terminals 25b can be configured to carry one or more of data strobe signals, or other signals or reference potentials such as chip select, reset, power supply voltages, e.g., Vdd, Vddq, and ground, e.g., Vss and Vssq. The second terminals 25b may include terminals assigned to carry data signals and also data masks and “on die termination” (ODT) signals used to turn on or off parallel terminations to termination resistors.
The microelectronic package 10 can include joining elements 11 attached to the terminals 25 for connection with an external component. The joining elements 11 can be, for example, masses of a bond metal such as solder, tin, indium, a eutectic composition or combination thereof, or another joining material such as an electrically conductive paste, an electrically conductive adhesive or electrically conductive matrix material or a combination of any or all of such bond metals or electrically conductive materials. In a particular embodiment, the joints between the terminals 25 and contacts of an external component (e.g., the circuit panel 60) can include an electrically conductive matrix material such as described in U.S. Pat. Nos. 8,890,304 and 9,117,811, the disclosures of which are hereby incorporated herein by reference. In a particular embodiment, the joints can have a similar structure or be formed in a manner as described therein.
The microelectronic package 10 can comprise a plurality of microelectronic elements 30 (e.g., 30a, 30b, and 30c) each having a front face 31 facing the first surface 21 of the dielectric element 20. Although the microelectronic elements 30 are shown in
The front surfaces 31 of the first and second microelectronic elements 30a, 30b can confront the first surface 21 of the substrate 20, and the front surface of the third microelectronic element 30c can at least partially overlie a rear surface 33 of at least one of the first and second microelectronic elements. In the example shown in
One or more adhesive layers can be positioned between the front surface 31 of the first microelectronic element 30a and the first surface 21 of the dielectric element 20, between the front surface of the second microelectronic element 30b and the first surface of the dielectric element, and/or between the front surface of the third microelectronic element 30c and the rear surface 33 of one or both of the first and second microelectronic elements.
In one example, the microelectronic elements 30 can each comprise a memory storage element such as a dynamic random access memory (“DRAM”) storage array or that is configured to predominantly function as a DRAM storage array (e.g., a DRAM integrated circuit chip). As used herein, a “memory storage element” refers to a multiplicity of memory cells arranged in an array, together with circuitry usable to store and retrieve data therefrom, such as for transport of the data over an electrical interface. In one example, each of the microelectronic elements 30 can have memory storage array function. In a particular embodiment, each microelectronic element 30 can embody a greater number of active devices to provide memory storage array function than any other function.
As further seen in
The central region 37 is disposed between peripheral regions 43a, and 43b, each of which lies between the central region 37 and a respective peripheral edge 32a or 32b, and each peripheral region also occupying an area covering a respective third 41a or 41b of the distance 38 between the opposite peripheral edges 32a, 32b. In the particular example shown in
The microelectronic elements 30 in a microelectronic package 10 can be configured in accordance with one of several different standards, e.g., standards of JEDEC, which specify the type of signaling that semiconductor chips (such as the microelectronic elements 30) transmit and receive through the contacts 35 thereof.
Thus, in one example, each of the microelectronic elements 30 can be of DDRx type, i.e., configured in accordance with one of the JEDEC double data rate DRAM standards DDR3, DDR4, or one or more of their follow-on standards (collectively, “DDRx”). Each DDRx type microelectronic element can be configured to sample the command and address information coupled to the contacts thereof at a first sampling rate, such as once per clock cycle (e.g., on the rising edge of the clock cycle). In particular examples, the DDRx type microelectronic elements can have four, eight or sixteen contacts used for transmitting and receiving bi-directional data signals, each such bi-directional signal referred to as a “DQ” signal. Alternatively, the first terminals of a package can be configured to carry uni-directional data signals such as data signals or “D” signals input to the package and data signals “Q” output from the package, or can be configured to carry a combination of bi-directional and uni-directional data signals.
In another example, each of the microelectronic elements 30 can be of LPDDRx type, i.e., configured in accordance with one of the JEDEC low power double data rate DRAM standards LPDDR3 or one or more of its follow-on standards (collectively, “LPDDRx”). LPDDRx type DRAM chips are available which have 32 contacts assigned to carry DQ signals. There are other differences as well. Each contact 35 on an LPDDRx type DRAM chip may be used to simultaneously carry two different signals in interleaved fashion. For example, each contact 35 on such DRAM chip can be assigned to carry one signal which is sampled on the rising edge of the clock cycle and can also be assigned to carry another signal that is sampled on the falling edge of the clock cycle.
Thus, in LPDDRx type chips, each microelectronic element 30a, 30b, 30c can be configured to sample the command and address information input to the contacts thereof at a second sampling rate, such as twice per clock cycle (e.g., on both the rising edge and on the falling edge of the clock cycle). Accordingly, the number of contacts on the LPDDRx DRAM chip that carry address information or command-address bus information can also be reduced. In a particular example of LPDDRx type chips, one or more of the contacts 35 of each microelectronic element 30a, 30b, 30c can be configured to carry address information at one edge of the clock cycle and command information at another edge of the clock cycle, such that a single contact can be used to alternatingly receive command and address information. Such contacts and/or terminals that are configured to alternatingly receive command and address information can be included in any of the embodiments described herein.
Electrical connections between the contacts 35 and the terminals 25 can include leads, e.g., wire bonds 40, or other possible structure in which at least portions of the leads are aligned with at least one of the apertures 26. For example, as seen in
The microelectronic package 10 can also include an encapsulant 50 that can optionally cover, partially cover, or leave uncovered the rear surfaces 33 of the microelectronic elements 30. For example, in the microelectronic package 10 shown in
In the embodiment of
For example, a first terminal 25a in a first set 15a of the first terminals disposed in the central region 23 of the second surface 22 of the dielectric element 20 can be electrically coupled with a conductive contact 35 of each of the first and third microelectronic elements 30a and 30c through conductive traces, conductive elements 24, e.g., bond pads, and wire bonds 40 joined to corresponding ones of the conductive elements and the contacts. A first terminal 25a in a second set 15b of the first terminals disposed in the central region 23 of the second surface 22 of the dielectric element 20 can be electrically coupled with a conductive contact 35 of only the second microelectronic element 30b through conductive traces, a conductive element 24, e.g., a bond pad, and a wire bond 40 joined to corresponding ones of the conductive elements and the contacts.
In one example, the first group 15a of first terminals 25a disposed on a first side of a theoretical axis 29d can have signal assignments that are symmetric about the axis 29d with the signal assignments of the second group 15b of first terminals that are disposed on a second side of the axis 29d. The theoretical axis 29d can extend parallel to the longitudinal axis 29 of each of the apertures 26 and is disposed between the proximate edges of the respective apertures. In the example shown in
Typically, the theoretical axis 29d is disposed at or near the median distance between the proximate edges of the first and second apertures 26a, 26b. “Symmetric” as used herein in connection with signal assignments of terminals for carrying address information means that the signal assignment of a terminal on a first side of the theoretical axis has a name and numerical weight which are the same as that of another terminal on an opposite side of the axis at a position symmetric about the axis from the terminal on the first side. The “numerical weight” of the address information assigned to a given terminal refers to the place of that address information within the places of an address that is specified by the address information. For example, an address can be specified by 20 address bits A0 . . . A19. Each bit has a numerical weight, from the highest-ordered address information bit A19, which has a numerical weight of 19 representing 2^19 (2 to the power of 19), to the lowest-ordered address information bit A0, which has a numerical weight of zero representing 2^0 (2 to the power of zero), which is the l's place of the address.
In a particular embodiment, the first and second groups 15a, 15b of first terminals 25a of the microelectronic package 10 can be configured to have modulo-X symmetry about the theoretical axis 29d. Microelectronic packages having groups of address and/or data terminals having modulo-X symmetry are shown and described in U.S. Pat. Nos. 8,441,111 and 9,123,555, which are hereby incorporated by reference herein in their entireties.
As can be seen in
Stated another way, in the microelectronic package 10, the first set 15a of the first terminals 25a are electrically connected with the first and third microelectronic elements 30a, 30c and not electrically connected with the second microelectronic element 30b, and the second set 15b of the first terminals are electrically connected with the second microelectronic element and not electrically connected with the first or third microelectronic elements. In this way, the first and third microelectronic elements 30a, 30c share an electrical connection 2a to the first set 15a of the first terminals 25a, and the second microelectronic element 30b has an unshared independent electrical connection 2b to a second set 15b of the first terminals.
In one potential example of the terminal configuration of the microelectronic package 10 described above,
In another potential example of the terminal configuration of the microelectronic package 10 described above,
Although the microelectronic elements 30 are shown in
In another embodiment, a variation of the microelectronic package 10 can have microelectronic elements each bearing element contacts a front face thereof, the front faces facing toward the first surface of the substrate, with the element contacts facing and joined to substrate contacts at the first surface of the substrate by conductive joining material extending therebetween. The substrate contacts can be electrically connected with the terminals at the second surface of the substrate.
In yet another variation of the of the microelectronic package 10, the substrate can be omitted, such that the microelectronic package 10 can be in form of microelectronic elements 30 having packaging structure that includes an electrically conductive redistribution layer overlying the front face 31 of one or more of the microelectronic elements. The redistribution layer has electrically conductive metallized vias extending through a dielectric layer of the package to the element contacts 35 of the microelectronic elements 30. The redistribution layer may include the terminals 25 and traces electrically connected with the terminals, such that the terminals are electrically connected with the element contacts, such as through the metallized vias or through metallized vias and electrically conductive traces. In this case, the package can be referred to as a “wafer-level package having a redistribution layer thereon.” In an additional variation, such a microelectronic package having a redistribution layer thereon as described above can have one or more columns of the terminals 25 disposed on areas of the dielectric layer that extend laterally beyond one or more edges of the microelectronic elements. In this case, the package can be referred to as a “fan-out wafer-level package having a redistribution layer thereon.”
Referring to
Each of the microelectronic packages 10 of the microelectronic assembly 1 can have a similar structure that includes first, second, and third microelectronic elements 30 as described above with reference to
In the examples of
The microelectronic assembly 1 can include an address bus or command-address bus 3 that can comprise a plurality of signal conductors each passing sequentially through connection regions 70 of the circuit panel 60 such as first, second, third, fourth, fifth, and sixth connection regions 71, 72, 73, 74, 75, and 76. The bus 3 can extend within or on a support, which may be a portion of the circuit panel 60. The bus 3 can comprise a plurality of signal conductors for transmitting address signals or address and command signals. The circuit panel 60 can have conductive panel contacts 65 at a surface of the support, such as the first panel contacts 65a at the first surface 61 of the circuit panel and the second panel contacts 65b at the second surface 62 of the circuit panel. The microelectronic packages 10 can be mounted to the panel contacts 65, for example, by joining elements 11 that can extend between the terminals 25 and the panel contacts.
The address bus or command-address bus 3 can comprise a plurality of signal conductors electrically connected with a plurality of mutually exclusive connection regions 71-76. As used herein, “mutually exclusive” connection regions are not electrically connected to one another within the circuit panel 60. In the example shown in
In one example, the address bus 3 can be configured to carry all address signals usable by circuitry within the microelectronic packages 30. In a particular example (e.g., DDR3 chips), the address bus 3 can be configured to carry all command signals transferred to each of the microelectronic packages 30, the command signals being write enable, row address strobe, and column address strobe signals. In one embodiment (e.g., DDR4 chips), all of the command signals transferred to each of the microelectronic packages 30 can be write enable, row address strobe, column address strobe, activate, and parity signals. The first terminals 25a of each of the microelectronic packages 30 can be configured to carry all of the address signals usable by circuitry within the respective microelectronic package.
On the circuit panel 60, e.g., a printed circuit board, module card, etc., these above-noted signals of the command-address bus: i.e., command signals, address signals, bank address signals, and clock signals, can be bussed to multiple microelectronic packages 10 that are connected thereto in parallel, for example, to first and second microelectronic packages 10a, 10b mounted to opposite surfaces of the circuit panel in a clamshell configuration.
In one embodiment, the first terminals 25a of the respective microelectronic packages 10 can be functionally and mechanically matched, such that each microelectronic package can have the same pattern of first terminals at the second surface 22 of the substrate 20 of the respective microelectronic package with the same function, although the particular dimensions of the length, width, and height of each microelectronic package can be different than that of the other microelectronic packages.
In one example, each of the sets or groups 15a and 15b of the first terminals 25a of each microelectronic package 30 can be configured to carry all of the same address signals. As can be seen in
As can be seen in
For example, as shown in
Likewise, the second connection region 72 is electrically connected only with memory array U2 of the first microelectronic package 10a (via the second set 15b of the first terminals 25a) and with memory arrays U3 and U4 of the second microelectronic package 10b (via the first set 15a of the first terminals). Therefore, the second connection region 72 is electrically connected only with the second microelectronic element 30b of the first microelectronic package 10a and with the first and third microelectronic elements 30a, 30c of the second microelectronic package 10b.
Stated another way, the first and third microelectronic elements 30a, 30c of the first microelectronic package 10a and the second microelectronic element 30b of the second microelectronic package 10b can be electrically coupled to the address bus 3 only at a first one of the connection regions 71, and the second microelectronic element 30b of the first microelectronic package 10a and the first and third microelectronic elements 30a, 30c of the second microelectronic package 10b are electrically coupled to the address bus only at a second one of the connection regions 72. In one example, the first and third microelectronic elements 30a, 30c of the third microelectronic package 10c and the second microelectronic element 30b of the fourth microelectronic package 10d can be electrically coupled to the address bus 3 only at a third one of the connection regions 73, and the second microelectronic element 30b of the third microelectronic package 10c and the first and third microelectronic elements 30a, 30c of the fourth microelectronic package 10d are electrically coupled to the address bus only at a fourth one of the connection regions 74.
In some examples, the microelectronic assembly 1 can further include an optional controller package 4 electrically coupled to the address bus or command-address bus 3. The controller package 4 can include a controller element configured to control generation of address signals for transmission on the bus 3. In one example, first and second microelectronic packages 10a, 10b can overlie respective first and second areas of a same surface of the support or circuit panel 60, and the controller package 4 can overlie a third area of the circuit panel. Such a controller package 4 may be included in embodiments of the microelectronic assembly 1 where the assembly is a registered DIMM. In other embodiments, the microelectronic assembly may not include the controller package 4 where the assembly is a DIMM without registers, e.g., UDIMM (unregistered DIMM).
As illustrated in
The at least one direction D3 can be transverse or orthogonal to a direction D2 (
In the embodiment shown in
The first terminals 25a of the microelectronic packages 10a and 10c can be electrically coupled to first, second, third, and fourth sets 66, 67, 68, and 69 of the first panel contacts 65a. In turn, the first, second, third, and fourth sets 66, 67, 68, and 69 of the first panel contacts 65a can be electrically coupled to the signal conductors of the bus 3. In one example (e.g., DDR3 chips), each of the first, second, third, and fourth sets 66, 67, 68, and 69 of first panel contacts 65a can be configured to carry address information usable by circuitry within the microelectronic packages 10 and command signals transferred to the microelectronic packages, the command signals being write enable, row address strobe, and column address strobe signals. In one embodiment (e.g., DDR4 chips), the command signals transferred to the microelectronic packages can be write enable, row address strobe, column address strobe, activate, and parity signals.
Each of the memory arrays U0, U1, U2, U6, U7, and U8 of the microelectronic packages 10a, 10c can be electrically coupled to the signal conductors of the bus 3 at one of the connection regions 71, 72, 73, 74 via a set 66, 67, 68, 69 of the first panel contacts 65a and via packaging structure (e.g., first terminals 25a) of the respective microelectronic package for receiving address signals or address and command signals.
In the embodiment shown in
In the example shown in
In one embodiment, the geometric centers G1, G2, G3, and G4 of the respective first, second, third, and fourth sets 66, 67, 68, 69 of the first panel contacts 65a can be equally spaced from one another along a common theoretical axis A1 extending parallel to the first surface 61 of the circuit panel 60. As used herein, a statement that elements are “equally spaced” with respect one another along a common theoretical axis means that the actual difference in spacing between adjacent ones of the elements is within a typical manufacturing tolerance known to one skilled in the relevant art.
In the embodiment of
In one embodiment, each of the first, second, and third connection regions 71, 72, 73 can have respective first, second, and third relative electrical lengths (i.e., electrical trace lengths) from the respective second, third, and fourth connection regions 72, 73, 74, and any difference among the first, second, and third relative electrical lengths can fall within a same tolerance, for example, a same tolerance of ±0.5 mm, or in a particular embodiment, a same tolerance of ±1% of any one of the relative electrical lengths. In a particular embodiment, an electrical trace length between the first and second connection regions 71, 72 can be within a same tolerance of the electrical trace length between the second and third connection regions 72, 73.
In a particular embodiment, each of the second, third, and fourth connection regions 72, 73, and 74 can be configured to receive address signals from the bus 3 at respective first, second, and third relative delays (i.e., electrical propagation delays) from the respective first, second, and third connection regions 71, 72, and 73, and any difference among the first, second, and third relative delays can fall within a same tolerance, for example, a same tolerance of ±1% of any one of the relative delays. In a particular embodiment, an electrical propagation delay between the first and second connection regions 71, 72 can be within a same tolerance of the electrical propagation delay between the second and third connection regions 72, 73.
In one example, a characteristic impedance of the signal conductors of the bus 3 between the first and second connection regions 71 and 72, and the characteristic impedance of the signal conductors between the second and third connection regions 72 and 73 can fall within a same tolerance, for example, a same tolerance of ±5 ohms. Likewise, a characteristic impedance of the signal conductors of the bus 3 between the first and second connection regions 71 and 72, the characteristic impedance of the signal conductors of the bus 3 between the second and third connection regions 72 and 73, and the characteristic impedance of the signal conductors between the third and fourth connection regions 73 and 74 can fall within a same tolerance, for example, a same tolerance of ±5 ohms.
In one example, each of the groups of microelectronic elements 30 electrically connected to a particular one of the connection regions 71-76 can be configured to apply substantially a same load (i.e., electrical load) to the bus 3 as any other of the groups of microelectronic elements 30 electrically connected to another one of the connection regions 71-76, for example, within a tolerance of ±5 ohms. In a particular embodiment, a difference in electrical load applied to the address bus 3 via the first and second connection regions 71, 72 can be within a same tolerance of the difference in electrical load applied to the address bus via the second and third connection regions 72, 73. For example, the same tolerance of the difference in electrical load applied to the address bus can be within a tolerance of ±5 ohms.
In the example of
Since each connection region is electrically connected with only two of the memory arrays U0-U17, the first set 15a of the first terminals 25a of each microelectronic package 10, through which the first and third microelectronic elements 30a, 30c have a shared electrical connection 2a to the address bus or command/address bus 3, does not share a connection region 470 with any other microelectronic package. However, the second set 15b of the first terminals 25a of each microelectronic package 10, through which the second microelectronic element 30b has an independent electrical connection 2b to the address bus or command/address bus 3, shares its connection region with a corresponding second set of first terminals of another microelectronic package mounted to the opposite side of the circuit panel 60.
Therefore, in the example shown in
More specifically, in the microelectronic assembly 401, the first and third microelectronic elements 30a, 30c of the first microelectronic package 10a are electrically coupled to the address bus 3 only at a first one of the connection regions 471, the second microelectronic element 30b of the first microelectronic package and the second microelectronic element of the second microelectronic package 10b are electrically coupled to the address bus only at a second one of the connection regions 472, and the first and third microelectronic elements of the second microelectronic package are electrically coupled to the address bus only at a third one of the connection regions 473. This pattern is repeated for the third through sixth microelectronic packages 10c-10f.
In the embodiment of
In the embodiment of
In the example of
In the examples of the microelectronic assemblies 1, 401, 401a described herein having microelectronic packages 10 configured to apply balanced electrical connections to the address bus or command/address bus 3 (through independent groups 15a, 15b of first terminals each connected to only one of the connection regions 70), the electrical loads may be distributed more evenly distributed along the signal conductors of the fly-by bus 3 compared to conventional microelectronic assemblies.
Such microelectronic assemblies 1, 401, 401a may result in better impedance matching between adjacent connection regions along the bus 3, and more bandwidth capability along the bus to handle higher frequency signals, compared to conventional microelectronic assemblies. The inventors have found that in use, the structure of the microelectronic assemblies 1, 401, 401a may produce significantly lower reflection compared to conventional microelectronic assemblies, thereby permitting the assembly to operate at a higher bandwidth with better signal transmission than conventional microelectronic assemblies.
In one embodiment, the connection regions 71, 72, 73, and 74 need not all be disposed on a single circuit panel. For example, connection regions 71, 72 to which the microelectronic elements of a first package 10a are coupled can be disposed on a circuit panel other than the circuit panel on which the connection regions 73, 74 coupled to the second package 10c are disposed.
Although in the embodiments described herein, the first terminals 25a of the microelectronic packages 30 were disposed in the central region 23 of the second surface 22 of the substrate 20, in other examples, the first terminals can be disposed anywhere on the substrate. Although in the embodiments described herein, the first and second sets 17a, 17b of the second terminals 25b of the microelectronic packages 30 were disposed in the peripheral regions 28 of the second surface 22 of the substrate 20, in other examples, the first and second sets of the second terminals can be disposed anywhere on the substrate. Although in the embodiments described herein, the third set 17c of the second terminals 25b of the microelectronic packages 30 were disposed in the central region 23 of the second surface 22 of the substrate 20, on both sides of the third aperture 26c, in other examples, the third set of the second terminals can be disposed anywhere on the substrate, and the third set of the second terminals need not be distributed on both sides of the third aperture.
The microelectronic packages and microelectronic assemblies described above with reference to
In the exemplary system 500 shown, the system can include a circuit panel, motherboard, or riser panel 502 such as a flexible printed circuit board, and the circuit panel can include numerous conductors 504, of which only one is depicted in
In a particular embodiment, the system 500 can also include a processor such as the semiconductor chip 508, such that each module or component 506 can be configured to transfer a number N of data bits in parallel in a clock cycle, and the processor can be configured to transfer a number M of data bits in parallel in a clock cycle, M being greater than or equal to N.
In the example depicted in
Modules or components 506 and components 508 and 511 can be mounted in a common housing 501, schematically depicted in broken lines, and can be electrically interconnected with one another as necessary to form the desired circuit. The housing 501 is depicted as a portable housing of the type usable, for example, in a cellular telephone or personal digital assistant, and screen 510 can be exposed at the surface of the housing. In embodiments where a structure 506 includes a light-sensitive element such as an imaging chip, a lens 511 or other optical device also can be provided for routing light to the structure. Again, the simplified system shown in
It will be appreciated that the various dependent claims and the features set forth therein can be combined in different ways than presented in the initial claims. It will also be appreciated that the features described in connection with individual embodiments may be shared with others of the described embodiments. Although the invention herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present invention. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present invention as defined by the appended claims.
This application is a divisional of, and hereby claims priority to, pending U.S. patent application Ser. No. 15/148,726, filed May 6, 2016, the entirety of which is hereby incorporated by reference herein for all purposes.
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| Number | Date | Country | |
|---|---|---|---|
| 20170323667 A1 | Nov 2017 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 15148726 | May 2016 | US |
| Child | 15595163 | US |
