Patent Application
20240274503
A semiconductor package may include one or more semiconductor dies that may be stacked or mounted on an interposer. During operation, the semiconductor dies may generate a large amount of heat. For improved performance, the generated heat may be dissipated.
The semiconductor package may include a thermal interface material (TIM) layer to help dissipate heat. In particular, the TIM layer may help to transport heat from the interposer (e.g., from a semiconductor chip on the interposer) to a package lid of the semiconductor package. The TIM layer may be of particular benefit in large semiconductor packages and advanced semiconductor packages.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Unless explicitly stated otherwise, each element having the same reference numeral is presumed to have the same material composition and to have a thickness within a same thickness range.
A thermal variation (e.g., heating, cooling) may cause a typical semiconductor package to warp (e.g., thermal stress induced warp bending). This package warpage may induce delamination of the TIM layer from the interposer module, which may result in a failure of the semiconductor package. In such instances of package warpage, the TIM layer may delaminate from an upper surface of the interposer module at a corner of the interposer module.
One or more embodiments of the present disclosure may include a TIM layer protection structure. The TIM layer protection structure may help to protect the TIM layer—to inhibit (e.g., prevent) the TIM layer from delaminating off of the interposer module. The TIM layer protection structure may, therefore, provide improved reliability and better thermal dissipation performance for the overall semiconductor package. The TIM layer protection structure may be located in an air gap surrounding an interposer module (e.g., a semiconductor die/chip, integrated fan-out chiplets, integrated multiple logic chiplets, etc.) and between a package lid and package substrate (e.g., integrated circuit (IC) substrate).
In one or more embodiments, the TIM layer protection structure may be added to the semiconductor package after the package lid is attached to the package substrate over the interposer module. In one or more embodiments, the package lid may include a filling hole and a degassing hole. A TIM layer protection structure material (e.g., a liquid material) may be injected into the filling hole while a gas (e.g., air, nitrogen, etc.) may exit the semiconductor package through the degassing hole.
The TIM layer protection structure material may include, for example, a material such as or similar to an underfill material. The TIM layer protection structure may have a coefficient of thermal expansion (CTE) between 3 ppm/° C. and 20 ppm/° C. The TIM layer protection structure may have thermal conductivity that is greater than 1 W/m·K.
The TIM layer protection structure material may cure to form a solid TIM layer protection structure. The TIM layer protection structure may form a strong bond between the package lid, the package substrate and the interposer module (e.g., which may include a semiconductor die/chip). The TIM layer protection structure may be formed underneath the package lid, above the package substrate and surrounding the interposer module.
A ratio of a thickness of the TIM layer protection structure to a thickness of the interposer module (e.g., chip thickness) may be greater than 1.0 and less than 3.0. Further, the package lid may have a package lid length in a first direction and the TIM layer protection structure may have a TIM layer protection structure length in the first horizontal direction. A ratio of the TIM layer protection structure length to the package lid length may be in a range between 0.3 and 1.0. The package lid may also have a package lid width in a second horizontal direction perpendicular to the first horizontal direction and the TIM layer protection structure may have a TIM layer protection structure width in the second horizontal direction. A ratio of the TIM layer protection structure width to the package lid width may be in a range between 0.3 and 1.0.
The semiconductor package 100 may include a package substrate 110, an interposer module 120 mounted on the package substrate 110, and a package lid 130 on the interposer module 120 and attached to the package substrate 110. The semiconductor package 100 may also include a TIM layer 140 on the interposer module 120. The semiconductor package 100 may also include a TIM layer protection structure 170 that may protect that TIM layer 140. In particular, the TIM layer protection structure 170 may inhibit or mitigate against a delamination of the TIM layer 140 from a surface of the interposer module 120.
The package substrate 110 may include, for example, a core 112, a package substrate upper dielectric layer 114 formed on the core 112 (e.g., a first side or chip-side of the package substrate 110), and a package substrate lower dielectric layer 116 formed on the core 112 (e.g., a second side or board-side of the package substrate 110). In particular, the package substrate 110 may include a build-up film substrate such as an Ajinomoto build-up film (ABF) substrate. That is, in at least one embodiment, each of the package substrate upper dielectric layer 114 and the package substrate lower dielectric layer 116 may be described as an ABF layer.
The core 112 may provide rigidity to the package substrate 110. The core 112 may include, for example, an epoxy resin such as a bismaleimide triazine epoxy (BT epoxy) and/or a woven glass laminate. The core 112 may alternatively or in addition include an organic material such as a polymer material. In particular, the core 112 may include a dielectric polymer material such as polyimide (PI), benzocyclo-butene (BCB), or polybenzobisoxazole (PBO). Other suitable dielectric materials are within the contemplated scope of disclosure.
The core 112 may include one or more through vias 112a. The one or more through vias 112a may extend from a lower surface of the core 112 to an upper surface of the core 112. The one or more through vias 112a may allow an electrical connection between the package substrate upper dielectric layer 114 and the package substrate lower dielectric layer 116. The one or more through vias 112a may include, for example, one or more layers and may include metals, metal alloys, and/or or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.). Other suitable metal materials are within the contemplated scope of disclosure.
The package substrate lower dielectric layer 116 may include a plurality of layers and, in particular, may include a build-up film (e.g., ABF). The package substrate lower dielectric layer 116 may include an organic material such as a polymer material. In particular, the package substrate lower dielectric layer 116 may include one or more layers of dielectric polymer material such as polyimide (PI), benzocyclobutene (BCB), or polybenzobisoxazole (PBO). Other suitable dielectric materials are within the contemplated scope of disclosure.
The package substrate lower dielectric layer 116 may include one or more package substrate lower bonding pads 116a on a board-side surface of the package substrate lower dielectric layer 116. In particular, the package substrate lower bonding pads 116a may be exposed on the board-side surface of the package substrate lower dielectric layer 116. The package substrate lower dielectric layer 116 may also include one or more metal interconnect structures 116b. The metal interconnect structures 116b may be connected to the package substrate lower bonding pads 116a and the through vias 112a in the core 112. The metal interconnect structures 116b may include metal layers (e.g., copper traces) and metal vias connecting the metal layers. The package substrate lower bonding pads 116a and the metal interconnect structures 116b may include, for example, one or more layers and may include metals, metal alloys, and/or or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.). Other suitable metal materials for use in the metal interconnect structures 116b are within the contemplated scope of disclosure.
A package substrate lower surface layer 110b may be formed on the board-side surface of the package substrate lower dielectric layer 116. The package substrate lower surface layer 110b may partially cover the package substrate lower bonding pads 116a. The package substrate lower surface layer 110b may include one or more of a passivation layer and protection layer. The package substrate lower surface layer 110b may include, for example, a dielectric polymer material such as polyimide (PI), benzocyclobutene (BCB), or polybenzobisoxazole (PBO). The package substrate lower surface layer 110b may alternatively or additionally include silicon oxide, silicon nitride, low-k dielectric materials such as carbon-doped oxides, extremely low-k dielectric materials such as porous carbon doped silicon dioxide, or a combination thereof. Other suitable dielectric materials are within the contemplated scope of disclosure.
A ball-grid array (BGA) including a plurality of solder balls 110c may be formed on the board-side surface of the package substrate lower dielectric layer 116. The solder balls 110c may allow the semiconductor package 100 to be securely mounted on a substrate such as a printed circuit board (PCB) and electrically coupled to the PCB substrate. The solder balls 110c may contact the package substrate lower bonding pads 116a, respectively.
The package substrate upper dielectric layer 114 may be formed on an upper surface of the core 112. The package substrate upper dielectric layer 114 may also include a plurality of layers and, in particular, may include a build-up film (e.g., ABF). The package substrate upper dielectric layer 114 may also include an organic material such as a polymer material. In particular, the package substrate upper dielectric layer 114 may include a dielectric polymer material such as polyimide (PI), benzocyclobutene (BCB), or polybenzobisoxazole (PBO). Other suitable dielectric materials are within the contemplated scope of disclosure.
The package substrate upper dielectric layer 114 may include one or more package substrate upper bonding pads 114a on a chip-side surface of the package substrate upper dielectric layer 114. In particular, the package substrate upper bonding pads 114a may be exposed on the chip-side surface of the package substrate upper dielectric layer 114. In at least one embodiment, a bonding pad surface layer (not shown) (e.g., one or more layers of metals (e.g., tin, nickel, palladium, gold, etc.) and/or other materials) may be formed on the package substrate upper bonding pads 114a to improve solder joint reliability.
The package substrate upper dielectric layer 114 may also include one or more metal interconnect structures 114b. The metal interconnect structures 114b may include metal layers (e.g., copper traces) and metal vias connecting the metal layers. The package substrate upper bonding pads 114a may be electrically connected to the solder balls 110c of the BGA by way of the metal interconnect structures 114b, the through vias 112a, the metal interconnect structures 116b, and the package substrate lower bonding pads 116a. The package substrate upper bonding pads 114a and the metal interconnect structures 114b may include, for example, one or more layers and may include metals, metal alloys, and/or or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.). Other suitable metal materials are within the contemplated scope of disclosure.
A package substrate upper surface layer 110a may be formed on the chip-side surface of the package substrate upper dielectric layer 114. The package substrate upper surface layer 110a may including a coating layer, laminate layer, etc. The package substrate upper surface layer 110a may be formed so as to at least partially cover the package substrate upper bonding pads 114a.
In at least one embodiment, the package substrate upper surface layer 110a may include a solder resist layer (e.g., solder mask layer). The solder resist layer may include a thin layer of polymer material (e.g., epoxy polymer). The solder resist layer may have a thickness in a range from about 5 μm to 50 μm. In at least one embodiment, the solder resist layer may have a thickness in a range from about 10 μm to 30 μm. Greater or lesser thickness of the solder resist layer may be used. The solder resist layer may be formed so as to cover the package substrate upper bonding pads 114a and other metal features (e.g., conductive lines, copper traces) on the chip-side surface of the package substrate 110. The solder resist layer may protect the package substrate upper bonding pads 114a and other metal features from oxidation. The solder resist layer may also inhibit (e.g., prevent) solder bridges (e.g., unintended electrical connections) from forming between closely spaced metal features. The solder resist layer may include solder resist openings (SROs) over the package substrate upper bonding pads 114a, respectively. An upper surface of the package substrate upper bonding pads 114a may be exposed through the SROs. The SROs may have a tapered sidewall so that a diameter of the SRO (in the X-Y plane) may decrease in a direction toward the package substrate upper bonding pad 114a.
The package substrate upper surface layer 110a may alternatively or additionally include a layer other than a solder resist layer, such as a passivation layer or protection layer. In particular, the package substrate upper surface layer 110a may alternatively or additionally include a dielectric polymer material such as polyimide (PI), benzocyclo-butene (BCB), or polybenzobisoxazole (PBO), silicon oxide, silicon nitride, low-k dielectric materials such as carbon-doped oxides, extremely low-k dielectric materials such as porous carbon doped silicon dioxide, a combination thereof or other suitable material. The package substrate upper surface layer 110a may alternatively or additionally be formed, for example, by chemical vapor deposition (CVD), physical vapor deposition (PVD), spin coating, lamination or other suitable deposition technique.
The interposer module 120 may be mounted by controlled collapse chip connection (C4) bumps 121 on the package substrate upper bonding pads 114a in the package substrate 110. The interposer module 120 may include an interposer dielectric layer 122 that may include metal interconnects 122a electrically connected to the C4 bumps 121. The interposer module 120 may also include a first semiconductor die 123 and second semiconductor die 124 that may each be mounted on the interposer dielectric layer 122. It should be noted that any number of semiconductor dies may be mounted on the interposer dielectric layer 122.
The first semiconductor die 123 and second semiconductor die 124 may be mounted on the interposer dielectric layer 122 by micro-bumps 128 that may be electrically connected to the metal interconnects 122a. A package underfill layer 129 may be formed under and around the interposer module 120 and the C4 bumps 121 so as to fix the interposer module 120 to the package substrate 110. The package underfill layer 129 may be formed of an epoxy-based polymeric material.
Each of the first semiconductor die 123 and second semiconductor die 124 may include, for example, a semiconductor chip or chiplet for a high performance computing (HPC) application, an artificial intelligence (AI) application, and a 5G cellular network application, a logic die (e.g., mobile application processor, microcontroller, etc.), or a memory die (e.g., dynamic random access memory (DRAM) die, a Wide I/O die, a M-RAM die, a R-RAM die, a NAND die, static random access memory (SRAM), etc.), a central processing unit (CPU) chip, graphics processing unit (GPU) chip, field-programmable gate array (FPGA) chip, networking chip, application-specific integrated circuit (ASIC) chip, artificial intelligence/deep neural network (AI/DNN) accelerator chip, etc., a co-processor, accelerator, an on-chip memory buffer, a memory cube (e.g., HBM, HMC, etc.), a high data rate transceiver die, a I/O interface die, a IPD die (e.g., integrated passives device), a power management die (e.g., power management integrated circuit (PMIC) die), a radio frequency (RF) die, a sensor die, a micro-electro-mechanical-system (MEMS) die, a signal processing die (e.g., digital signal processing (DSP) die), a front-end die (e.g., analog front-end (AFE) die), a monolithic 3D heterogeneous chiplet stacking die, etc.
Each of the first semiconductor die 123 and second semiconductor die 124 may include, for example, an active region (not shown). The active region may include a front end of line (FEOL) region including electronic circuitry including various electronic devices (e.g., transistors, resistors, etc.). In particular, the FEOL region may include one or more logic circuits including logic devices (e.g., logic gates) and/or one or more memory circuits including memory devices (e.g., volatile memory (VM) devices and/or non-volatile memory (NVM) devices). The active region may also include a back end of line (BEOL) region that may include interlayer dielectric having a plurality of dielectric layers. The dielectric layers may include, for example, SiO2, a dielectric polymer or other suitable dielectric material. The interlayer dielectric may include one or more metal interconnect structures formed therein. The metal interconnect structures may include metal traces and metal vias formed in the dielectric layers and provide an electrical connection to the electronic circuitry in the FEOL region.
An interposer underfill layer 126 may be formed around the micro-bumps 128 and between the first semiconductor die 123 and the interposer dielectric layer 122, as well as between the second semiconductor die 124 and the interposer dielectric layer 122. The interposer underfill layer 126 may be formed continuously under both of the first semiconductor die 123 and second semiconductor die 124, as illustrated in
A molding material layer 127 may be formed over the first semiconductor die 123, second semiconductor die 124, the interposer underfill layer 126 and the interposer dielectric layer 122. The molding material layer 127 may be formed of an epoxy molding compound (EMC).
The TIM layer 140 may include, for example, a gel TIM, graphite TIM, metal TIM, solder TIM and a carbon nanotube TIM. Other types of TIMs are within the contemplated scope of this disclosure. In at least one embodiment, the TIM layer 140 may be in a range from 30 μm to 150 μm. The TIM layer 140 may be formed on the interposer module 120 to dissipate of heat generated during operation of the semiconductor package 100 (e.g., operation of first semiconductor die 123 and second semiconductor die 124. The TIM layer 140 may be attached to the interposer module 120, for example, by a thermally conductive adhesive. In particular, the TIM layer 140 may contact an upper surface of first semiconductor die 123, an upper surface of second semiconductor die 124, an upper surface of the molding material layer 127 and/or an upper surface of the interposer underfill layer 126. The TIM layer 140 may have a low bulk thermal impedance and high thermal conductivity. The bond-line-thickness (BLT) (e.g., a distance between the package lid 130 and the interposer module 120) may be less than about 100 μm, although greater or lesser distances may be used.
The semiconductor package 100 may also include a stiffener ring 150 that may be fixed to the package substrate 110 by an adhesive 160 such as a silicone adhesive or an epoxy adhesive. Other adhesives are within the contemplated scope of this disclosure. The stiffener ring 150 may be formed of a metal such as copper with a nickel coating, or an aluminum alloy. The stiffener ring 150 may alternatively be formed of a ceramic material or hard plastic (polymer) material. The stiffener ring 150 may be formed on the package substrate 110 so as to surround (e.g., encircle) the interposer module 120 in the x-y plane. The stiffener ring 150 may extend in a substantially perpendicular direction (e.g., in the z-direction) from the package substrate 110. The stiffener ring 150 may help to provide rigidity to the package substrate 110 and interposer module 120.
The package lid 130 may be connected to the stiffener ring 150 so as to cover the interposer module 120. The package lid 130 may be fixed to the stiffener ring 150 by an adhesive 161 (e.g., a silicone adhesive or an epoxy adhesive). The package lid 130 may contact at least a portion of the TIM layer 140. In one or more embodiments, the package lid 130 may directly contact an entire upper surface of the TIM layer 140. The package lid 130 may be formed, for example, of metal, ceramic or polymer material. The package lid 130 may have a plate shape (e.g., planar shape) and be substantially parallel to an upper surface of the package substrate 110. The package lid 130 may extend, for example, in an x-y plane in
The package lid 130 may include a bottom surface 130a and an upper surface 130b opposite the bottom surface 130a in the z-direction. The package lid 130 may have a thickness T130. The bottom surface 130a of the package lid 130 may extend across the package lid 130 between opposing sides of the stiffener ring 150 and contact the TIM layer 140. The TIM layer 140 may be compressed between the bottom surface 130a of the package lid 130 and the upper surface of the interposer module 120. The bottom surface 130a of the package lid 130 may be fixed to the stiffener ring 150 by the adhesive 161. The bottom surface 130a may be substantially planar. In particular, a height (e.g., in the z-direction) of the bottom surface 130a from the package substrate upper surface layer 110a may be substantially uniform across an entirety of the bottom surface 130a. Alternatively, the package lid 130 may also include a bottom step region (not shown) that may project from the bottom surface 130a and contact the TIM layer 140. The bottom step region may extend in a substantially perpendicular direction from the bottom surface 130a. The bottom step region may be formed around the central region of the package lid 130.
The semiconductor package 100 may also include a TIM layer protection structure 170. The TIM layer protection structure 170 may help to protect the TIM layer 140 and, in particular, may help to inhibit (e.g., prevent) the TIM layer 140 from delaminating off of the interposer module 120. The TIM layer protection structure 170 may, therefore, provide improved reliability and better thermal dissipation performance of the semiconductor package 100.
The TIM layer protection structure 170 may include a material that is substantially similar to the package underfill layer 129 and/or the interposer underfill layer 126. In at least one embodiment, the TIM layer protection structure 170 may include a polymeric material and in particular, an epoxy-based polymeric material. In at least one embodiment, the TIM layer protection structure 170 may include an added material (e.g., filler material) for improving a property of the TIM layer protection structure 170 (e.g., thermal conductivity, CTE, etc.). The added material may include, for example, metal powder, metal oxide powder, etc. Other materials in the TIM layer protection structure 170 are within the contemplated scope of the disclosure.
The TIM layer protection structure 170 may be located in a space (e.g., air gap) surrounding an interposer module 120, between the interposer module 120 and the stiffener ring 150 and between the package lid 130 and package substrate 110. In at least one embodiment, the TIM layer protection structure 170 may substantially fill the space (e.g., air gap) surrounding an interposer module 120.
In at least one embodiment, the TIM layer protection structure 170 may have a coefficient of thermal expansion (CTE) between 3 ppm/° C. and 20 ppm/° C. In at least one embodiment, the TIM layer protection structure may have thermal conductivity that is greater than 1 W/m·K. In at least one embodiment, the TIM layer protection structure may have a CTE that is greater than a CTE of the TIM layer. In at least one embodiment, the TIM layer protection structure may have a thermal conductivity that is greater than a thermal conductivity of the TIM layer. In at least one embodiment, the TIM layer protection structure 170 may be formed of a curable material that may cure to form a hard, solid structure. A ratio of a thickness T170 of the TIM layer protection structure 170 to a thickness T120 of the interposer module 120 (e.g., chip thickness) may be greater than 1.0 and less than 3.0. The TIM layer protection structure 170 may form a strong bond between the package lid 130, the package substrate 110 and the interposer module 120. In at least one embodiment, the TIM layer protection structure 170 may be bonded to one or more of the bottom surface 130a of the package lid 130, an upper surface of the package substrate 110, an outer side surface (sidewall) of the TIM layer 140, an outer side surface (sidewall) of the interposer module 120, an inner side surface (sidewall) of the stiffener ring 150, the package underfill layer 129, the adhesive 160 and the adhesive 161.
In at least one embodiment, the TIM layer protection structure 170 may be added to the semiconductor package 100 through a filling hole 131 in the package lid 130. The package lid 130 may also include a degassing hole 133 to facilitate the adding of the TIM layer protection structure 170. The package lid 130 may also include a filling plug 132 and a degassing plug 134 for plugging the filling hole 131 and degassing hole 133, respectively. The filling plug 132 and degassing plug 134 may include a polymeric material and in particular, an epoxy-based polymeric material. Other materials are within the contemplated scope of the disclosure.
Referring to
The filling hole 131 may be located in a central region of the TIM layer protection structure 170. The filling hole 131 may be separated from the interposer module 120 by an inner length L131i. The filling hole 131 may be separated from the stiffener ring 150 by an outer length L131o. In at least one embodiment, the filling hole 131 may be equidistant between the interposer module 120 and the stiffener ring 150 (e.g., L131i=L131o).
The filling plug 132 may extend from the bottom surface 130a of the package lid 130 to the upper surface 130b of the package lid 130. An upper surface of the filling plug 132 may be substantially coplanar with the upper surface 130b of the package lid 130. A bottom surface of the filling plug 132 may be substantially coplanar with the bottom surface 130a of the package lid 130. Thus, a thickness of the filling plug 132 may be substantially the same as the thickness T130 of the package lid 130. The filling plug 132 may fill an entirety of the filling hole 131 and completely seal the filling hole 131. The filling plug 132 may adhere and bond to a wall of the filling hole 131 over an entirety of the filling hole 131.
As further illustrated in
Referring to
The degassing hole 133 may be located in a central region of the TIM layer protection structure 170. The degassing hole 133 may be separated from the interposer module 120 by an inner length L133i. The degassing hole 133 may be separated from the stiffener ring 150 by an outer length L1330. In at least one embodiment, the degassing hole 133 may be equidistant between the interposer module 120 and the stiffener ring 150 (e.g., L131i=L131o). In at least one embodiment, the inner length L131i may be greater than the outer length L1330 (e.g., L131i>L131o). That is, the degassing hole 133 may be located in the package lid 130 closer to the stiffener ring 150 than the interposer module 120.
The degassing plug 134 may also extend from the bottom surface 130a of the package lid 130 to the upper surface 130b of the package lid 130. An upper surface of the degassing plug 134 may be substantially coplanar with the upper surface 130b of the package lid 130. A bottom surface of the degassing plug 134 may be substantially coplanar with the bottom surface 130a of the package lid 130. Thus, a thickness of the degassing plug 134 may be substantially the same as the thickness T130 of the package lid 130. The degassing plug 134 may fill an entirety of the degassing hole 133 and completely seal the degassing hole 133. The degassing plug 134 may adhere and bond to a wall of the degassing hole 133 over an entirety of the degassing hole 133.
Referring to
In particular, the package lid 130 may have a width L130 in the first horizontal direction (i.e., x-direction) and a width W130 in a second horizontal direction (i.e., y-direction). The TIM layer protection structure 170 may be formed around an entire periphery of the interposer module 120 and TIM layer 140. The TIM layer protection structure 170 may have a width L170 in the first horizontal direction (i.e., x-direction) and a width W170 in the second horizontal direction (i.e., y-direction). A ratio R1 of the length L170 of the TIM layer protection structure 170 to the length L130 of the package lid 130 may be in a range between 0.3 and 1.0. A ratio R2 of the width W170 of the TIM layer protection structure 170 to the width W130 of the package lid 130 may be in a range between 0.3 and 1.0. The ratio R1 and the ratio R2 may be in the range between 0.3 and 1.0, to ensure that the TIM layer protection structure 170 provides sufficient bonding between the package lid 130, the package substrate 110 and the interposer module 120.
As illustrated in
It should be noted that the diameter D131 of the filling hole 131 and the diameter D133 of the degassing hole 133 may depend on a thickness of the package lid 130. In at least one embodiment, the diameter D131 and diameter D133 may increase with an increasing thickness of the package lid 130. The diameter D131 and diameter D133 may also depend on a volume of the space to be filled by the TIM layer protection structure 170 (i.e., volume defined by the inner stiffener ring 150 and interposer 120, top surface of the package substrate 110a and bottom surface of the package lid 130). In at least one embodiment, the diameter D131 and diameter D133 may increase with an increasing volume of the space.
The package substrate lower bonding pads 116a may be formed, for example, on a lowest dielectric layer of the package substrate lower dielectric layer 116. The package substrate lower bonding pads 116a may be formed so as to contact the metal interconnect structures 116b. The package substrate lower bonding pads 116a may be formed by depositing a metal layer (e.g., copper, aluminum or other suitable conductive materials) on the lowest dielectric layer of the package substrate upper dielectric layer 114. The metal layer may then be patterned by etching (e.g., by wet etching, dry etching, etc.) so as to form the package substrate lower bonding pads 116a. Other suitable metal layer materials and etching processes may be within the contemplated scope of disclosure.
After formation, the package substrate upper bonding pads 114a and package substrate lower bonding pads 116a may optionally undergo a surface roughening treatment (e.g., copper surface roughening treatment which may also be referred to as copper zarazara (CZ) treatment). In the surface roughening treatment, a surface of the package substrate upper bonding pads 114a (e.g., a copper surface) and surface of the package substrate lower bonding pads 116a (e.g., a copper surface) may be etched by an organic acid-type microetching solution, to create a super-roughened surface (e.g., copper surface). The uniquely-roughened copper surface topography of the package substrate upper bonding pads 114a and package substrate lower bonding pads 116a may help to achieve a high copper-to-resin adhesion.
The package substrate upper surface layer 110a and package substrate lower surface layer 110b may be applied concurrently. The package substrate upper surface layer 110a and package substrate lower surface layer 110b may be applied, for example, as a liquid photo-imageable film. The liquid photo-imageable film can be applied, for example, by silk-screening or spraying the liquid photo-imageable film onto the surface of the package substrate 110. The liquid photo-imageable film may be applied over the package substrate upper bonding pads 114a and the package substrate lower bonding pads 116a. The package substrate upper surface layer 110a and package substrate lower surface layer 110b may alternatively be applied as a dry-film photo-imageable film that may be vacuum-laminated onto the surface of the package substrate 110 and over the package substrate upper bonding pads 114a and the package substrate lower bonding pads 116a, respectively.
The package substrate upper surface layer 110a and package substrate lower surface layer 110b may be applied so as to have a thickness that is slightly greater than a thickness of the package substrate upper bonding pads 114a and the package substrate lower bonding pads 116a, respectively. Alternatively, the package substrate upper surface layer 110a and package substrate lower surface layer 110b may be applied so as to have an upper surface that is substantially co-planar with an upper surface of the package substrate upper bonding pads 114a and the package substrate lower bonding pads 116a, respectively.
Openings O110a may be formed in the package substrate upper surface layer 110a so as to expose an upper surface of the package substrate upper bonding pads 114a. Openings O110b may be formed in the package substrate lower surface layer 110b so as to expose an upper surface of the package substrate lower bonding pads 116a. The openings O110b and the openings O110b may be formed, for example, by using a photolithographic process. In at least one embodiment, the openings O110b and the openings O110b may be formed in separate photolithographic processes.
The photolithographic process (e.g., processes) used to form the openings O110a may include forming a patterned photoresist mask (not shown) on the package substrate upper surface layer 110a, and etching (e.g., wet etching, dry etching, etc.) the exposed upper surface of the package substrate upper surface layer 110a through openings in the photoresist mask. The photoresist mask may be subsequently removed by ashing, dissolving the photoresist mask or by consuming the photoresist mask during the etch process.
The photolithographic process (e.g., processes) used to form the openings O110b may include forming a patterned photoresist mask (not shown) on the package substrate lower surface layer 110b, and etching (e.g., wet etching, dry etching, etc.) the exposed upper surface of the package substrate lower surface layer 110b through openings in the photoresist mask. The photoresist mask may be subsequently removed by ashing, dissolving the photoresist mask or by consuming the photoresist mask during the etch process.
After the openings O110a are formed in the package substrate upper surface layer 110a and the openings O110b are formed in the package substrate lower surface layer 110b, the package substrate upper surface layer 110a (upper solder resist layer) and the package substrate lower surface layer 110b may be cured such as by a thermal cure or ultraviolet (UV) cure.
In
The adhesive 161 may be applied to an upper surface (e.g., an entire upper surface) of the stiffener ring 150. Alternatively, the adhesive 161 may be applied to the bottom surface 130a of the package lid 130 at a location corresponding to a location of the stiffener ring 150. The package lid 130 may then be aligned with the stiffener ring 140 and lowered onto the stiffener ring 150 and the TIM layer 140. The package lid 130 may then be clamped to the package substrate 110 for a period to allow the adhesive 161 and the adhesive 160 to cure and form a secure bond between the package substrate 110, the stiffener ring 150 and the package lid 130. The clamping of the package lid 130 to the package substrate 110 may be performed, for example, by using a heat clamp module. The heat clamp module may apply a uniform force across the upper surface of the package lid 130. In some embodiments as illustrated and described in more detail below with reference to
Concurrently with the injecting of the material, a gas (e.g., air, nitrogen, etc.) may exit the semiconductor package 100 through the degassing hole 133 in the package lid 130.
In at least one embodiment, the material of the TIM layer protection structure 170 may be injected into the filling hole 131 until the material of the TIM layer protection structure 170 reaches the degassing hole 133. That is, the injecting of the material may be ceased when the material of the TIM layer protection structure 170 reaches the degassing hole 133. In at least one embodiment, the injecting of the material may cease when an uppermost surface of the TIM layer protection structure 170 is substantially coplanar with the bottom surface 130a, a bottom end of the filling hole 131 and a bottom end of the degassing hole 133. In at least one embodiment, the injecting of the material may cease when the TIM layer protection structure 170 fills the entire volume between the interposer module 120 and stiffener ring 150.
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In at least one embodiment, a filling of the material of the TIM layer protection structure 170 may be automated. In particular, various aspects of the filling process may be computer-controlled by a control system (e.g., electronic control system; central processing unit (CPU)). In at least one embodiment, a beginning of the injecting of the material, a flow rate of the injecting of the material, and a stopping of the injecting of the material may be controlled by the control system.
In at least one embodiment, a vacuum line may be connected to the degassing hole 133 so that a vacuum may be pulled on the volume around the interposer module 120. An imaging device (e.g., camera) may be connected to a portion the vacuum line inserted into the degassing hole 133. The vacuum line and imaging device may also be controlled by the control system. The imaging device may detect a level of the material of the TIM layer protection structure 170. An output of the imaging device may be transmitted (e.g., by wired or wireless signal) to the control system. The control system may cause the injecting of the material to stop and a vacuum in the vacuum line to stop when the output of the imaging device indicates that the material has reached a particular level within the semiconductor package 100 (e.g., when the material has reached the degassing hole 133).
Alternatively, the control system may be programmed to inject a predetermined volume of the material based on various input parameters. The input parameters may include, for example, a volume of the space around the interposer module 120, a size of the interposer module 120, a size of the package lid 130, a size of the stiffener ring 150, etc.
In at least one embodiment, the material for forming the TIM layer protection structure 170 (e.g., an epoxy-based polymeric material) may include a capillary material (e.g., capillary underfill type material). The material may have a low viscosity. In particular, the viscosity of the material may be less than a viscosity of the material of the package underfill layer 129. In at least one embodiment, the viscosity may be less than about 5,000 cP at 10 rpm. In at least one embodiment, the material may include a low-viscosity suspension of thermally conductive material (e.g., metal, metal oxide) in prepolymer. The low viscosity may help to facilitate transport of the material around the interposer module 120 and throughout the space around the interposer module 120. The low viscosity may also help to avoid the formation of voids in the TIM layer protection structure 170. In at least one embodiment, the TIM layer protection structure 170 may be substantially free of voids.
During the process of adding the material of the TIM layer protection structure 170, the material may contact and flow over a surface of the package substrate upper surface layer 110a (e.g., solder resist layer). The surface of the package substrate upper surface layer 110 may have a low surface roughness. In particular, the surface roughness of the package substrate upper surface layer 110 may be less than a surface roughness of the bottom surface 130a of the package lid 130. In at least one embodiment, a surface roughness (arithmetical mean roughness (Ra)) of the package substrate upper surface layer 110 may be less than 1.0 nm (Ra<1.0 nm). The low surface roughness may help to facilitate flow (transport) of the material in the space around the interposer module 120. A roughness value may include, for example, arithmetical mean roughness (Ra), ten-point mean roughness (Rz), and Rq is the rms root-mean-square (rms) value of the departures of the profile from the mean line, and/or maximum height or depth (Rmax). However, other measures of roughness may be within the scope of disclosure (e.g., mean spacing of profile irregularities (Sm), mean spacing of local peaks of the profile(S), and profile bearing length ratio (tp)).
In an alternative embodiment, the material of the filling plug 132 may be different than the material of the degassing plug 134. For example, a material of one of the filling plug 132 and the degassing plug 134 may include a silicone based material, and a material of the other one of the filling plug 132 and the degassing plug 134 may include an epoxy-based polymeric material. In another alternative embodiment, the material of the filling plug 132 and/or the degassing plug 134 may be different than the material of the TIM layer protection structure 170.
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The package lid 130 in the fifth alternative design may also include the inner foot 130d that is formed inside the outer foot 130c. The inner foot 130d may project substantially perpendicular from the plate portion 130p. The inner foot 130d may have the same length or different length in the z-direction as the outer foot 130c. The inner foot 130d may also be connected to the package substrate 110 by the adhesive 160.
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The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
