Thermal nitrogen distribution method to improve uniformity of highly doped ultra-thin gate capacitors

Abstract

Methods such as Remote Plasma Nitridation (RPN) are used to introduce nitrogen into a gate dielectric layer. However, these methods yield nitrided layers where the layers are not uniform, both in cross-sectional profile and in nitrogen profile. Subjecting the nitrided layer to an additional NO anneal process increases the uniformity of the nitrided layer.

Description

FIELD OF INVENTION

The present invention relates to transistor design, and, in particular, a thermal nitrogen deposition method to improve the uniformity of the nitrided layer of a gate capacitor of a transistor.

BACKGROUND OF THE INVENTION

The speed requirements for high-performance 0.13 um CMOS devices has driven gate oxide thicknesses to less than 20 Å, with inversion and physical thicknesses trending to less than 20 Å. As the dielectric layers are scaled thinner, the leakage currents through these gates exponentially increase due to more direct tunneling of electrons and holes through the potential barriers of the dielectric. This can affect device properties by causing higher standby power consumption, reliability problems, and degradation of certain chip functions such as timing. Battery powered devices for mobile applications for example, have some of the strictest requirements for leakage current, where lower leakage currents produce longer battery life.

FIG. 1 shows a transistor structure with the gate dielectric ( 20 ). Gate leakage current is defined as the current from gate to drain when Vg ( 22 ) is less, than the threshold voltage of the device. This current is an exponential function of thickness, with the current increasing by 2-3× for every 1 Å decrease in thickness, in the sub-20 Å thickness range for a gate dielectric layer that is formed using SiO 2 .

Remote plasma nitridation (RPN) or decoupled plasma nitridation (DPN) are methods used to introduce large concentrations of nitrogen into the gate dielectric layer, thereby forming a silicon oxynitride gate dielectric. With the incorporation of nitrogen, the gate leakage current can by reduced. This is mainly due to increasing the capacitance of the layer which allows for larger physical thicknesses with the same electrical thickness. There is also some reduction in leakage current due to the change in chemical bonding at the dielectric-Si substrate interface. These particular processes are desirable due to their ability to incorporate large concentrations of nitrogen (>4×10 21 at/cm 3 ) and their ability to control the profile of the nitrogen throughout the dielectric layer. These process techniques however, can be inherently non-uniform, thus causing a large non-uniformity of device parameters across the wafer. Non-uniformity of device parameters can cause severe yield degradation in chip performance if certain specifications are out of range. These electrical parameters can include leakage current, electrical thickness, threshold voltage, and device current. This invention addresses this non-uniformity, and demonstrates that the physical thickness and nitrogen concentration is improved by making use of the techniques described in the invention.

SUMMARY OF THE INVENTION

The present invention relates to a method for improving the uniformity of the nitrided layer that is formed over the base SiO 2 layer of a transistor gate dielectric, thus lowering the leakage current through the base SiO 2 layer.

DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a transistor used to define gate leakage current.

FIG. 2 shows the cross-sectional profile of a wafer, comprising the base oxide layer and the nitrided layer formed by any nitrogen-deposition process.

FIG. 3 shows the cross sectional profile of a wafer, comprising a first base oxide layer, a second nitrided layer formed by any nitrogen-deposition process, and a third NO annealed layer.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 2 shows the cross sectional profile of a wafer used as a gate dielectric. First a base oxide layer ( 24 ), for example, silicon dioxide (SiO 2 ), of the wafer is formed using known techniques, such as RTO or furnace oxidation. The base oxide layer can be between 5A and 20A thick. The base oxide layer is usually approximately 10A thick. Next, nitrogen is deposited in the base oxide layer using RPN or DPN, resulting in a highly-nitrided second layer ( 26 ) containing a high concentration of nitrogen. This highly-nitrided second layer can be anywhere between 10A-30A thick. However, RPN and DPN result in this highly-nitrided second layer having a non-uniform physical profile. FIG. 2 shows the situation where the height of the second layer is greater in the middle than at the edges of the profile. FIG. 2 shows only this one irregular profile. Other irregular profiles, such as where, for example, the edges of the highly nitrided layer are higher than the middle of the highly nitrided layer are possible as well, are not shown. FIG. 2 defines h max as the highest point of the highly-nitrided second layer above the base oxide layer and h min as the lowest point of the highly-nitrided second layer above the base oxide layer.

In addition to RPN's and DPN's resulting in the non-uniform physical structure of this highly-nitrided second layer, RPN and DPN also results in a non-uniform deposition of nitrogen within the highly-nitrided second layer. For example, Table 2 shows nitrogen concentrations between the center and the edge of the highly-nitrided second layer differing by 3×10 14 atoms/cm 3 .

Subjecting this structure shown in FIG. 2 (i.e., a two-layer structure comprising a base oxide layer and a highly-nitrided second layer) to a nitric thermal anneal process reduces the non-uniformity of the profile of the highly-nitrided second layer, resulting in the cross-sectional profile shown in FIG. 3 . The resulting structure has a base oxide layer ( 24 ), a highly nitrided second layer ( 26 ), and a NO anneal layer ( 28 ). The NO anneal layer can be between 1A and 30A thick, and is typically between 1A and 5A thick. Subjecting this structure shown in FIG. 2 to a nitric thermal anneal process also reduces the non-uniformity of nitrogen deposition concentration within the highly-nitrided second layer, as shown in Table 2. Two methods can be used to carry out this nitric thermal anneal.

In a first embodiment of the present invention, a plurality of wafers on which a base oxide layer and a highly-nitrided second layer have been formed are put into an annealing furnace. The time, temperature, and pressure of the annealing process can be varied to achieve the maximum uniformity of the nitric anneal layer. The wafers are exposed to a range of temperatures for times ranging from 5 minutes to 30 minutes. The temperatures to which the wafers are exposed can range between 500-1100 degrees Centigrade. The pressure to which the wafers are exposed during this process can range between 1-760 torr. During the time when the wafers are in the furnace exposed to the annealing temperature and pressure, gas is allowed to flow over the surface of the wafers. This gas can be any gas which under the temperature and pressure conditions under which the anneal is performed dissociates into NO. The gas is heated to a temperature in the range of 800-1100 degrees Centigrade before being admitted into the furnace and allowed to pass over the wafers. Preferably, the gas is heated to 950-degrees Centigrade before being admitted into the furnace and allowed to pass over the wafers.

In a second embodiment of the present invention, single wafer tools are used to perform the annealing process instead of an annealing furnace. In other words, while using the annealing furnace allows a batch of wafers to undergo thermal annealing at one time, in this embodiment, single wafers are subjected to the annealing process at one time. The time, temperature, and pressure parameters to which the wafers are exposed are the same as in the first embodiment described previously. The wafers are exposed to a range of temperatures for times ranging from 5 seconds to 30 minutes. The temperatures to which the wafers are exposed can range between 500-1100 degrees Centigrade. The pressure to which the wafers are exposed during this process can range between 1-760 torr. During the time when the wafers are exposed to the annealing temperature and pressure, gas is allowed to flow over the surface of the wafers. This gas can be any gas which under the temperature and pressure conditions under which the anneal is performed dissociates into NO. The gas is heated to a temperature in the range of 800-1200 degrees Centigrade before being allowed to pass over the wafers. Preferably, the gas is heated to 950 degrees Centigrade before being allowed to pass over the wafers.

The advantage of the first embodiment discussed above is that several wafers can be annealed at once. The advantage of the second embodiment is that, in a single wafer process, the required temperature and pressure can be reached in a shorter period of time.

The following table (Table 1) shows the results obtained for two furnace annealing processes accomplished under the conditions shown. These data are obtained by optical measuring:

	Furnace Anneal
	for 13 minutes	Furnace Anneal
	N 2 O 700 C. (950 C.	for 26 minutes
	precombustion	N 2 O 800 C. (950 C.
	chamber	precombustion
	temperature)	chamber
Process/	temperature)
se-	Elliptical		Std.	Elliptical		Std.
quence	thickness	Range	Dev.	Thickness	Range	Dev.
RPN	21.44A	2.24A	0.5A	21.34A	1.91A	0.47A
RPN/	22.46A	1.38A	0.33A	24.17A	0.93A	0.28A
Furnace
anneal
RTO/	20.27A	1.53A	0.39A	20.04A	1.05A	0.27A
RPN
RTO/	23.04A	0.70A	0.18A	26.11A	0.98A	0.24A
RPN/
Furnace
Anneal

Where: (a) elliptical thickness represents the thickness of the highly-nitrided layer after the various processes shown; and (b) range shows the difference between the highest and lowest points of the cross-sectional profile of the top of the highly-nitrided layer. All unit measurements shown are in angstroms. As the data above shows, the furnace annealing processes reduces the range; that is, the difference between the highest and lowest points on the cross-sectional profile of the top of the highly nitrided layer.

The following table (Table 2) shows data obtained from the furnace annealing process measured by secondary ion mass spectrometry.

					SIMS N
		Elliptic	TOF-	SIMS N	concen-
	Wafer	thick-	SIMS	dose	tration
Process	site	ness	Thickness	(e14 at/cm 3 )	(e21 at/cm 3 )
1. RTO/RPN	Center	20.14A	15.0A	9	4
(no anneal)	Edge	19.02A	17.0A	6	3
	Mean	19.65A
2. RTO/RPN	Center	23.24A	20.0A	9	4
and Furnace	Edge	22.29A	19.0A	8	4
1 anneal	Mean	22.80A
3. RTO/RPN	Center	26.25A	23.0A	8	3.5
and Furnace	Edge	25.50A	23.0A	7	3.4
2 anneal	Mean	25.79A

Where physical elliptical uniformity is defined as 100*(max-min)/(2*mean), where max and min are the maximum height and minimum height, respectively, of the cross sectional profile of the highly nitrided layer, the processes listed above yielded the following data. Process 1 yielded a physical elliptical uniformity of 2.85%. Process 2 yielded a physical elliptical uniformity of 2.08%. Process 3 yielded a physical elliptical uniformity of 1.42%.

The table also shows the improvement in concentration uniformity gained by the annealing process. Process 1 , in which no anneal was performed, yielded a dose uniformity of 67% and a concentration uniformity of 77%. By contrast, process 2 yielded a dose uniformity of 89% and a concentration uniformity of 100%. Process 3 yielded a dose uniformity of 88% and a concentration uniformity of 97%.

The Furnace 1 process is a furnace annealing process for 13 minutes N 2 O 700 C (950 C precombustion chamber temperature). The Furnace 2 process is a furnace annealing process at 26 minutes N 2 O 800 C (950 C precombustion chamber temperature).

The foregoing description encompasses only the preferred embodiments of the present invention. The following claims and their equivalents define the scope of the invention.

Claims

1. For a gate dielectric wafer used in an integrated circuit device, said wafer comprising a base silicon oxide layer, a method for forming an NO annealed layer on said wafer, comprising:forming a nitrided layer on said silicon oxide layer, wherein said nitrided layer has a first percent elliptical uniformity and a first percent nitrogen concentration uniformity; subjecting the wafer to a temperature between 500 and 1100 degrees C.; subjecting the wafer to a pressure between 1 to 760 torr; providing a NO-dissociating gas; preheating said gas to between 800-1200 degrees C. and passing said gas over the surface of said nitrided layer, thus forming an NO annealed layer on the wafer, wherein said annealed layer has a second percent elliptical uniformity less than said first percent elliptical uniformity, and a second percent nitrogen concentration uniformity higher than said first percent nitrogen concentration uniformity.

2. The method of claim 1, where the gas is passes over the surface of the nitrided layer for a time period between 5 seconds and 30 minutes.

3. The method of claim 2, where the gas is preheated to 950 degrees C.