Patent Application
20180269230
The present invention relates to a radio frequency (RF) switch including a plurality of silicon-on-insulator (SOI) CMOS transistors.
Silicon-on-insulator (SOI) CMOS technologies are now the dominant platforms for creating best-in-class radio frequency switch (RFSW) products for handsets and other mobile devices. Thus, transistors 1101-110N and 1201-120N are typically implemented using SOI CMOS transistors. Such SOI CMOS transistors enable the associated RF switches 110 and 120 to transmit RF signals in the range of 0.5 GHz to 6 GHz with a high degree of linearity, while withstanding voltages of 40V to 70V and in an off-state. Because SOI CMOS technology uses standard CMOS technologies and standard cell libraries, RF switches that implement SOI CMOS transistors can be readily integrated into larger system-on-chip (SOC) devices, thereby minimizing fabrication costs. For example, transistors 1101-110N and 1201-120N and transistors associated with receive port 115 and transmit port 125 may be fabricated on the same integrated circuit chip.
As described herein, an SOI CMOS technology includes any process that can be used to fabricate SOI CMOS transistors. Thus, a process that can be used to integrate the fabrication of both SOI CMOS transistors and other types of transistors (e.g., SiGe BiCMOS transistors) is considered to be an SOI CMOS process.
For RF switch 110 (or 120), the on-resistance of the switch (RON) multiplied by the off-capacitance of the switch (COFF) is a key figure of merit, which dictates the ability to transmit RF power with low losses through on-state transistor stacks, while maintaining adequate isolation across off-state transistor stacks. The thin film SOI CMOS transistors are attractive for RF switch applications, because these transistors reduce the junction capacitance component of the off-capacitance value, COFF.
Typically, the off-state stacks of an RF switch need to hold off relatively high voltage RF signals (e.g., 40-70V). Consequently, RF switches are implemented with older generation SOI CMOS transistors having operating voltages in the 2.5 Volt-5 Volt range. These older generation SOI CMOS transistors are fabricated using process nodes with a minimum feature size of 0.18 microns or greater. In general, the gate length of each of transistors 1101-110N and 1201-120N must be about 0.18 microns or more to provide the required off-state isolation. Note that transistors fabricated using more advanced process nodes (e.g., a 0.13 micron process node) have lower operating voltages (e.g., 1.2 Volts or lower), and are typically not suitable for implementing an RF switch.
SOI CMOS transistors 201-202 are fabricated on a thin silicon layer 205, which is located on an insulator 204 (e.g., silicon oxide), which in turn, is located on a substrate 203 (e.g., monocrystalline silicon).
N-channel SOI CMOS transistor 201 includes an n-type source region 211 (which includes lightly doped source region 211A and source contact region 211B), an n-type drain region 212 (which includes lightly doped drain region 212A and drain contact region 212B), gate dielectric 215, polysilicon gate 217, dielectric sidewall spacers 219-220 and metal silicide regions 223-225. A p-type channel region 209 exists between the source region 211 and the drain region 212. Polysilicon gate 217 has a length LA of 0.18 microns or greater, and a thickness TX of about 2000 Angstroms. To implement a typical RF switch, polysilicon gate 217 may have a length LA of about 0.28 microns.
Polysilicon gate electrode 217 is exposed during the implant of an n-type dopant into source/drain regions 211-212, such that polysilicon gate electrode 217 is doped to an n-type conductivity. When a logic high voltage (e.g., 2.5 Volts) is applied to polysilicon gate electrode 217, a depletion effect within the polysilicon results in the formation of an inversion layer within the polysilicon gate electrode 217, whereby a reduced voltage (e.g., 2.3 Volts) is applied at the channel region 209 of the transistor 201. This polysilicon depletion effect undesirably results in an increased on-resistance RON of transistor 201.
P-channel SOI CMOS transistor 202 includes a p-type source region 213 (which includes lightly doped source region 213A and source contact region 213B), a p-type drain region 214 (which includes lightly doped drain region 214A and drain contact region 214B), gate dielectric 216, polysilicon gate 218, dielectric sidewall spacers 221-222 and metal silicide regions 226-228. An n-type channel region 210 exists between the source region 213 and the drain region 214. Polysilicon gate 218 has the same thickness TX as polysilicon gate 217. Polysilicon gate 218 has a length of 0.18 microns or greater. The length of polysilicon gate 218 is selected in view of the particular application of transistor 202.
A multi-layer interconnect structure 260 is fabricated over transistors 201-202, thereby providing electrical connections to these transistors (and other devices fabricated in the thin silicon layer 205). In the example illustrated, a pre-metal dielectric (PMD) structure 230 is formed over transistors 201-202. Tungsten (W) contacts 231, 232, 233 and 234 extend through the PMD layer 230 and contact the silicide regions 223, 225, 226 and 228, respectively, as illustrated. A first metal layer (M1), including aluminum traces 241-244, is formed over PMD layer 230. A dielectric structure 240 is formed over the PMD structure 230 and the first metal layer (M1). Tungsten vias 245-248 extend through the dielectric structure 240 to provide contact to aluminum traces 241-244, respectively, of the first metal layer.
Additional alternating metal layers, metal vias and insulating structures are formed over the dielectric structure 240 in a manner known to those in the art. For example,
The lengths, thicknesses and spacings of traces 231-234, traces 241-244, vias 245-248 and traces 251-255 contribute to the off-capacitances (COFF) of the associated RF switches 110 and 120. For example, capacitance CA (between polysilicon gate 217 and source region 211), capacitance CB (between polysilicon gate 217 and contact 231), capacitance CC (between polysilicon gate 217 and M1 trace 241), capacitance CD (between polysilicon gate 217 and M1 trace 242), capacitance CE (between polysilicon gate 217 and contact 232), and capacitance CF (between polysilicon gate 217 and drain region 212) all contribute to the off-capacitance (COFF) of transistor 217.
It would be desirable to have an improved SOI CMOS transistor for implementing an RF switch structure, and a method for fabricating the same. It would be desirable for the improved RF switch structure to have a reduced on-resistance RON and a reduced off-capacitance COFF. It would further be desirable if this improved RF switch structure can be fabricated using a process that is substantially consistent with existing conventional fabrication process nodes.
Accordingly, the present invention provides an RF switch that includes a plurality of SOI CMOS transistors having polysilicon gates with relatively small thicknesses. That is, the thickness of the polysilicon gate is thinner than the typical thickness of a polysilicon gate associated with the process used to fabricate the device.
In one embodiment, the SOI CMOS transistors of the RF switch are fabricated using a largely conventional SOI CMOS process. However, the thickness of the polysilicon layer (and therefore the thicknesses of the polysilicon gates of the associated transistors) is reduced with respect to a conventional SOI CMOS process. For example, a conventional 0.18 micron SOI CMOS process technology may typically use a polysilicon layer having a thickness of about 2000 Angstroms. In accordance with one embodiment, the 0.18 micron SOI CMOS process is modified to provide a polysilicon layer having a reduced thickness of about 1250 Angstroms. In an alternate embodiment, the 0.18 micron SOI CMOS process is modified to provide a polysilicon layer having a thickness in a range of about 1350 to about 1150 Angstroms. In yet another embodiment, the 0.18 micron SOI CMOS process is modified to provide a polysilicon layer having a thickness of less than about 1450 Angstroms. In another embodiment, the 0.18 micron SOI CMOS process is modified to provide a polysilicon layer having a thickness that is less than or equal to about 70% of the thickness of a conventional polysilicon layer used by the 0.18 micron SOI CMOS process.
The thin polysilicon gate of the SOI CMOS transistor advantageously exhibits a reduced contact-to-polysilicon capacitance, a reduced metal one (M1) to polysilicon capacitance and a reduced fringing capacitance (between the polysilicon and the source/drain regions of the SOI CMOS transistor), thereby resulting in a lower off-capacitance (COFF) of the associated RF switch. In addition, the thin polysilicon gate of the SOI CMOS transistor inhibits the polysilicon depletion effect, advantageously resulting in a lower on-resistance (RON) of the associated RF switch.
The present invention also includes methods for fabricating RF switches having SOI CMOS transistors with polysilicon gates having reduced thicknesses. The present invention will be more fully understood in view of the following description and drawings.
In general, the present invention includes an RF switch that includes a plurality of n-channel SOI CMOS transistors connected in series. The n-channel SOI CMOS transistors are fabricated in accordance with a conventional SOI CMOS process node, with the exception of the formation of the polysilicon gate layer. In accordance with the present invention, the polysilicon gate layer is thinner than a polysilicon layer typically associated with the conventional SOI CMOS process node. For example, n-channel SOI CMOS transistors may be fabricated substantially in accordance with a 0.18 micron SOI CMOS process node. The polysilicon gate layer of a 0.18 SOI CMOS process node typically has thicknesses of about 2000 Angstroms. However, in accordance with the present invention, the polysilicon gate layer is fabricated to have a thickness less than about 1450 Angstroms. For example, the polysilicon gate layer may have a thickness in the range of about 1350 to 1150 Angstroms. In another embodiment, the polysilicon gate layer may have a thickness of about 1250 Angstroms. In another embodiment, the 0.18 micron SOI CMOS process is modified to provide a polysilicon gate layer having a thickness that is less than or equal to about 70% of the thickness of a conventional polysilicon gate layer used by the 0.18 micron SOI CMOS process. The thinner polysilicon gate layer results in associated SOI CMOS transistors having a lower off-capacitance (COFF) and a lower on-resistance (RON). As a result, an RF switch constructed from such SOI CMOS transistors advantageously exhibits a reduced RON×COFF value. The present invention is described in more detail below.
N-channel SOI CMOS transistor 301 includes an n-type source region 211 (which includes lightly doped source region 211A and source contact region 211B), an n-type drain region 212 (which includes lightly doped drain region 212A and drain contact region 212B) and gate dielectric 215. A p-type channel region 209 exists between the source region 211 and the drain region 212.
P-channel SOI CMOS transistor 302 includes a p-type source region 213 (which includes lightly doped source region 213A and source contact region 213B), a p-type drain region 214 (which includes lightly doped drain region 214A and drain contact region 214B) and gate dielectric 216. An n-type channel region 210 exists between the source region 213 and the drain region 214.
Notably, transistors 301 and 302 include polysilicon gate electrodes 317 and 318, respectively, which are formed from a relatively thin polysilicon layer. The polysilicon gate electrodes 317 and 318 are thinner than the conventional polysilicon gate electrodes 217 and 218 of transistor 201 and 202 (
Dielectric sidewall spacers 319-320 and 321-322 are formed adjacent to gate electrodes 317 and 318, respectively, and metal silicide regions 323, 324, 325, 326, 327 and 328 are formed over source region 211, gate electrode 317, drain region 212, source region 213, gate electrode 318 and drain region 214, respectively. Multi-layer interconnect structure 260 (which includes pre-metal dielectric structure 230, contacts 231-234, first metal (M1) layer traces 241-244, conductive vias 245-248, inter-metal dielectric structure 240 and second metal (M2) layer traces 251-254) is formed over transistors 301-302. In the embodiments described herein, PMD structure 230 has a thickness T2 of about 4,000 to 10,000 Angstroms.
In accordance with one embodiment, transistors 301-302 and multi-layer interconnect structure 260 are fabricated in accordance with a conventional 0.18 micron SOI CMOS process node, with the exception of the polysilicon layer used to form the polysilicon gates 317-318. The polysilicon layer used to form polysilicon gates 317-318 is selected to have a thickness that is less than the thickness of a typical polysilicon layer in a conventional 0.18 micron SOI CMOS process node. For example, while the polysilicon layer in a conventional 0.18 micron SOI CMOS process node may have a typical thickness of about 2000 Angstroms (see, e.g.,
Various parasitic capacitances C1-C6 are associated with polysilicon gate electrode 317. These parasitic capacitances include, for example, capacitance C1 (between polysilicon gate 317 and source region 211), capacitance C2 (between polysilicon gate 317 and contact 231), capacitance C3 (between polysilicon gate 317 and M1 trace 241), capacitance C4 (between polysilicon gate 317 and M1 trace 242), capacitance C5 (between polysilicon gate 317 and contact 232), and capacitance C6 (between polysilicon gate 317 and drain region 212). These parasitic capacitances C1-C6 all contribute to the off-capacitance (COFF) of transistor 317. The capacitances C1-C6 are dependent upon the lateral surface area of polysilicon gate 317. Similarly, the capacitances CA-CF are dependent upon the lateral surface area of polysilicon gate 217 (
Polysilicon gate electrode 317 is exposed during the formation (e.g., implantation) of n-type source/drain regions 211-212, such that polysilicon gate electrode 317 is doped to an n-type conductivity. Within a relatively thick polysilicon gate electrode (e.g., polysilicon gate electrode 217), such n-type doping can result in the formation of an inversion layer within the gate electrode when a positive voltage is applied to the gate electrode (to turn on the transistor). As described above, this inversion layer results in the formation of a potential barrier within the gate electrode 217, such that the full voltage applied to the gate electrode is not applied to the channel region of the transistor. The reduced thickness T1 of polysilicon gate electrode 317 results in a higher n-type dopant concentration within gate electrode 317 (when compared with the n-type dopant concentration within gate electrode 217), thereby inhibiting the formation of an inversion layer within the gate electrode 317 when a positive voltage is applied to the gate electrode 317 to turn on transistor 301. Elimination/reduction of the inversion layer results in a higher voltage being applied to the channel region 209 of transistor 301, effectively reducing the on-resistance of transistor 301. Thus, if a 2.5 Volt control voltage is applied to gate electrode 317, then the channel region 209 is biased to a voltage of about 2.5 Volts to turn on transistor 301.
In accordance with one embodiment of the present invention, transistors similar to n-channel SOI CMOS transistor 301 are connected in series using the interconnect structure of
Although the invention has been described in connection with several embodiments, it is understood that this invention is not limited to the embodiments disclosed, but is capable of various modifications, which would be apparent to a person skilled in the art. Thus, the invention is limited only by the following claims.
