Patent Application
20180005887
The present invention relates in general to forming interconnect vias in integrated circuits (ICs). More specifically, the present invention relates to improved systems, fabrication methodologies and resulting structures for through-silicon vias (TSVs) that utilize a high purity low-void conductive lining material and a conductive fill, are planar at front and back surfaces of the host wafer to facilitate downstream IC fabrication processes, and can be fabricated over a wide range of via aspect-ratios.
Embodiments of the present invention are directed to a method of forming a conductive via. The method includes forming an opening in a substrate and forming a conductive material along sidewall regions of the opening, wherein the conductive material occupies a first portion of an area within the opening. The method further includes forming a conductive fill in a second portion of the area within the opening, wherein at least one surface of the conductive material and at least one surface of the conductive fill are substantially coplanar with a front surface of the substrate.
Embodiments of the present invention are further directed to a method of forming a conductive via. The method includes forming an opening in a substrate and forming a layer of superconducting material along sidewall regions of the opening, wherein the layer of superconducting material occupies a first portion of an area within the opening. The method further includes filling a second portion of the area within the opening with a conductive material, wherein the opening extends through the substrate from a front surface of the substrate to a back surface of the substrate, wherein at least one surface of the layer of superconducting material and at least one surface of the conductive fill are substantially coplanar with the front surface of the substrate, wherein at least one second surface of the layer of superconducting material is substantially coplanar with the back surface of the substrate, and wherein an electrical conducting path is provided from the at least one surface of the layer of superconducting material to the at least one second surface of the layer of superconducting material.
Embodiments of the present invention are further directed to a conductive via having an opening in a substrate and a conductive material along sidewall regions of the opening, wherein the conductive material occupies a first portion of an area within the opening. The conductive via further includes a conductive fill in a second portion of the area within the opening, wherein at least one surface of the conductive material and at least one surface of the conductive fill are substantially coplanar with a front surface of the substrate.
Additional features and advantages are realized through the techniques described herein. Other embodiments and aspects are described in detail herein. For a better understanding, refer to the description and to the drawings.
The subject matter which is regarded as the present invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other features and advantages are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:
In the accompanying figures and following detailed description of the embodiments, the various elements illustrated in the figures are provided with three or four digit reference numbers. The leftmost digit(s) of each reference number corresponds to the figure in which its element is first illustrated.
It is understood in advance that, although this description includes a detailed description of the formation and resulting structures for a specific type of via (i.e., a TSV), implementation of the teachings recited herein are not limited to a particular type of via or integrated IC architecture. Rather embodiments of the present invention are capable of being implemented in conjunction with any other type of via or IC architecture, now known or later developed.
Various embodiments of the present invention are described herein with reference to the related drawings. Alternative embodiments can be devised without departing from the scope of this invention. It is noted that various connections and positional relationships (e.g., over, below, adjacent, etc.) are set forth between elements in the following description and in the drawings. These connections and/or positional relationships, unless specified otherwise, can be direct or indirect, and the present invention is not intended to be limiting in this respect. Accordingly, a coupling of entities can refer to either a direct or an indirect coupling, and a positional relationship between entities can be a direct or indirect positional relationship. As an example of an indirect positional relationship, references in the present description to forming layer “A” over layer “B” include situations in which one or more intermediate layers (e.g., layer “C”) is between layer “A” and layer “B” as long as the relevant characteristics and functionalities of layer “A” and layer “B” are not substantially changed by the intermediate layer(s).
The following definitions and abbreviations are to be used for the interpretation of the claims and the specification. As used herein, the terms “comprises,” “comprising,” “includes,” “including,” “has,” “having,” “contains” or “containing,” or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a composition, a mixture, process, method, article, or apparatus that comprises a list of elements is not necessarily limited to only those elements but can include other elements not expressly listed or inherent to such composition, mixture, process, method, article, or apparatus.
Additionally, the term “exemplary” is used herein to mean “serving as an example, instance or illustration.” Any embodiment or design described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments or designs. The terms “at least one” and “one or more” is understood to include any integer number greater than or equal to one, i.e. one, two, three, four, etc. The terms “a plurality” can be understood to include any integer number greater than or equal to two, i.e. two, three, four, five, etc. The term “connection” can include both an indirect “connection” and a direct “connection.”
For the sake of brevity, conventional techniques related to semiconductor device and IC fabrication may not be described in detail herein. Moreover, the various tasks and process steps described herein can be incorporated into a more comprehensive procedure or process having additional steps or functionality not described in detail herein. In particular, various steps in the manufacture of semiconductor devices and semiconductor-based ICs are well known and so, in the interest of brevity, many conventional steps will only be mentioned briefly herein or will be omitted entirely without providing the well-known process details.
By way of background, however, a more general description of the semiconductor device fabrication processes that can be utilized in implementing one or more embodiments of the present invention will now be provided. Although specific fabrication operations used in implementing one or more embodiments of the present invention can be individually known, the described combination of operations and/or resulting structures of the present invention are unique. Thus, the unique combination of the operations described in connection with the fabrication of a via according to the present invention utilize a variety of individually known physical and chemical processes performed on a semiconductor (e.g., silicon) substrate, some of which are described in the following immediately following paragraphs.
In general, the various processes used to form a micro-chip that will be packaged into an IC fall into four general categories, namely, film deposition, removal/etching, semiconductor doping and patterning/lithography. Deposition is any process that grows, coats, or otherwise transfers a material onto the wafer. Available technologies include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE) and more recently, atomic layer deposition (ALD) among others. Removal/etching is any process that removes material from the wafer. Examples include etch processes (either wet or dry), and chemical-mechanical planarization (CMP), and the like. Semiconductor doping is the modification of electrical properties by doping, for example, transistor sources and drains, generally by diffusion and/or by ion implantation. These doping processes are followed by furnace annealing or by rapid thermal annealing (RTA). Annealing serves to activate the implanted dopants. Films of both conductors (e.g., poly-silicon, aluminum, copper, etc.) and insulators (e.g., various forms of silicon dioxide, silicon nitride, etc.) are used to connect and isolate transistors and their components. Selective doping of various regions of the semiconductor substrate allows the conductivity of the substrate to be changed with the application of voltage. By creating structures of these various components, millions of transistors can be built and wired together to form the complex circuitry of a modern microelectronic device.
Fundamental to the above-described fabrication processes is semiconductor lithography, i.e., the formation of three-dimensional relief images or patterns on the semiconductor substrate for subsequent transfer of the pattern to the substrate. In semiconductor lithography, the patterns are a light sensitive polymer called a photo-resist. To build the complex structures that make up a transistor and the many wires that connect the millions of transistors of a circuit, lithography and etch pattern transfer steps are repeated multiple times. Each pattern being printed on the wafer is aligned to the previously formed patterns and slowly the conductors, insulators and selectively doped regions are built up to form the final device.
Semiconductor devices are used in a variety of electronic and electro-optical applications. ICs are typically formed from various circuit configurations of semiconductor devices (e.g., transistors, capacitors, resistors, etc.) and conductive interconnect layers (known as metallization layers) formed on semiconductor wafers. Alternatively, semiconductor devices can be formed as monolithic devices, e.g., discrete devices. Semiconductor devices and conductive interconnect layers are formed on semiconductor wafers by depositing many types of thin films of material over the semiconductor wafers, patterning the thin films, doping selective regions of the semiconductor wafers, etc.
In contemporary semiconductor fabrication processes, a large number of semiconductor devices and conductive interconnect layers are fabricated in and on a single wafer. The conductive interconnect layers serve as a network of pathways that transport signals throughout an IC, thereby connecting circuit components of the IC into a functioning whole and to the outside world. Conductive interconnect layers vary in number and type depending on the complexity of the device. Interconnect layers are themselves interconnected by a network of holes (or vias) formed through the IC. For example, a through-silicon via (TSV) is an electrical contact that passes completely through the semiconductor wafer or die. In multilevel IC configurations, for example, a TSV can be used to form vertical interconnections between a semiconductor device located on one level of the IC and an interconnect layer located on another level of the IC. As IC feature sizes continue to decrease, the aspect ratio, (i.e., the ratio of height/depth to width) of features such as vias generally increases. With narrower, taller (i.e., higher-aspect-ratio) vias, the resistivity of the via must be kept sufficiently low. Otherwise, the via can fail, possibly causing failure of the entire IC. Fabricating intricate structures of conductive interconnect layers and vias within an increasingly smaller IC footprint is one of the most process-intensive and cost-sensitive portions of semiconductor IC fabrication.
In its simplest configuration, a TSV is formed by creating a hole or opening through the semiconductor wafer at a desired location, and then filling the via with conductive material, thereby providing a solid metal contact that extends from a front side of the wafer to a back side of the wafer. There are several considerations in forming TSVs. For example, in order to be compatible with downstream processing techniques, the conductive metal fill of the via must be substantially planar with the front side of the wafer and the back side of the wafer. Additionally, in order to minimize downstream fabrication problems, it is necessary to completely fill the via with conductive material in a manner that leaves no voids, which is difficult to do using known via fabrication techniques. To facilitate filling of the via, relatively narrow (i.e., high-aspect-ratio) vias are often used because is it generally accepted that, using known via fabrication techniques, it is easier to completely fill a relatively narrow via than a relatively wide (i.e., low-aspect-ratio) via. Higher-aspect-ratio (i.e., taller) vias are also advantageous because they take up less wafer/chip space and cause less stress to the wafer/chip.
Known deposition techniques for filling a via opening/hole with conductive material require tradeoffs. For example, chemical vapor deposition (CVD) is considered to be compatible with depositing material within a narrow, high-aspect-ratio space. However, because the CVD deposited gas is a mixture of the desired conductive material and a carrier organic gas, the conductive material remaining after CVD is less pure than other deposition procedures, such as physical vapor deposition (PVD). PVD is a line-of-sight process in which a desired fill material (e.g., copper) is sputtered (or knocked) from a target into the via opening/hole. PVD and similar deposition techniques result in a very pure conductive material fill because only the material of interest is deposited in the via opening/hole. However, because PVD is a line-of-sight process, using PVD to create conductive material fill within a narrow, high-aspect-ratio via opening/hole having perpendicular sidewalls is a challenge. For example, applying a line-of-sight deposition process in a narrow, low-aspect-ratio via opening/hole can result in the space between the via opening/hole sidewalls being filled before the bottom of the via opening/hole (due to the sticking coefficient at the upper edges of the sidewalls), which results in voids at the bottom of the via opening/hole and overfill at the top of the via opening/hole. The presence of voids in the via conductive material causes problems in downstream fabrication processes, and the overfilled conductive material requires additional post-deposition processing operations in order to planarize the overfill down to the wafer surface. Although using a relatively wide, low-aspect-ratio via would make the via more compatible with a line-of-sight deposition process, as previously noted, it is generally accepted that a relatively wide, low-aspect-ratio via is harder to completely fill with conductive material using known via and conductive material fill formation techniques.
Accordingly, it would be beneficial to provide systems, fabrication methodologies and resulting structures for TSVs that utilize high purity low-void conductive material, are planar with the front and back surfaces of the wafer, and are less dependent than known techniques on the aspect-ratio of the via.
Embodiments of the present invention provide improved systems, fabrication methodologies and resulting structures for TSVs that utilize a high purity low-void conductive lining material that surrounds portions of a conductive material fill. In one or more embodiments, the conductive material fill is applied using an injection molded soldering (IMS). In one or more embodiments, the TSV structure is planar with front and back surfaces of the wafer to facilitate downstream IC fabrication processes, and can be fabricated over a range of via aspect-ratios. According to one or more embodiments, the via can be fabricated by forming an opening from a front surface to a back surface of a semiconductor substrate. The opening is then partially filled with a conductive material. In one or more embodiments, the partial filling of the opening includes providing conductive material along some or all of the via sidewalls to form, in effect, a conductive material liner or shell along the sidewalls of the opening. In one or more embodiments, the conductive material liner extends along the sidewalls of the via opening from a front surface of the wafer to the back surface of the wafer, thereby providing an electrically conductive path extending from a front wafer surface through the conductive liner to a back surface of the wafer. In one or more embodiments, the conductive liner is formed using a damascene process. In one or more embodiments, a line-of-sight deposition process such as PVD can be used to form the conductive liner, which results in a conductive liner having high purity and also allows a wide range of conductive materials. In one or more embodiments, the partially filled conductive material is a superconducting material.
In one or more embodiments, after the partial fill, one or more wetting layers are applied over the partial fill, and then the remaining space within the via opening is filled with a conductive fill material. In one or more embodiments, the conductive fill material is injection molded solder. In one or more embodiments, the injection molded solder is a superconducting material such as indium (In). In one or more embodiments, the injection molded solder is a superconducting alloy material such as InSn. In one or more embodiments, the wetting layers are not superconducting. However, because the wetting layers are electrically shunted by the conductive liner and the conductive fill material, minimal loss or dissipation occurs in the wetting layers, particularly for embodiments wherein both the conductive liner and the conductive fill are superconducting materials. In such embodiments, the superconducting liner is sufficiently thick (on the order of the London penetration depth of the material(s)) in order to prevent propagation of high frequency radiation through the superconducting liner into the wetting layers. Further, if the wetting layers are sufficiently thin, after deposition of the superconducting material fill, the wetting layers can alloy such that they also exhibit superconducting properties. In one or more embodiments, the wetting layers can become superconducting by a phenomenon known as “proximity effect,” whereby non-superconducting metals can become superconducting by merely being close to the superconducting metal. This occurs by having the superconducting paired electrons (responsible for zero resistance) leak into the normal metal. This is a diffusion process, which can occur when there is a clean interface between the normal and superconducting metal films. The diffusion of superconducting Cooper pair electrons extends over a limited distance. Therefore, if the non-superconducting wetting layers are sufficiently thin, and if the interfaces are sufficiently clean, they can effectively be superconducting due to the proximity effect. The resulting conductive liner and conductive fill structure is then integrated by making contact to the top and bottom ground planes or to the signal carrying lines on each wafer surface.
The described conductive material liner with conductive fill TSV structure is compatible with both high-aspect ratio (e.g., aspect ratios above about 4:1) and lower-aspect-ratio (e.g., aspect ratios between about 2:1 and about 4:1), particularly for embodiments wherein the conductive material liner is a superconducting material. The described liner and fill structures and fabrication methodologies eliminate voids in the via. The conductive liner, wetting layers and the conductive fill each provide surfaces that are substantially coplanar with the front and back surfaces of the wafer, which is required for effective downstream wafer fabrication operations (e.g., operations that require the uniform deposition of a photoresist layer over the wafer). The described conductive material liner with conductive fill TSV structures is particularly useful where the conductive fill material is a superconducting material and where the operating environment is cryogenic.
Turning now to a more detailed description of the present invention,
Via structure 100 can be formed by forming (e.g., using reactive ion etching (RIE)) an opening through substrate 102, partially filling (e.g., using a damascene process) the opening with conductive (e.g., superconducting) liner 110 and wettable layer stack 115. Wettable layer stack 115 is then ground and polished back (e.g., using chemical mechanical polishing (CMP)) until wettable layer stack 115 is only present in the via opening. The remaining space within the via opening is filled with conductive material fill 120. In one or more embodiments, conductive material fill 120 is injection molded solder that is inserted into the via opening using an injection-molded soldering (IMS) technique. The process of IMS melts bulk solder and dispenses same through an IMS head into the remaining space within the via opening. In one or more embodiments, the IMS head is scanned over the substrate including the via opening. The molten solder is thereafter cooled so that the solder solidifies. In one or more embodiments, the solder is In, InSn or other superconducting solder alloys that have a melting temperature that is consistent with IMS tooling. Other devices, interconnect layers and conductive vias (shown collectively at 108) are then formed in or on substrate 102 using processing operations that include patterning and etching conductive liner 110 and the fabrication of junctions (shown at 108).
Via structure 200 can be formed by forming (e.g., using reactive ion etching (RIE)) an opening through first substrate 202, partially filling (e.g., using a damascene process) the opening with conductive (e.g., superconducting) liner 210 and wettable layer stack 215. Wettable layer stack 215 is then ground and polished back (e.g., using CMP) until wettable layer stack 215 is only present in the via opening. The remaining space within the via opening is filled with conductive material fill 220. In one or more embodiments, conductive material fill 220 is injection-molded solder that is inserted into the via opening using an injection-molded soldering (IMS) technique. The process of IMS melts bulk solder and dispenses same through an IMS head into the remaining space within the via opening. In one or more embodiments, the IMS head is scanned over the substrate including the via opening. The molten solder is thereafter cooled so that the solder solidifies. In one or more embodiments, the solder is In, InSn or other superconducting solder alloys that have a melting temperature that is consistent with IMS tooling. Via structure 200 is then integrated by making contact to front liner surface 212 and back liner surface 214.
Turning now to
In
In
In
Thus, it can be seen from the foregoing detailed description and accompanying illustrations that one or more embodiments of the present invention provide systems, methodologies and resulting structures for forming a conductive via. Technical effects and benefits of the present invention include forming the conducive via as a lined, conductive material filled TSV, wherein the lining and the fill are formed from conductive materials that provides the conduction path of the TSV. In one or more embodiments, the liner is a superconducting material. In one or more embodiments, the fill material is a superconducting material. The described TSV structure can be formed across a range of via aspect ratios, including aspect ratios that would traditionally be considered high (e.g., above about 4:1), as well as aspect ratios that would traditionally be considered low (e.g., between about 2:1 and about 4:1). The conductive liner of the described TSV can be formed with high purity deposition techniques such as PVD, and the fill material can be deposited using an IMS deposition process. The described TSV structure is substantially coplanar with the front and back surfaces of its host wafer, which facilitates downstream processing that would be compromised by uneven wafer surfaces. The PVD formed conductive liner and the IMS formed conductive fill of the described TSV sufficiently fill the via opening such that substantially no voids are left in the via after formation of the conductive liner and the conductive fill. Where both the conductive liner and the conductive fill are superconducting materials, the teachings of the present invention provide methods and structures for superconducting vias that provide appropriate signal propagation in applications such as RSFQ (rapid single flux quantum) circuitry, as well as ground stitching to control chip modes and slot line modes.
In some embodiments, various functions or acts can take place at a given location and/or in connection with the operation of one or more apparatuses or systems. In some embodiments, a portion of a given function or act can be performed at a first device or location, and the remainder of the function or act can be performed at one or more additional devices or locations.
The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the form described. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.
The flowchart and block diagrams in the figures illustrate the functionality and operation of possible implementations of systems and methods according to various embodiments of the present invention. In some alternative implementations, the functions noted in the block can occur out of the order noted in the figures. For example, two blocks shown in succession can, in fact, be executed substantially concurrently, or the blocks can sometimes be executed in the reverse order, depending upon the functionality involved. The actions can be performed in a differing order or actions can be added, deleted or modified. Also, the term “coupled” describes having a signal path between two elements and does not imply a direct connection between the elements with no intervening elements/connections therebetween. All of these variations are considered a part of the invention.
The terms “about” or “substantially” are intended to include the degree of error associated with measurement of the particular quantity based upon the equipment available at the time of filing the application. For example, “about” can include a range of ±8% or 5%, or 2% of a given value.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, element components, and/or groups thereof.
While the present invention has been described in detail in connection with only a limited number of embodiments, it should be readily understood that the present invention is not limited to such described embodiments. Rather, the present invention can be modified to incorporate any number of variations, alterations, substitutions or equivalent arrangements not heretofore described, but which are commensurate with the spirit and scope of the present invention. Additionally, while various embodiments of the present invention have been described, it is to be understood that aspects of the present invention can include only some of the described embodiments. Accordingly, the present invention is not to be seen as limited by the foregoing description, but is only limited by the scope of the appended claims.
The invention described in the present description was made with government support under government contract number H98230-13-D-0173 awarded by the National Security Agency. The government has certain rights in the invention.
