Patent Application
20230402457
The disclosure relates in general to a semiconductor structure and the method for fabricating the same, and more particularly to a transistor structure and the method for fabricating the same.
The success of low power integrated circuits industry is primarily due to the complementary metal oxide semiconductor (CMOS) technology, wherein the key role of integrated circuits is the MOSFET (metal-oxide-semiconductor field-effect transistor). Although advanced technology nodes (such as 3-10 nm) for Fin structure transistors are frequently used in high performance computing applications (such as Artificial Intelligence AI, CPU, GPU, etc.), the mature technology nodes (such as 12-30 nm) for planar MOSFET are still popular in many IC applications, such as, power management IC, DRAM, and MCU chip.
However, during the previously mentioned thermal annealing process, the implanted n-type or p-type dopants will unavoidably diffuse into different directions and enlarge the area of the source and drain regions. The larger the area of the source and drain regions due to the thermal annealing processes, the shorter of the effective channel length between the source and drain regions, and such reduced effective channel length (Leff) will incur short channel effect (SCE). An MOS transistor could be considered to be shorted when the Leff is comparable to the source/drain junction depletion width. When the Leff is further reduced, the drain current finally cannot be turned off and the gate has no control over the charge. The so-called punch-through effect poses a severe problem for miniaturized devices. Therefore, to reduce the impact of SCE, it is common to reserve longer gate length to accommodate the diffusion of n-type or p-type dopants due to thermal annealing. Using technology node of 25 nm (Lamda or A) as an example, the reserved gate length would be 60 nm to 100 nm. Thus, the size of the transistor could not be proportionally shrunk.
Other problems are introduced or getting worse in current planar MOSFETs made by mature technology nodes of 12 nm to 30 nm: (1) All junction leakages resulted by junction formation processes, such as forming lightly-doped drain (LDD) structure into the substrate/well regions, forming n+ source/drain structures into p-substrate and forming p+ source/drain structures into n-well, are getting worse to control, since leakage currents occur through both perimeter and bottom areas where extra damages like vacant traps for holes and electrons are harder to be reconciled due to lattice imperfections which have been created by ion-implantation; (2) In addition, since the ion-implantation to form the LDD structure (or the n+/p junction or the p+/n junction) works like bombardments in order to insert ions from the top of a silicon surface straight down to the substrate, it is hard to create uniform material interfaces with lower defects from the source and drain regions to the channel and the substrate-body regions since the dopant concentrations are non-uniformly distributed vertically from the top surface with higher doping concentrations down to the junction regions with lower doping concentrations; (3) It's getting harder to align the LDD junction edge to the edge of gate structure in a perfect position by only using the conventional self-alignment method of using gate, spacer and ion-implantation formation. In addition, the thermal annealing process for removing the ion-implantation damages must count on high temperature processing techniques such as rapid thermal annealing method by using various energy sources or other thermal processes. One problem thus created is that a gate-induced drain lowering (GIDL) leakage current is badly induced due to a gated diode structure formed in the gate-to-source/drain regions and hard to be controlled regardless the fact that it should be minimized to reduce leakage currents; the other problem as created is that the effective channel length is difficult to be controlled and so the short channel effect is hardly minimized. (4) As the dimensions of the transistors are continuously scaled down, manufacture parameter fluctuations cause undesirable result and impact on the circuit performance, for example, line edge roughness (LER), random dopant fluctuations (RDFs) and poly grain granularity (PGG), will unavoidably incur the variation of gate length (or the effective channel length) and then the threshold voltage V T variation, as shown in
Therefore, there is a need to provide an advanced transistor structure and the processing method therefor to overcome the drawbacks of the prior art.
This invention discloses several new concepts of realizing a novel transistor structure, such as a planar transistor, which greatly improves or even solved most of the problems as stated above, such as minimizing current leakages, increasing channel-conduction performance and control, optimizing functions of source and drain regions such as making better their conductance to metal interconnections and their closest physical intact to the channel region with a seamless orderly crystalline lattice matchup.
One aspect of the present disclosure is to provide a transistor structure, wherein the transistor structure includes a semiconductor substrate, a gate region, a spacer, a trench, an isolation region and a conductive region. The semiconductor substrate has an active region which has a semiconductor surface. The gate region has a first conductive portion over the semiconductor surface of the semiconductor substrate in the active region and a second conductive portion over the first conductive portion. The spacer covers a sidewall of the gate region. The trench is formed below the semiconductor surface of the semiconductor substrate in the active region. The isolation region is in the trench. The conductive region is positioned on the isolating region. Wherein a lateral length of the first conductive portion is greater than that of the second conductive portion.
In one embodiment of the present disclosure, the isolation region includes a vertical layer and a bottom layer; an edge of the vertical layer is underneath the spacer; and a gap between the edge of the vertical layer and an edge of the first conductive portion of the gate region is less than 3 nm.
In one embodiment of the present disclosure, the conductive region is independent from the semiconductor substrate.
In one embodiment of the present disclosure, the transistor structure is a planar NMOS transistor, the conductive region includes an N type LDD region and an N type heavily doped region contacting with the N type LDD region.
In one embodiment of the present disclosure, a top surface of the N type LDD region is fully covered by the spacer.
In one embodiment of the present disclosure, the isolation region further includes a filling dielectric region on the bottom layer, and a top surface of the vertical layer is aligned or substantially aligned with that of the filling dielectric region.
In one embodiment of the present disclosure, the vertical layer and the bottom layer of the first isolation region are made of thermal oxide, and the filling dielectric region is made of a spin-on-dopant (SOD) layer.
In one embodiment of the present disclosure, the N type LDD region is on the vertical layer and the N type heavily doped region is on the filling dielectric region.
In one embodiment of the present disclosure, a vertical thickness of the N type LDD region is less than 20 nm, and a lateral width of the N type LDD region is around 20 nm.
In one embodiment of the present disclosure, the transistor structure further includes a shallow trench isolation (STI) region below the semiconductor surface of the semiconductor substrate in the active region and an extending dielectric layer above the STI region, wherein the extending dielectric layer includes a vertical portion, and a top surface of the vertical portion is higher than the semiconductor surface of the semiconductor substrate in the active region.
In one embodiment of the present disclosure, the conductive region is confined by the vertical portion of the extending dielectric layer.
Another aspect of the present disclosure is to provide a transistor structure, wherein the transistor structure includes a semiconductor substrate, a first trench, a second trench, a first isolation region, a second isolation region, a gate region, a channel region, a drain region and a source region. The semiconductor substrate has an active region which has a semiconductor surface. The first trench and a second trench are both formed below the semiconductor surface. The first isolation region is in the first trench. The second isolation region is in the second trench. The gate region has a first conductive portion over the semiconductor surface of the semiconductor substrate in the active region and a second conductive portion over the first conductive portion. The channel region is under the gate region. The drain region is on the first isolation region. The source region is on the second isolation region. Wherein a lateral length of the first conductive portion is different from that of the second conductive portion, and a distance between an edge of the first isolation region and an edge of the second isolation region is greater than the lateral length of the first conductive portion.
In one embodiment of the present disclosure, the distance between the edge of the first isolation region and the edge of the second isolation region is greater than the length of the lateral length of the first conductive portion around 4 nm.
In one embodiment of the present disclosure, the transistor structure further includes a STI region below the semiconductor surface of the semiconductor substrate in the active region and an extending dielectric layer above the STI region, wherein the extending dielectric layer includes a vertical portion surrounding the active region, and a top surface of the vertical portion is higher than the semiconductor surface of the semiconductor substrate in the active region.
In one embodiment of the present disclosure, the drain region and the source region are confined by the vertical portion of the extending dielectric layer.
Yet another aspect of the present disclosure is to provide a transistor structure, wherein the transistor structure includes a semiconductor substrate and a gate region. The semiconductor substrate has an active region which has a semiconductor surface. The gate region has a first conductive portion over the semiconductor surface of the semiconductor substrate in the active region and a second conductive portion over the first conductive portion. Wherein a lateral length of the first conductive portion is greater than that of the second conductive portion.
In one embodiment of the present disclosure, the transistor structure further includes a first spacer and a second spacer, wherein the second spacer contacts sidewalls of the second conductive portion rather than the first conductive portion, and the first spacer contacts sidewalls of the first conductive portion.
In one embodiment of the present disclosure, an edge of the first conductive portion is aligned or substantially aligned with an edge of the second spacer.
In one embodiment of the present disclosure, the second conductive portion includes a metal containing material, and the first conductive portion is made of a first semiconductor material which is different from the metal containing material.
In one embodiment of the present disclosure, the metal containing material of the second conductive portion is surrounded by the second spacer.
In one embodiment of the present disclosure, the second spacer is made of SiN.
In one embodiment of the present disclosure, the transistor structure further includes a gate dielectric layer under the first conductive portion, and a lateral length of the gate dielectric layer is greater than that of the second conductive portion.
In one embodiment of the present disclosure, a length of the gate region is immune from a gate line edge roughness.
In one embodiment of the present disclosure, a vertical thickness of the first conductive portion is 10 nm to 15 nm.
In one embodiment of the present disclosure, the transistor structure further includes a first spacer and a second spacer, wherein the second spacer contacts sidewalls of the second conductive portion and is positioned on a top surface of the first conductive portion.
The above and other aspects of the disclosure will become better understood with regard to the following detailed description of the preferred but non-limiting embodiment(s). The following description is made with reference to the accompanying drawings:
The present disclosure provides a transistor structure and the processing method thereof. The above and other aspects of the disclosure will become better understood by the following detailed description of the preferred but non-limiting embodiment(s). The following description is made with reference to the accompanying drawings:
Several embodiments of the present disclosure are disclosed below with reference to accompanying drawings. However, the structure and contents disclosed in the embodiments are for exemplary and explanatory purposes only, and the scope of protection of the present disclosure is not limited to the embodiments. It should be noted that the present disclosure does not illustrate all possible embodiments, and anyone skilled in the technology field of the disclosure will be able to make suitable modifications or changes based on the specification disclosed below to meet actual needs without breaching the spirit of the disclosure. The present disclosure is applicable to other implementations not disclosed in the specification.
A simple planar NMOS which made in a p-type substrate (or p-well) is used as an example to illustrate the manufacture processes and key attributes of this invention, while similar processes and structures could also be applied to a planar PMOS transistor which is made in an N-well of the p-type substrate.
The flowing description discloses the step for forming a transistor structure 20 according to one embodiment of the present disclosure. In the present embodiment of the present disclosure, the transistor structure 20 may include a planar CMOS device which includes a PMOS transistor 21 and a NMOS transistor 22. The forming of the transistor structure 20 includes steps as follows:
Referring to Step S21: forming a semiconductor substrate having at least one active region defined on a semiconductor surface of the semiconductor substrate by at least one STI region.
In the present embodiment, a semiconductor substrate (such as Si substrate) 201 is provided; and an N-well and a P-well are formed in the semiconductor substrate 201, such as, by at least two ion-implantation process carried on the semiconductor surface 201s (i.e., the original silicon surface (OSS) of the Si substrate). The semiconductor substrate 201 is then etched to form a plurality of trenches 201T; and the trenches 201T are filed with dielectric material to form the STI regions 202 surrounding the N-well and P-well respectively. Wherein the N-well surrounded by the STI regions 202 can serve as an active region of the PMOS transistor 21; and the P-well surrounded by the STI regions 202 can serve as an active region of the NMOS transistor 22.
It is noticed that the original silicon surface (OSS) of the Si substrate (the semiconductor surface 201s of the semiconductor substrate 201) is higher than the top surface 202s of the STI 202. For example, in some embodiments of the present disclosure, a distance H between the semiconductor surface 201s (the original silicon surface (OSS) of the Si substrate) and the top surface 202s of the STI 202 measured along a direction perpendicular to the semiconductor surface 201s is about 20 nm to 40 nm (such as about 30 nm).
Referring to Step S22: forming an extending dielectric layer above the STI region, wherein the extending dielectric layer includes a vertical portion and a top surface of the vertical portion is higher than the semiconductor surface of the semiconductor substrate in the active region. The forming of the extending dielectric layer includes sub-steps S221-S223.
Referring to sub-Steps S221 and S222: sequentially depositing a silicon oxide layer 203, a SiN layer 204 and a SOD layer to cover the semiconductor surface, and etching back the SOD layer, such that a top surface of the remaining SOD layer 205 is aligned with an exposed portion of the SiN layer over the at least one active region.
In order to provide a concise and clear description, merely a portion of the planar CMOS device and the processing structures for forming the same are taken as an example and depicted. For example,
In the present embodiment, the silicon oxide layer 203, the SiN layer 204 and the SOD layer 205 are formed by a series deposition processes (e.g., low pressure chemical vapor deposition (LPCVD)) performed sequentially on the semiconductor surface 201s of the semiconductor substrate 201 and the top surface of the STI regions 202. The silicon oxide layer 203 may be a silicon dioxide (SiO2) conformal with the semiconductor surface 201s of the semiconductor substrate 201 and the top surface of the STI regions 202; the SiN layer 204 is conformal with the silicon oxide layer 203; and the SOD layer 205 is conformal with the SiN layer 204. The silicon oxide layer 203 and the SiN layer 204 both have a thickness less than the distance H between the semiconductor surface 201s and the top surface 202s of the STI 202. In some embodiments, the silicon oxide layer 203 and the SiN layer 204 both have a thickness around 8 nm to 12 nm, such as 10 nm.
In one embodiment, the silicon oxide layer 203 at least include a first oxide portion 203a disposed on the top surface 202s of the STI 202, a second oxide portion 203b disposed on the active regions 201N and a vertical oxide portion 203v disposed on the vertical sidewalls of the P-well. The SiN layer 204 that is conformal with the SiN layer 204 also at least include a first nitride portion 204a disposed on the first oxide portion 203a, a second nitride portion 204b disposed on the second oxide portion 203b and a vertical nitride portion 204v disposed at outer of the vertical oxide portion 203v.
As shown in
Referring to sub-Step S223: etching portions of the silicon oxide layer and the SiN layer to expose the at least one active region.
In the present embodiment, an anisotropic etch (such as, a dry etching or a reactive ion etching (RIE)) is performed to remove the second oxide portion 203b of the silicon oxide layer 203 and the second nitride portion 204b of the SiN layer 204 that are not covered by the SOD layer 205 to reveal the semiconductor surface 201s of the semiconductor substrate 201 in the active region 201N.
It is noticed that the vertical oxide portion 203v of the silicon oxide layer 203 and the vertical nitride portion 204v of the SiN layer 204 may extend above the semiconductor surface 201s of the semiconductor substrate 201 (OSS) and surrounds the active region 201N (as shown in
Referring to Step S23: forming a gate region with an upper conductive portion and a lower conductive portion (such as, an upper portion) over the semiconductor surface, wherein a lateral length of the first conductive portion is greater than that of the second conductive portion. The forming of the gate region includes sub-steps S231-S233:
Referring to sub-step S231: sequentially forming a gate dielectric layer, a gate semiconductor layer, a barrier layer, a metal layer, a SiN cap layer and an oxide cap layer to cover the of the active region.
In some embodiment of the present disclosure, the forming of the gate dielectric layer 206 includes steps as follows: A gate dielectric material layer (such as an oxide layer or a High-K dielectric layer) is formed to cover the semiconductor surface 201s of the semiconductor substrate 201 in the active region 201N. In one embodiment, the dielectric material layer will be formed on semiconductor surface 201s of the semiconductor substrate 201 in the active region 201N.
Subsequently, a series deposition processes (e.g., low pressure chemical vapor deposition (LPCVD)) are performed to sequentially deposit the gate semiconductor layer 207, the barrier layer 208, and the metal layer 209, the SiN cap layer 210 and the oxide cap layer 211 covering the semiconductor surface 201s of the semiconductor substrate 201 in the active region 201N and the extending dielectric layer 214. In the present embodiment, the gate semiconductor layer 207 is a gate poly-silicon layer; the barrier layer 208 is a TiN/Ti composite layer; the metal layer 209 is a tungsten (W)/WSi layer; and the oxide cap layer 211 is a SiO2 layer.
Referring to sub-step S232: etching the oxide cap layer, the SiN cap layer, the metal layer, the barrier layer and the gate semiconductor layer to form the upper conductive portion of the gate region on the surface of the semiconductor substrate 201 in the active region.
In the present embodiment, the forming of the upper conductive portion 212U of the gate region 212 includes steps as follows: A patterned photoresist layer 213 is formed on the oxide cap layer 211 (as shown in
Referring to sub-step S233: forming an inner spacer contacting the sidewall of the upper conductive portion.
In the present embodiment, the forming of the inner spacer 215 includes steps as follows: A dielectric layer (such as, a SiN layer) is formed to cover the upper conductive portion 212U of the gate region 212 and the remaining portion of the SiN layer 210; and the dielectric layer is then etched to remain the portions thereof covering the remaining portion of the SiN layer 210 and sidewalls of the upper conductive portion 212U to serve as the inner spacer 215. In some embodiments of the present disclosure, an edge 212e of the upper conductive portion 212U is aligned or substantially aligned with an inner edge 215e of the inner spacer 215. The lateral thickness 215t of the inner spacer 215 is about 4 nm to 8 nm, such as 5 nm.
Referring to sub-step S234: forming a lower conductive portion of the gate region on the gate dielectric layer and beneath the upper conductive portion (such as, etch down the gate polysilicon layer 207 outside the inner SiN spacer 215).
In some embodiments of the present disclosure, the lower conductive portion 212L is disposed over the semiconductor surface 201s of the semiconductor substrate 201 in the active region 201N and the upper conductive portion 212U is disposed over the lower conductive portion 212L; and the upper conductive portion 212U includes a metal containing material, and the lower conductive portion 212L is made of a first semiconductor material which is different from the metal containing material.
In the present embodiment, the lower conductive portion 212L can be formed by performing an etching process to remove the portions of the gate semiconductor layer 207 not covered by the remaining portion of the SiN layer 210 and the inner spacer 215. Such that the remaining portion of the gate semiconductor layer 207 positioned underneath the lower conductive portion 212L and the inner spacer 215 can serve as the lower conductive portion 212L. Now the gate region 212 includes the lower conductive portion 212L (made of poly silicon) and the upper conductive portion 212U including the semiconductor pillar 207P (made of poly silicon), the remaining portions of the metal layer ((W)/WSi layer) 209 and the barrier layer 208 (TiN/Ti composite layer).
As shown in
Referring to sub-step S235: forming an outer spacer contacting the sidewall of the lower conductive portion. In the present embodiment, the forming of the outer spacer 216 includes steps as follows: A dielectric layer 216a made of a dielectric material (such as, SiO2) other than that for consisting the inner spacer 215 is formed to at least blanket over the inner spacer 215, the sidewalls of the lower conductive portion 212L, and the gate dielectric layer 206. The dielectric layer 216a is then etched to remain the portion thereof covering the sidewalls of the lower conductive portion 212L and the inner spacer 215, so as to partially expose the semiconductor surface 201s of the semiconductor substrate 201 in the active region 201N.
It is noticed that, in some embodiments of the present disclosure, the portion of the gate dielectric layer 206 not covered by the remaining portions of the SiN layer 210, the inner spacer 215 and the remaining portion of the dielectric layer 216a can be removed simultaneously by the etching process. Thus, the lateral length TD of the remaining portion of the gate dielectric layer 206 is also greater than the lateral length TU of the upper conductive portion 212U, and also greater than the lateral length TL of the lower conductive portion 212L. Moreover, the remaining portions of the SOD layer 205 and the vertical oxide portion 203v of the silicon oxide layer 203 could also be removed by the same etching process. Such that a gap 217 can be formed between the vertical nitride portion 204v of the extending dielectric layer 214 and the vertical sidewall 201v of the semiconductor substrate 201 (as shown in
Subsequently, another dielectric layer 216b made of a dielectric material (such as, SiN) other than that for consisting the dielectric layers 216a is formed to blanket over the top surface of the SiN layer 210, the inner spacer 215, the dielectric layer 216a, the exposed semiconductor surface 201s of the semiconductor substrate 201 in the active region 201N and the extending dielectric layer 214; and such dielectric material could fill the gap 217 as well. The dielectric layer 216b is then etched to partially expose the semiconductor surface 201s of the semiconductor substrate 201 in the active region 201N. The reaming portions of these two dielectric layers 216a and 216b that are disposed to cover the inner spacer 215 and gate region 212 can be combed to form the outer spacer 216.
In some embodiments of the present disclosure, since the extending dielectric layer 214 and the dielectric layer 216b are made of the same material (such as, SiN), the portions of the dielectric layer 216b remained on the extending dielectric layer 214 may enlarge the thickness of the extending dielectric layer 214. Similarly, the lateral width of the extending dielectric layer 214 may be enlarged by the remaining portions of the dielectric layer 216b disposed in the gap 217.
Referring to Step S24: forming at least one isolation region below the semiconductor surface of the semiconductor substrate in the active region. The forming of the at least one isolation region includes sub-steps S241-S243.
Referring to sub-step S241: forming at least one trench below the semiconductor surface of the semiconductor substrate in the active region.
Wherein, each of the trenches 218A and 218B has a depth measured from bottoms 218b and a vertical sidewall 218v with predetermined crystal oriented silicon (such as (110)) right under the outer spacer 216. In some embodiments, the depth of the trenches 218A and 218B may be from 100 nm to 120 nm (such as, 110 nm), and one of the sidewalls of the trenches 218A and 218B may be defined by the STI 202.
Referring to sub-step S242: forming a thermal oxide layer on the bottom and the sidewalls of the at least one trench.
In the present embodiment, a thermal oxidation process is performed to grow the thermal oxide layer 219 (such as, a silicon oxide layer) on the bottoms and the sidewalls of the trenches 218A and 2188. As shown in
In one embodiment, the thickness of the thermal oxide vertical portion 219A and the thermal oxide bottom portion 219B could be around 20 nm. However, it is important to design this thermal oxidation process such that the thickness of the thermal oxide vertical portion 219A can be very accurately controlled under both precisely controlled thermal oxidation temperature, timing and growth rate. The thermal oxidation over a well-defined silicon surface result in that 40% of the thickness of the thermal oxide vertical portion 219A extends into the transistor body (semiconductor substrate 201) from the exposed vertical sidewall 218v (with (110)-oriented silicon), and that the remaining 60% of the thickness of the thermal oxide vertical portion 219A counted as an addition part extends into the trenches 218A or 218B from the vertical sidewall 218v.
Since the thickness of the thermal oxide vertical portion 219A is very accurately controlled based on the thermal oxidation process, the edge of the thermal oxide vertical portion 219A could be controlled, such as the gap G between the edge 219e of the thermal oxide vertical portion 219A and the edge 212e of the lower conductive portion 212L of the gate region 212 is around 2 nm to 4 nm or less (as shown in
Referring to sub-step S243: filling the at least one trench with a dielectric material to form the at least one isolation region.
In the present embodiment, the dielectric material 220, such as SOD or Nitride, is deposited over the gate region 212, the SiN cap layer 210, the inner spacer 215, the outer space 216, the extending dielectric layer 214 and the active region 201 with sufficient thickness to fully fill up both the trenches 218A and 218B. An etching back process is then performed to remove the unnecessary portion of the dielectric material 220 (SOD) to leave only a suitable thickness of the dielectric material 220 (also referred to as filling dielectric regions) inside the trenches 218A and 218B. Wherein the portions of the thermal oxide layer 219 and the remaining dielectric material 220 (SOD) that are disposed in one of the trenches 218A and 218B can be combined to serve as one of the isolation regions 221, which is also referred to as a localized isolation into silicon substrate (LISS). It is noticed that the gap 222 between the semiconductor surface 201s of the semiconductor substrate 201 (OSS) and the top surface of the remaining dielectric material 220 (SOD) is 6 nm to 12 nm, such as 9 nm.
Referring to Step S25: forming at least one conductive region positioned on the at least one isolation region and being independent from the semiconductor substrate. The forming of the conductive region includes sub-steps S251-S253:
Referring to sub-step S251: forming at least one undercut below the gate region to partially expose the semiconductor substrate.
It is noted that (as shown in
Referring to sub-step S252: forming at least one first selective growth portion of the at least one conductive region in the at least one undercut.
A selective growth technique (such as, selective epitaxial growth (SEG) or other suitable technology which may be atomic layer deposition (ALD) or selective growth (ALD-SALD)) to grow the first selective growth portions 225A from the silicon surface exposed from the undercuts 223. In the present embodiment, each of the first selective growth portions 225A may have an n-type electricity serving as the LDD regions and can be used as crystalline seeds to form a new well-organized (110) lattice source/drain region of the NMOS transistor 22 across the thermal oxide layer 219. Each of the first selective growth portions 225A has a lateral thickness around 20 nm.
Referring to sub-step S253: forming at least one second selective growth portion of the at least one conductive region.
In the present embodiment, prior to forming of the second selective growth portion 225B, an optional composite dielectric layer, including a SiN layer and a SiO2 (or SiCON) layer are sequentially deposited to cover the SiN layer 210, the inner spacer 215 and the outer spacer 216, the isolation regions 221 and the extending dielectric layer 214; then the composite dielectric layer is etched by several etching process to form a composite spacer 226 covering on the outer spacer 216 and the tops of the first selective growth portions 225A (serving as the N-LDD regions). It is noticed that, since the first selective growth portions 225A (serving as the N-LDD regions) are covered by the composite spacer 226, thus an upward growth can be prevented from the first selective growth portions 225A.
Afterward, a further selective growth process is performed to grow N+ doped regions along the vertical walls of the first selective growth portions 225A with (110) orientation, so as to form the second selective growth portion 225B within the trenches 218A and 218B and extending beyond the same. Wherein, the combination of one of the first selective growth portions 225A and one of the second selective growth portions 225B both disposed in the same trench (trench 218A or 218B) may be referred to as the conductive regions 225, and serve as the source region or the drain region of the NMOS transistor 22.
In some embodiments of the present disclosure, the conductive regions 225 are confined by the extending dielectric layer 214. In the present embodiment, as shown in
Similarly, the planar PMOS transistor 21 can be formed by the same process as described above, simultaneous with the process for forming the planar NMOS transistor 22, or formed independent from the process for forming the planar NMOS transistor 22. After a series steps of down-stream process are performed, the forming of the transistor structure (e.g., the CMOS device) 20 can be implemented (as shown in
It is noticed that, in the present invention there are two or more separate steps of lateral selective growth of the source/drain regions (the conductive regions 225), the first one is lateral selective growth of the N-LDD or P-LDD region (e.g., the first selective growth portion 225A), and the second one is lateral selective growth of N+ or P+ doped regions (e.g., the second selective growth portion 225B). The growth temperature of the first step could be different form that of the second step. Moreover, the grown material (such as Si) of the first step could be different from the grown material (such as, SiGe, SiC, W, or other selective grown material) of the second step in order to reduce the resistances of Source/Drain regions or increase the stress force to the initial portions of Source/Drain regions into the channel region to increase mobility.
After this SEG processes for forming the source/drain regions (the conductive regions 225) are completed, there are some novel results achieved:
As such a newly grown silicon region is formed as described and shown in the aforementioned text, the remaining transistor formation steps can be continued to fill the entire source/drain regions with well-designed doping concentration profiles as desired. Another way of complete the active portions of source/drain regions is that, some tungsten (or other suitable metal materials) plugs can be formed in a horizontal connection to the silicon portion of source/drain for completion of the entire source/drain regions. The active channel current flowing to future metal interconnection such as a metal-1 layer is gone through LDD regions and heavily-doped conductive silicon source/drain regions to the tungsten (or other metal materials) plugs which are directly connected to Metal-1 by some good Metal-to-Metal Ohmic contact with much lower resistance than the traditional Silicon-to-Metal contact.
Of course, the present invention not only could be implemented in the planar MOSFET, but also be implemented in non-planar MOSFET, such as FinFET, Tri-gate, GAA (Gate-All-Around) transistors.
While the invention has been described by way of example and in terms of the preferred embodiment(s), it is to be understood that the invention is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.
This application claims the benefit of U.S. provisional applications Ser. No. 63/351,846 and Ser. No. 63/351,849, both filed Jun. 14, 2022, the subject matter of which is incorporated herein by reference.
| Number | Date | Country | |
|---|---|---|---|
| 63351846 | Jun 2022 | US | |
| 63351849 | Jun 2022 | US |
