TRANSISTOR STRUCTURE HAVING BURIED ISLAND REGIONS

Abstract

A semiconductor device such as a transistor includes a source region, a drain region, a semiconductor region, at least one island region and at least one gate region. The semiconductor region is located between the source region and the drain region. The island region is located in the semiconductor region. Each of the island regions differs from the semiconductor region in one or more characteristics selected from the group including resistivity, doping type, doping concentration, strain and material composition. The gate region is located between the source region and the drain region covering at least a portion of the island regions.

Description

BACKGROUND

The ability to modify the threshold voltage in a transistor is highly desirable to design complex circuits. In Silicon MOSFETs, threshold voltage is commonly tuned by the doping density in the channel. However, the change in threshold voltage in unipolar transistors is not easy. For example, the threshold voltage of unipolar n-type transistors of III-V and III-Nitride semiconductors is typically negative. Therefore these transistors are depletion-mode or normally-on devices. Although enhancement-mode or normally-off transistors are highly desirable in many applications, it can be difficult to change the threshold voltage of these transistors to positive values.

This invention describes a new structure with island regions in the gate region of a transistor. This new structure is useful for tuning the threshold voltage.

SUMMARY

In accordance with one aspect of the disclosed subject matter, a transistor is provided that includes a source region, a drain region, a semiconductor region, at least one island region and at least one gate region. The semiconductor region is located between the source region and the drain region. The island region is located in the semiconductor region. Each of the island regions differs from the semiconductor region in one or more characteristics selected from the group including resistivity, doping type, doping concentration, strain and material composition. The gate region is located between the source region and the drain region covering at least a portion of the island regions.

In accordance with another aspect of the disclosed subject matter, a diode is provided that includes a cathode region, a semiconductor region, at least one island region and an anode region. The island region is located in the semiconductor region. Each of the island regions differs from the semiconductor region in one or more characteristics selected from the group including resistivity, doping type, doping concentration, strain and material composition. The anode region covers at least a portion of the island regions.

In accordance with yet another aspect of the disclosed subject matter, a method is provided for forming a transistor having a tailored threshold voltage. In accordance with the method, at least one island region is formed in a semiconductor region. The island region is formed so that it has at least one structural and/or compositional characteristic that differs from the at least one structural and/or compositional characteristic of the semiconductor region so that the transistor has the tailored threshold voltage. A conductive electrode is formed which covers at least a portion of the island regions.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a plan view of one embodiment of a semiconductor device constructed in accordance with the teachings presented herein.

FIGS. 2 and 3 show cross-sectional views of semiconductor device of FIG. 1 taken along lines A-A′ and B-B′, respectively.

FIGS. 4( a)-4(d) show alternative embodiments of the semiconductor device taken along lines A-A′ in FIG. 1.

FIG. 5 shows the embodiment of FIG. 4(a) taken along lines B-B′ in FIG. 1.

FIGS. 6( a)-6(c) show cross-sectional views of other alternative embodiments of the semiconductor device taken along line A-A′ in FIG. 1.

FIGS. 7( a)-7(d) shows a simplified example of the processing steps that may be employed to fabricate the embodiment of the semiconductor device shown in FIGS. 2-3.

FIGS. 8( a)-8(e) shows a simplified example of the processing steps that may be employed to fabricate the embodiment of the semiconductor device shown in FIG. 4(a) in which the island regions are formed at the bottom of trenches.

DETAILED DESCRIPTION

In the following description, numerous specific details are set forth in order to provide a thorough understanding of exemplary embodiments or other examples described herein. However, it will be understood that these embodiments and examples may be practiced without the specific details. In other instances, well-known methods and procedures have not been described in detail, so as not to obscure the following description. Further, the embodiments disclosed are for exemplary purposes only and other embodiments may be employed in lieu of, or in combination with, the embodiments disclosed.

Reference throughout this specification to “one embodiment”, “an embodiment”, “one example” or “an example” means that a particular feature, structure or characteristic described in connection with the embodiment or example is included in at least one embodiment of the present invention. Thus, appearances of the phrases “in one embodiment”, “in an embodiment”, “one example” or “an example” in various places throughout this specification are not necessarily all referring to the same embodiment or example. Furthermore, the particular features, structures or characteristics may be combined in any suitable combinations and/or subcombinations in one or more embodiments or examples. In addition, it is appreciated that the figures provided herewith are for explanation purposes to persons ordinarily skilled in the art and that the drawings are not necessarily drawn to scale.

FIG. 1 shows a plan view of one embodiment of a semiconductor device 100 constructed in accordance with the teachings presented herein. FIGS. 2 and 3 show cross-sectional views of semiconductor device 100 taken along lines A-A′ and B-B′, respectively. In FIGS. 1-3 and the FIGs. that follow like elements are denoted by like reference numerals. The semiconductor device 100 in this illustrative embodiment is depicted as a transistor that is operational in an enhancement mode or a depletion-mode. However, the teachings presented herein are equally applicable to other semiconductor devices such as diodes and various power and RF devices and is not limited to the particular devices described below.

Referring to FIGS. 1-3, semiconductor device 100 includes a substrate 105 (shown in FIG. 3 only), semiconductor layer 110 disposed on substrate 105, an optional barrier layer 120 disposed over semiconductor layer 110 and an optional dielectric layer 130 disposed over barrier layer 120.

Source and drain contacts 140 and 150, respectively, are disposed in a recess extending through the barrier layer 120 and dielectric layer 130 and into the semiconductor layer 110. In this way the source and drain contacts 140 and 150 contact the semiconductor layer 110. A gate electrode 160 is disposed over the dielectric layer 130 and is located between the source and drain contacts 140 and 150.

In some embodiments semiconductor layer 110 may be an epitaxial layer that is formed on the substrate 105. In other embodiments the semiconductor layer 110 is bulk-like and need not be epitaxial. In these latter embodiments the semiconductor layer 110 may itself act as the substrate. As used herein, the term “substrate” refers to a free-standing, self-supporting structure and is not to be construed as a thin film layer that is formed on a free-standing, self-supporting structure.

A series of n (n≧1) island regions 170 are located in the semiconductor layer 110 between the source contact 140 and drain contact 150. At least a portion of each island region 170 extends underneath or below the gate electrode 160. More specifically, if the gate electrode 160 extends in the lateral direction (e.g., the x-direction in FIGS. 1-3), then in some embodiments each island region 170 extends in a direction perpendicular to the lateral direction (e.g., the z-direction in FIGS. 1-3). In some embodiments, the gate region (including the gate electrode 160, dielectric layer 130 and possibly barrier layer 120) covers the entirety of island regions 170. In the embodiment shown in FIG. 2 the island regions 170 extend through the barrier layer 120 and may contact the dielectric layer 130.

The island regions 170 will have any suitable cross-section shape such as square, rectangular, hexagonal, circular and elliptical, for example. The width of each island region 170 in the lateral direction (e.g., along the x-direction in FIGS. 1-3) may vary, for instance, from 10 nm to the maximum width of the source and drain contacts 140 and 150. The island regions 170 may all have the same or different widths. The distance between each island region 170 may vary from 0 to 100 μm, for example. Likewise, the length of each island region 170 may vary from 10 nm to the full distance between the source and drain contacts 140 and 150. The island regions 170 may all have the same or different lengths. The depth of each “island region 170 may vary from 1 nm to 500 μm in some embodiments.

The semiconductor device 100 may be fabricated from many different material systems, including but not limited to Si-based systems and group III-V materials, in particular group III-nitride based material systems. Group-III nitrides include the semiconductor compounds formed between nitrogen and the elements in Group-III of the periodic table, usually aluminum (Al), gallium (Ga), and indium (In). This group also includes ternary and tertiary compounds such as AlGaN and AlInGaN. Some particular materials that may be suitable include, by way of example, Si, GaAs, Ga₂O₃, ZnO₂, AlN, SiC, AlN, InN, GaN and diamond-based power and RF devices.

As previously mentioned, the semiconductor layer 110 may be a bulk semiconductor layer or it may comprise one or more sublayers formed on a substrate. By way of illustration, in some embodiments semiconductor layer 110 may be composed of In_xAl_yGa_zN (0≦x≦1, 0≦y≦1, 0≦z≦1, x+y+z=1), SiC, In_xAl_yGa_zAs (0≦x≦1, 0≦y≦1, 0≦z≦1, x+y+z=1), diamond, Si and/or oxide semiconductors such as Ga₂O₃, ZnO₂, either by themselves or in combination with other materials and/or heterostructures.

Barrier layer 120, which may comprise two or more sublayers, may comprise in some embodiments one or more layers of In_xAl_yGa_zN (0≦x≦1, 0≦y≦1, 0≦z≦1, x+y+z=1), SiC, In_xAl_yGa_zAs (0≦x≦1, 0≦y≦1, 0≦z≦1, x+y+z=1), diamond, Si_xN_y, SiO₂, Ga₂O₃, ZnO₂ and/or etch-stop layers formed by a combination of these materials. Dielectric layer 130 in some embodiments may comprise Al₂O₃, Si_xO_y, Si_xN_y, Si_xO_yN_z, Teflon, HfO₂, or any other dielectric with a dielectric constant below 200.

The gate electrode 160 may include conductive material including, for instance, amorphous, poly-crystalline, or crystalline semiconductors, metals or conductive oxides or dielectrics or a combination of these materials.

The island regions 170 differs from the surrounding semiconductor layer 110 and the barrier layer 120 in any one or more ways. For example, the island regions may differ from semiconductor layer 110 and the barrier layer 120 by having different doping types, doping levels, resistivity or material compositions including crystalline, poly-crystalline, amorphous semiconductors or dielectric material or any combination of different doping types, doping levels, resistivity and material compositions. The island regions 170 may be formed by ion implantation or by etching into the semiconductor layer and re-deposition of materials or by any combination of these and other methods. In some embodiments the island regions 170 may contain voids, without solid phase materials. For instance, as will be shown below in connection with FIG. 4(b) the island regions 170 may each incorporate a portion of a trench that is lined with various layers that define the individual island regions 170.

FIGS. 4 a-4d show alternative embodiments of the invention along the lateral direction taken along lines A-A′ in FIG. 1. While in the embodiment of FIG. 2 the top of the island regions 170 and the barrier layer 120 are in the same plane, in some embodiments such as shown in FIGS. 4a and 4b they may be in different planes (i.e., different depths).

In the embodiment shown in FIG. 4(a), each island region 170 is formed at the bottom of a trench 172 located in the semiconductor layer 110. The trenches 172 may be lined or filled first with the dielectric layer 130 followed by the gate electrode 160. The barrier layer 120 may be located below the dielectric layer 130 between adjacent trenches 172 or between a trench and the source or drain contacts 140 and 150. FIG. 5 shows the embodiment of FIG. 4(a) taken along lines B-B′ in FIG. 1. The gate electrode 160 may or may not fill the trench 172.

In the embodiment shown in FIG. 4(b), each island region 170, which is shown within the rectangle defined by the dashed lines, contains two layers 175 each lining a sidewall of trench 172 formed in the semiconductor layer 110. The layers 175 are different from the surrounding semiconductor layer 110 and barrier layer 120 by having different doping types, doping levels, resistivity or material compositions including crystalline, poly-crystalline, amorphous semiconductors or dielectric material or any combination of the different doping types, doping levels, resistivity and material compositions.

In some embodiments such as shown in FIGS. 4(c) and 4(d), each of the island regions 170 includes multiple sub-layers 176 and 178, where the sub-layer 176 and sub-layer 178 are different from the surrounding semiconductor layer and barrier layer in any one or more ways by having, for example, different doping types, doping levels, resistivity or material compositions including crystalline, poly-crystalline, amorphous semiconductors or dielectric material or any combination of the different doping types, doping levels, resistivity and material compositions. Similar to FIG. 4(b), island regions 170 in FIGS. 4(c) and 4(d) are shown within the rectangles defined by the dashed lines.

The interface between the sub-layer 176 and sub-layer 178 is along the horizontal direction as shown in FIG. 4(c) or along the vertical direction as shown in FIG. 4(d). In some embodiments, the interface between the sub-layers of island regions 170 is at an angle different from 0 and 90 degrees. In some embodiments, each of the sub-layers 176 and 178 may include additional sub-layers.

In some embodiments, a portion of the barrier layer 120 in the gate region may be recessed and the dielectric layer 130 covers the recessed barrier layer 120 region. The gate electrode 160 disposed over the dielectric layer 130 may include conductive material including amorphous, poly-crystalline, or crystalline semiconductors, metals or conductive oxides or dielectrics or a combination of these material. In the embodiments described above the source and drain contacts 140 and 150 and the gate electrode 160 are all formed on the same side of the semiconductor layer (i.e., the top side as seen most easily in FIG. 3) to define a lateral device. In other embodiments, at least one of the drain or source contacts 140 and 150 is formed on the opposite side of the semiconductor layer 110 from the gate electrode 160 to define a vertical device.

FIGS. 6( a)-6(c) show cross-sectional views of other alternative embodiments of the invention taken along line A-A′ in FIG. 1. The island regions 170 in FIGS. 6(a)-6(c) are similar to those discussed above in connection with FIGS. 2, 4(c) and 4(d), respectively. The embodiments of FIGS. 6(a)-6(c), however, include an additional semiconductor layer 185 over or on semiconductor layer 110 and below barrier layer 120. The semiconductor layer 185 may or may not be located in whole or in part in the gate region shown in FIG. 1. Island regions 170 are located in the semiconductor layer 110 between the source contact 140 and drain contact 150 and are buried underneath the semiconductor layer 185.

The semiconductor layer 185, which is located over the island regions 170 and the semiconductor layer 110, may be formed by epitaxial growth or any other suitable method. The semiconductor layer 185 may be a single semiconductor layer or it may include two or more sub-layers. For example, in some embodiments the semiconductor layer 185 comprises In_xAl_yGa_zN (0≦x≦1, 0≦y≦1, 0≦z≦1, x+y+z=1), SiC, In_xAl_yGa_zAs (0≦x≦1, 0≦y≦1, 0≦z≦1, x+y+z=1), diamond, Si and/or oxide semiconductors such as Ga₂O₃, ZnO₂, either by themselves or in combination with other materials and/or heterostructures.

Due to the different compositional and/or structural differences (e.g., different doping types, doping densities, conductivities or material composition) between the island regions 170 and the surrounding layers in the various embodiments, the built-in potential or mechanical strain between the island regions 170 and the surrounding semiconductor layers shifts the Fermi-level of the semiconductor layers where the conduction channel is located. As a result, the threshold voltage of the transistor containing the island structure in the gate region is modulated. For example, if the semiconductor layer 110 is n-type, the island regions may be differ from the semiconductor layer 110 in being p-type, which will affect the Fermi-level and change the device threshold voltage. This structure can be applied to unipolar semiconductors to make normally-off/enhancement-mode transistors.

The semiconductor devices described herein may be fabricated using a wide variety of different fabrication techniques. For instance, low cost deposition techniques such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), and reactive or conventional sputtering methods may be employed. The island regions may be structured, for example, using a Si_xO_yN_z-based hard mask combined with dry/wet etching. As a further alternative, other growth methods, such as molecular beam epitaxy (MBE) or atomic layer epitaxy may be used. Yet additional techniques that may be employed include, without limitation, Flow Modulation Organometallic Vapor Phase Epitaxy (FM-OMVPE), Organometallic Vapor-Phase Epitaxy (OMVPE), Hydride Vapor-Phase Epitaxy (HYPE), Atomic Layer Deposition (ALD), and Physical Vapor Deposition (PVD). Standard metallization techniques, as known in the art of semiconductor fabrication, can be used to form the electrodes.

FIGS. 7( a)-7(d) shows a simplified example of the processing steps that may be employed to fabricate the embodiment of the invention shown in FIGS. 2-3. First, in step 310 of FIG. 7(a) barrier layer 120 is deposited on semiconductor layer 110, which, as previously mentioned, may be an epitaxial layer formed on a substrate (not shown) or it may itself serve as the substrate. Next, in step 320 of FIG. 7(b) an implantation step is performed using suitable masks and the like to form the island regions 170 that extend through the barrier layer 120. Of course, island regions 170 may be formed by alternative techniques as well. For instance, trenches may be formed in the semiconductor 110 using an etching process, followed by deposition into the trenches of the material(s) that define the island regions 170. Dielectric layer 130 is then formed in step 330 of FIG. 7(c) over the barrier layer 120 and the exposed surface of the island regions 170, followed by deposition of the gate electrode 160 in step 340 of FIG. 7(d). Finally, although not shown, source and drain regions and optional passivation layers may be formed in a conventional manner to complete the fabrication of the semiconductor device 100.

FIGS. 8( a)-8(e) shows a simplified example of the processing steps that may be employed to fabricate the embodiment of the invention shown in FIG. 4(a) in which the island regions 170 are formed at the bottom of trenches 172. First, in step 410 of FIG. 8(a) barrier layer 120 is deposited on semiconductor layer 110, which, as previously mentioned, may be an epitaxial layer formed on a substrate (not shown) or it may itself serve as the substrate. Next, in step 420 of FIG. 8(b) trenches 172 are formed through the barrier layer 120 and into the semiconductor layer 110 by etching methods using suitable masks and the like. An implantation or deposition step is then performed to deposit island regions 170 through the bottom of the trenches 172 in step 430 of FIG. 8(c). Dielectric layer 130 is then formed in step 440 of FIG. 8(d) over the barrier layer 120 and in the trenches 172 over the island regions 170, followed by deposition of the gate electrode 160 in step 450 of FIG. 8(e). Finally, although not shown, source and drain regions and optional passivation layers may be formed in a conventional manner to complete the fabrication of the semiconductor device 100.

As previously mentioned, the structures described herein may be employed in a number of different semiconductor devices. For instance, in addition to transistors, it may be incorporated into diodes. Similar to the transistor structures shown above, the anode (or in some cases the cathode) of such a diode will cover at least a portion of the island regions. The island regions themselves may be as described above. The anode will make electrical contact with the semiconductor layer underneath it. The different compositional and/or structural differences between the island regions and the surrounding semiconductor layers changes the diode junction capacitance and reverse leakage current.

The above description of illustrated examples of the present invention is not intended to be exhaustive or limited to the precise forms disclosed. While specific embodiments of, and examples for, the invention are described herein for illustrative purposes, various equivalent modifications are possible without departing from the broader spirit and scope of the present invention.

These modifications can be made to examples of the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific embodiments disclosed in the specification and the claims. Rather, the scope is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation. The present specification and figures are accordingly to be regarded as illustrative rather than restrictive.

Claims

1. A transistor, comprising: a source region;a drain region;a semiconductor region located between the source region and the drain region;at least one island region located in the semiconductor region, each of the island regions differing from the semiconductor region in one or more characteristics selected from the group including resistivity, doping type, doping concentration, strain and material composition; anda gate region located between the source region and the drain region covering at least a portion of the island regions.

2. The transistor of claim 1, wherein the semiconductor region comprises InxAlyGazN (0≦x≦1, 0≦y≦1, 0≦z≦1, x+y+z=1), SiC, InxAlyGazAs (0≦x≦1, 0≦y≦1, 0≦z≦1, x+y+z=1), diamond, Si and/or oxide semiconductors.

3. The transistor of claim 2 wherein the semiconductor region further comprises at least one additional material and/or a heterostructure.

4. The transistor of claim 1, further comprising a second semiconductor layer located on the semiconductor region and covering a least a portion of the island regions.

5. The transistor of claim 4, wherein the second semiconductor layer comprises InxAlyGazN (0≦x≦1, 0≦y≦1, 0≦z≦1, x+y+z=1), SiC, InxAlyGazAs (0≦x≦1, 0≦y≦1, 0≦z≦1, x+y+z=1), diamond, Si and/or oxide semiconductors.

6. The transistor of claim 1, wherein the semiconductor region includes a barrier layer located at a surface of the semiconductor region.

7. The transistor of claim 4, wherein the second semiconductor layer includes a barrier layer located at a surface of the second semiconductor layer.

8. The transistor of claim 6, wherein the barrier layer comprises at least one layer of InxAlyGazN (0≦x≦1, 0≦y≦1, 0≦z≦1, x+y+z=1), SiC, InxAlyGazAs (0≦x≦1, 0≦y≦1, 0≦z≦1, x+y+z=1), diamond, SixNy, SiO2, Ga2O3, ZnO2 and/or etch-stop layers formed by a combination of these materials.

9. The transistor of claim 6, wherein the barrier layer has a recessed region under the gate region. The method of claim 5 wherein the second semiconductor layer further comprises at least one additional material and/or a heterostructure.

10. The transistor of claim 1, wherein a surface of the semiconductor region extends in a first plane and the island regions comprise a plurality of sub-layers, wherein an interface between each of the sub-layers extends in the first plane or a second plane orthogonal to the first plane, or at an angle with respect to the first plane that is different from 0 and 90 degrees.

11. The transistor of claim 1, wherein the gate region comprises a gate electrode located over the semiconductor region.

12. The transistor of claim 11, wherein the gate electrode comprises one or more conductive materials selected from the group including metals, amorphous, polycrystalline, crystalline semiconductors or conductive oxides, and dielectric materials.

13. The transistor of claim 1, wherein the gate region comprises a gate dielectric layer located between the gate electrode and a surface of the semiconductor region.

14. The transistor of claim 13, wherein the gate dielectric layer comprises Al2O3, SixOy, SixNy, SixOyNz, Teflon, HfO2, or any other dielectric with a dielectric constant below 200.

15. A diode, comprising: a cathode region;a semiconductor region;at least one island region located in the semiconductor region, each of the island regions differing from the semiconductor region in one or more characteristics selected from the group including resistivity, doping type, doping concentration, strain and material composition; andan anode region covering at least a portion of the island regions.

16. The diode of claim 15, wherein the semiconductor region comprises of InxAlyGazN (0≦x≦1, 0≦y≦1, 0≦z≦1, x+y+z=1), SiC, InxAlyGazAs (0≦x≦1, 0≦y≦1, 0≦z≦1, x+y+z=1), diamond, Si and/or oxide semiconductors.

17. The diode of claim 16 wherein the semiconductor region further comprises at least one additional material and/or heterostructure.

18. The diode of claim 15, further comprising a second semiconductor layer located on the semiconductor region and covering at least a portion of the island regions.

19. The diode of claim 18, wherein the second semiconductor layer comprises InxAlyGazN (0≦x≦1, 0≦y≦1, 0≦z≦1, x+y+z=1), SiC, InxAlyGazAs (0≦x≦1, 0≦y≦1, 0≦z≦1, x+y+z=1), diamond, Si and/or oxide semiconductors.

20. The diode of claim 19 wherein the second semiconductor layer comprises at least one additional material and/or heterostructure.

21. The diode of claim 15, wherein the semiconductor region includes a barrier layer located at a surface of the semiconductor region.

22. The diode of claim 18, wherein the second semiconductor layer includes a barrier layer located at a surface of the second semiconductor layer.

23. The diode of claim 21, wherein the barrier layer comprises at least one layer of InxAlyGazN (0≦x≦1, 0≦y≦1, 0≦z≦1, x+y+z=1), SiC, InxAlyGazAs (0≦x≦1, 0≦y≦1, 0≦z≦1, x+y+z=1), diamond, SixNy, SiO2, Ga2O3, ZnO2 and/or etch-stop layers formed by a combination of these materials.

24. The diode of claim 21, wherein the barrier layer has a recessed region under the anode region.

25. The diode of claim 15 wherein a surface of the semiconductor region extends in a first plane and the island regions comprise a plurality of sub-layers, wherein an interface between each of the sub-layers extends in the first plane or a second plane orthogonal to the first plane, or at an angle with respect to the first plane that is different from 0 and 90 degrees.

26. The diode of claim 15, wherein the anode region includes an anode electrode located over the semiconductor region.

27. The diode of claim 26, wherein the anode electrode includes one or more conductive materials selected from the group including metals, amorphous, polycrystalline, crystalline semiconductors or conductive oxides and dielectric materials.

28. The diode of claim 26, wherein the anode electrode and the semiconductor region are in electrical contact.

29. The diode of claim 26, wherein the anode region includes a dielectric layer located between the anode electrode and a surface of the semiconductor region.

30. The diode of claim 29, wherein the dielectric layer comprises Al2O3, SixOy, SixNy, SixOyNz, Teflon, HfO2, or any other dielectric with a dielectric constant below 200.

31. A semiconductor structure, comprising: a semiconductor region;at least one island region located in the semiconductor region, each of the island regions differing from the semiconductor region in one or more characteristics selected from the group including resistivity, doping type, doping concentration, strain and material composition; anda conductive electrode covering a least a portion of the island regions.

32. The semiconductor structure of claim 31 wherein the semiconductor region comprises InxAlyGazN (0≦x≦1, 0≦y≦1, 0≦z≦1, x+y+z=1), SiC, InxAlyGazAs (0≦x≦1, 0≦y≦1, 0≦z≦1, x+y+z=1), diamond, Si and/or oxide semiconductors.

33. The semiconductor structure of claim 32 wherein the semiconductor region further includes at least one additional material and/or heterostructure.

34. The semiconductor structure of claim 31, further comprising a second semiconductor layer located on the semiconductor region and covering at least a portion of the island regions.

35. The semiconductor structure of claim 34, wherein the second semiconductor layer comprises InxAlyGazN (0≦x≦1, 0≦y≦1, 0≦z≦1, x+y+z=1), SiC, InxAlyGazAs (0≦x≦1, 0≦y≦1, 0≦z≦1, x+y+z=1), diamond, Si and/or oxide semiconductors.

36. The semiconductor structure of claim 31 wherein the semiconductor region includes a barrier layer located at the surface of the semiconductor region.

37. The semiconductor structure of claim 34 wherein the second semiconductor layer includes a barrier layer located at the surface of the second semiconductor layer.

38. The semiconductor structure of claim 36, wherein the barrier layer comprises one or more layers of InxAlyGazN (0≦x≦1, 0≦y≦1, 0≦z≦1, x+y+z=1), SiC, InxAlyGazAs (0≦x≦1, 0≦y≦1, 0≦z≦1, x+y+z=1), diamond, SixNy, SiO2, Ga2O3, ZnO2 and/or etch-stop layers formed by a combination of these materials.

39. The semiconductor structure of claim 36, wherein the barrier layer has a recessed region under the conductive electrode.

40. The semiconductor structure of claim 31 wherein a surface of the semiconductor region extends in a first plane and the island regions comprise a plurality of sub-layers, wherein an interface between each of the sub-layers extends in the first plane or a second plane orthogonal to the first plane, or at an angle with respect to the first plane that is different from 0 and 90 degrees.

41. The semiconductor structure of claim 31, wherein the conductive electrode comprises one more conductive materials selected from the group including metals, amorphous, polycrystalline, crystalline semiconductors or conductive oxides and dielectric materials.

42. The semiconductor structure of claim 31, further comprising one or more dielectric layers located between the conductive electrode and the surface of the semiconductor region.

43. The semiconductor structure of claim 42, wherein the dielectric layer comprises Al2O3, SixOy, SixNy, SixOyNz, Teflon, HfO2, or any other dielectric with a dielectric constant below 200.

44. A method of forming a semiconductor structure, the method comprising: forming at least one island region in a semiconductor region, each of the island regions differing from the semiconductor region in one or more characteristics selected from the group including resistivity, doping type, doping concentration, strain and material composition; and forming a conductive electrode covering at least a portion of the island regions.

45. The method of claim 44, wherein the semiconductor region comprises InxAlyGazN (0≦x≦1, 0≦y≦1, 0≦z≦1, x+y+z=1), SiC, InxAlyGazAs (0≦x≦1, 0≦y≦1, 0≦z≦1, x+y+z=1), diamond, Si and/or oxide semiconductors.

46. The method of claim 45 wherein the semiconductor region includes at least one additional material and/or heterostructures.

47. The method of claim 44, further comprising forming a second semiconductor layer on the semiconductor region.

48. The method of claim 47, wherein the second semiconductor layer is formed by epitaxial regrowth, sputtering or wafer bonding.

49. The method of claim 47, wherein the second semiconductor layer comprises InxAlyGazN (0≦x≦1, 0≦y≦1, 0≦z≦1, x+y+z=1), SiC, InxAlyGazAs (0≦x≦1, 0≦y≦1, 0≦z≦1, x+y+z=1), diamond, Si and/or oxide semiconductors.

50. The method of claim 44, wherein forming the island regions comprises forming the island regions by ion-implantation, diffusion to change resistivity, doping type, doping concentration, and/or mechanical strain in the island regions.

51. The method of claim 44, wherein forming the island regions comprises forming the island regions by etching and re-deposition of crystalline, poly-crystalline, amorphous semiconductors, dielectric materials or voids containing no solid-phase material.

52. The method of claim 44, wherein a surface of the semiconductor region extends in a first plane and the island regions comprise a plurality of sub-layers, wherein an interface between each of the sub-layers extends in the first plane or a second plane orthogonal to the first plane, or at an angle with respect to the first plane that is different from 0 and 90 degrees.

53. The method of claim 44, wherein forming the conductive electrode comprises the deposition one or more conductive materials selected from the group including metals, amorphous, polycrystalline, crystalline semiconductors and conductive oxides.

54. The method of claim 44, further comprising forming a dielectric layer between the conductive electrode and the surface of the semiconductor region.

55. The method of claim 44 wherein the semiconductor region includes a barrier layer located at the surface of the semiconductor region.

56. A method of forming a transistor having a tailored threshold voltage, the method comprising: forming at least one island region in a semiconductor region, wherein forming the at least one island region includes selecting at least one structural and/or compositional characteristic for each of the island regions that differs from the at least one structural and/or compositional characteristic of the semiconductor region so that the transistor has the tailored threshold voltage, wherein forming the at least one island region includes forming the at least one island region with the selected structural and/or compositional characteristic; andforming a conductive electrode covering at least a portion of the island regions.

57. The method of claim 56 wherein the at last one structural and/or compositional characteristic is selected from the group including resistivity, doping type, doping concentration, strain and material composition.