Embodiments of the present invention relate generally to the field of circuit interconnection and, in particular, aspects of the present invention relate to chip package interconnection to adjacent circuit boards.
Semiconductor chips such as processor chips are housed in chip packages, which are subsequently attached to circuit boards in the manufacture of a number of electronic devices. These devices, include personal computers, handheld computers, mobile telephones, MP3 players and other numerous information processing devices. One common configuration of input/output connections between chips, substrates, packages, and adjacent circuit boards, etc. includes grid array connection structures. In one common grid array connection structure, solder balls such as in ball grid array packages are used to connect between grids.
There are a number of design concerns that are taken into account when forming grid arrays. High mechanical strength and reliability of the grid array connections are desirable. In a solder structure grid interconnection example, two connection surfaces with one or more solder balls in between are heated to reflow the solder and form an electrical connection. The heating process causes adjacent structures such as chips, substrates, chip packages and circuit boards to expand and contract at different rates due to differences in the coefficient of thermal expansion (CTE) in each component. The differences in CTE may cause unwanted stresses and strains in resulting products. In addition, further stress is induced by product use conditions such as powering up and down. These product use conditions impose cyclic thermal stresses on components as well.
In the following detailed description of the invention reference is made to the accompanying drawings which form a part hereof, and in which are shown, by way of illustration, specific embodiments in which the invention may be practiced. In the drawings, like numerals describe substantially similar components throughout the several views. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized, and structural, mechanical, electrical, chemical changes, materials choices, etc. may be made, without departing from the scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the invention should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.
One method of providing increased mechanical strength to an interconnecting region of an electronic assembly includes introduction of an epoxy underfill layer after solder balls have already been connected between two component surfaces. In one underfill process, liquid epoxy or other curable liquid is flowed into a gap between two component surfaces and around the reflowed solder connections using capillary forces to draw the liquid into the gap. The liquid epoxy is then cured to form a more robust connection between the two component surfaces and protect the solder connections from failures such as stress cracking. Such capillary flow methods can be used between chips and substrates, or between chip packages and adjacent circuit boards, between two circuit boards, etc. One drawback of using capillary flow methods includes increased manufacturing time to both introduce the epoxy, and cure the epoxy.
In one embodiment, the adhesive can be activated through an external step such as heating a thermally activated adhesive, or applying force to a pressure sensitive adhesive. In one embodiment, the backing strip 114 includes a peel off backing to protect the adhesive 112 until assembly.
As discussed above, in one embodiment, an intermediate layer 123 is included within the holes 122, although the invention is not so limited. An advantage of the intermediate layer 123 is that in selected embodiments, it provides compatibility between the compliant layer 110 material and the conductive through thickness plug 130 material. For example, in one embodiment, the intermediate layer 123 includes copper, within a polymer compliant layer 110. A through thickness plug 130 of solder can be more easily applied into the holes 122 due to the presence of copper as an intermediate layer 123. In one embodiment, liquid solder is drawn into the holes 122 due to interfacial energy driving forces between copper and solder. In other embodiments, using for example a conductive epoxy to form the through thickness plug 130, an intermediate layer 123 may not be necessary.
In one embodiment, the top portion 126 and the bottom portion 128 are flared out to a larger surface area as discussed above. An advantage of this configuration includes easier subsequent attachment to device conductive structures such as metal input/output pads, solder bumps, etc.
As shown in
In one embodiment, the compliant layer 210 includes gradiated physical properties. A thickness 214 of the compliant layer is shown in
Although multiple layers are shown in
In one method of assembly, a first adhesive 334 is placed in contact with a component surface 311. In one embodiment, a second adhesive 336 is placed in contact with a circuit board surface such as surface 321. In one embodiment, the component surfaces such as surface 311 and 321 include additional structures such as solder masks 350.
One advantage of adhesive layer 334 includes a stress distributing bond at the interface between a compliant layer 332 and the chip package surface 311. Another advantage of using an adhesive layer includes ease of assembly. Use of an adhesive layer such as layer 336 at other interfaces provides similar advantages in selected embodiments. In one embodiment the compliant layer 332 includes a layer with gradiated physical properties similar to embodiments described above.
In one embodiment, a physical property adjacent to a first surface 331 of the compliant layer 332 is matched to a physical property of an adjacent component surface 321. Likewise, in one embodiment, a physical property adjacent to a second surface 333 of the compliant layer 332 is matched to a physical property of an adjacent component surface 311. In one embodiment, a coefficient of thermal expansion is substantially matched between the first surface 331 and the component surface 321 and between the second surface 333 and the component surface 311. An advantage of a gradiated compliant layer 332 and matching physical properties includes accommodating damaging strains in assemblies such as
In one embodiment, after assembly as shown in
An example of an electronic device using semiconductor chips and underfill layers is included to show an example of a higher level device application for the present invention.
An electronic assembly 510 is coupled to system bus 502. The electronic assembly 510 can include any circuit or combination of circuits. In one embodiment, the electronic assembly 510 includes a processor 512 which can be of any type. As used herein, “processor” means any type of computational circuit, such as but not limited to a microprocessor, a microcontroller, a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, a graphics processor, a digital signal processor (DSP), or any other type of processor or processing circuit.
Other types of circuits that can be included in electronic assembly 510 are a custom circuit, an application-specific integrated circuit (ASIC), or the like, such as, for example, one or more circuits (such as a communications circuit 514) for use in wireless devices like mobile telephones, pagers, personal data assistants, portable computers, two-way radios, and similar electronic systems. The IC can perform any other type of function.
The electronic device 700 can also include an external memory 520, which in turn can include one or more memory elements suitable to the particular application, such as a main memory 522 in the form of random access memory (RAM), one or more hard drives 524, and/or one or more drives that handle removable media 526 such as compact disks (CD), digital video disk (DVD), and the like.
The electronic device 500 can also include a display device 516, one or more speakers 518, and a keyboard and/or controller 530, which can include a mouse, trackball, game controller, voice-recognition device, or any other device that permits a system user to input information into and receive information from the electronic device 500.
An underfill device and method have been shown. Advantages of devices and methods shown include dissipation of stresses at an interface between components such as a chip package and an adjacent circuit board. Another advantage includes faster manufacturing time and ease of manufacture using underfill devices and methods shown. An underfill assembly can be pre made with conductive structures included within the underfill assembly. Steps such as flowing epoxy and curing can be eliminated or performed concurrently with other manufacturing steps.
Although selected advantages are detailed above, the list is not intended to be exhaustive. Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement which is calculated to achieve the same purpose may be substituted for the specific embodiment shown. This application is intended to cover any adaptations or variations of embodiments described above. It is to be understood that the above description is intended to be illustrative, and not restrictive. Combinations of the above embodiments, and other embodiments will be apparent to those of skill in the art upon reviewing the above description. The scope of the invention includes any other applications in which the above structures and fabrication methods are used. The scope of the invention should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.
This application is a divisional of U.S. application Ser. No. 11/169,518, filed Jun. 29, 2005, which is incorporated herein by reference in its entirety.
Number | Name | Date | Kind |
---|---|---|---|
4581680 | Garner | Apr 1986 | A |
5086558 | Grube et al. | Feb 1992 | A |
5352926 | Andrews | Oct 1994 | A |
5796163 | Glenn | Aug 1998 | A |
5914614 | Beaman | Jun 1999 | A |
6050832 | Lee et al. | Apr 2000 | A |
6108210 | Chung | Aug 2000 | A |
6190940 | DeFelice | Feb 2001 | B1 |
6258627 | Benenati | Jul 2001 | B1 |
6319829 | Pasco | Nov 2001 | B1 |
6414248 | Sundstrom | Jul 2002 | B1 |
6433565 | Desai et al. | Aug 2002 | B1 |
6670699 | Mikubo et al. | Dec 2003 | B2 |
6764748 | Farquhar et al. | Jul 2004 | B1 |
6783828 | Fujimaru et al. | Aug 2004 | B2 |
6933617 | Pierce | Aug 2005 | B2 |
6969914 | Fuller | Nov 2005 | B2 |
8399291 | Brusso et al. | Mar 2013 | B2 |
20020084108 | Amir | Jul 2002 | A1 |
20030094666 | Clayton et al. | May 2003 | A1 |
20030127737 | Takahashi | Jul 2003 | A1 |
20030147227 | Egitto | Aug 2003 | A1 |
20030206680 | Bakir | Nov 2003 | A1 |
20030230799 | Yee et al. | Dec 2003 | A1 |
20040005770 | Farnworth | Jan 2004 | A1 |
20040130343 | Beaman | Jul 2004 | A1 |
20040214370 | Quinones | Oct 2004 | A1 |
20050023033 | Saiki et al. | Feb 2005 | A1 |
20050028361 | Yin et al. | Feb 2005 | A1 |
20050042838 | Garyainov et al. | Feb 2005 | A1 |
20050046026 | Devanie | Mar 2005 | A1 |
20050221534 | Suh et al. | Oct 2005 | A1 |
20050224946 | Dutta | Oct 2005 | A1 |
20060022328 | Lee | Feb 2006 | A1 |
20060038303 | Sterrett et al. | Feb 2006 | A1 |
20060088715 | Husemann et al. | Apr 2006 | A1 |
20060220175 | Guzek et al. | Oct 2006 | A1 |
20060223226 | Guzek et al. | Oct 2006 | A1 |
20060226538 | Kawata | Oct 2006 | A1 |
20070004085 | Brusso et al. | Jan 2007 | A1 |
20070090506 | Sundstrom | Apr 2007 | A1 |
Entry |
---|
“U.S. Appl. No. 11/169,518, Response filed Sep. 4, 2007 to Non-Final Office Action mailed Jun. 4, 2007”, (Sep. 4, 2007), 6 pgs. |
“U.S. Appl. No. 11/169,518 , Response filed Aug. 23, 2012 to Non Final Office Action mailed May 23, 2012”, 5 pgs. |
“U.S. Appl. No. 11/169,518, Decision on Appeal mailed Mar. 1, 2012”, 6 pgs. |
“U.S. Appl. No. 11/169,518, Non Final Office Action mailed 05-23-2”, 12 pgs. |
“U.S. Appl. No. 11/169,518, Notice of Allowance mailed Nov. 15, 2012”, 10 pgs. |
“U.S. Appl. No. 11/169,518, Response filed Nov. 26, 2007 to Final Office Action mailed Sep. 25, 2007”, (Nov. 26, 2007), 6 pages. |
“Final-Office Action Mailed Sep. 25, 2007 in U.S. Appl. No. 11/169,518”, FOAR, 12 pages. |
Number | Date | Country | |
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20130208411 A1 | Aug 2013 | US |
Number | Date | Country | |
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Parent | 11169518 | Jun 2005 | US |
Child | 13846218 | US |