Patent Application
20250226352
The present disclosure relates generally to wire bonding and to forming v-bonds with a stacked configuration.
Wire bonding is a method of making interconnections between an integrated circuit (IC) or other semiconductor device and its packaging during semiconductor device fabrication. Wire bonding can also be used to connect an IC to other electronics or to connect from one circuit substrate, such as a printed circuit board (PCB), to another circuit substrate. Ball bonding and wedge bonding are two types of wire bonding processes. Ball bonding may be performed by a ball bonding tool. Ball bonding may include, at a first end of a wire, a ball formation followed by a ball bond formation. Ball bonding may include, at a second end of the wire, a tail bond formation, which may include forming a stitch bond formation or a wedge bond formation to a ball by applying lateral ultrasonic vibration, downward pressure, and heat. Wedge bonding is another a type of wire bonding that relies on an application of lateral ultrasonic vibration and downward force to form conductive bonds (e.g., wedge bond formations) on conductive bonding surfaces located at both ends of a wire.
In some implementations, a method of forming a wire bond assembly includes wire bonding a first end of a first bond wire to a first conductive bonding surface arranged on a first substrate to form a first conductive bond formation; wire bonding a second end of the first bond wire to a second conductive bonding surface arranged on a second substrate to form a second conductive bond formation; forming a conductive structure on top of the first conductive bond formation; wire bonding a first end of a second bond wire to a top of the conductive structure to form a third conductive bond formation; and wire bonding a second end of the second bond wire to the second conductive bonding surface to form a fourth conductive bond formation, wherein the fourth conductive bond formation is laterally separated from the second conductive bond formation on the second conductive bonding surface.
In some implementations, a method of forming a wire bond assembly includes wire bonding a first end of a first bond wire to a first conductive bonding surface arranged on a first substrate to form a first conductive bond formation; wire bonding a second end of the first bond wire to a second conductive bonding surface arranged on a second substrate to form a second conductive bond formation; forming a first conductive structure on top of the first conductive bond formation; forming a second conductive structure on top of the second conductive bond formation; wire bonding a first end of a second bond wire to a top of the first conductive structure to form a third conductive bond formation; and wire bonding a second end of the second bond wire to a top of the second conductive structure to form a fourth conductive bond formation.
In some implementations, a wire bond assembly includes a first substrate comprising a first conductive bonding surface; a second substrate comprising a second conductive bonding surface; a first conductive bump arranged on the first conductive bonding surface; a first conductive ball arranged on the second conductive bonding surface, wherein the first conductive ball is bonded to a first end of a first bond wire; a second conductive ball arranged on the second conductive bonding surface, wherein the second conductive ball is bonded to a first end of a second bond wire, and wherein the second conductive ball is laterally separated from the first conductive ball on the second conductive bonding surface; and a second conductive bump, wherein a second end of the first bond wire is wire bonded to a top of the first conductive bump to form a first conductive bond formation, wherein the second conductive bump is arranged on the first conductive bond formation, and wherein a second end of the second bond wire is wire bonded to a top of the second conductive bump to form a second conductive bond formation.
The following detailed description of example implementations refers to the accompanying drawings. The same reference numbers in different drawings may identify the same or similar elements.
Wire bonds should be made as short as possible to reduce wire bonding length and related parasitic inductance effects. When multiple wires are employed in a parallel configuration, larger diameter wire or ribbon bonds that have a wider cross section may be used to reduce inductance. However, a wider bond pad is needed to accommodate two wire bonds, a larger diameter wire, or a wider ribbon. For a radio frequency (RF) chip, it may be impractical to provide an RF bond pad that can accommodate two wires because of a lack of real estate or die area on the RF chip needed to accommodate wider bond pads. In addition, a wider bond pad on an RF receiver chip may increase parasitics (e.g., parasitic inductance), which may reduce a bandwidth of the RF receiver chip. Other types of chips or circuit substrates may face similar issues with smaller bond pads or other types of conductive bonding surfaces that cannot accommodate two parallel bond wires and/or wider bond wires that may be used to reduce parasitic inductance.
Some implementations described herein are directed to a method of implementing and sequencing wire bond interconnects between substrate structures with an objective of minimizing a parasitic inductive effect of the wire bond interconnects and minimizing capacitive effects of conductive bonding surfaces, such as bond pads. In RF receiver applications, improved optical receiver performance may be realized by increasing a bandwidth of an optical receiver by reducing parasitic inductance related to the wire bond interconnects.
The method may include using a pair of wire bond interconnects (e.g., bond wires) that start on a single conductive bonding surface and terminate in a V-configuration at a same termination point on a single conductive bonding surface. In other words, the pair of wire bond interconnects are vertically stacked (e.g., vertically bonded) on a conductive bonding surface of a first substrate structure (e.g., a first chip or a first circuit substrate), and are laterally bonded on a conductive bonding surface of a second substrate structure (e.g., a second chip or a second circuit substrate) to form the V-configuration. The pair of wire bond interconnects are arranged in a “V” to form an electrically parallel connection. As a result of arranging the two wire bond interconnects in the V-configuration, a lower inductance between two conductive bonding surfaces can be achieved. For example, V-bonds may provide lower inductance compared to 25 μm bonds. The lower inductance may be realized due to the two wire bond interconnects forming the electrically parallel connection. For example, an inductance of a V-bond wire assembly may be approximately 70% compared to a single wire of a same diameter. Thus, two wire bond interconnects arranged in the V-bond configuration may reduce parasitic inductance effects. In addition, vertically stacking the ends of the two wire bond interconnects on a same conductive bonding surface may enable the electrically parallel connection to be realized on smaller conductive bonding surfaces.
Using two wire bond interconnects with an electrically-equivalent parallel connection that are arranged in the V-bond configuration may be beneficial for connecting two substrate structures when using shorter wires, two side-by-side parallel wires, or larger wire sizes is not possible. Moreover, the V-bond configuration may increase an RF bandwidth of the connection. For example, a bonding technique for forming the V-bond configuration may be used to reduce a wirebond-induced peaking for optical receiver interconnects. For optical receivers, the reduction in wirebond-induced peaking may result in a more favorable/flat frequency response with enhanced bandwidth. However, the V-bond bonding technique is not limited to optical receivers and may be used in any application.
Some implementations described herein may be performed using a ball bonder tool, a wedge bonder tool, or a combination of a ball bonder tool and a wedge bonder tool.
The first processing stage 100A may include forming a first conductive bump 110 on top of the first conductive bonding surface 104.
The fourth processing stage 100D may also include wire bonding a second end 130 of the second bond wire 126 to the second conductive bonding surface 108 to form a fourth conductive bond formation 132, such as a conductive ball (i.e., a ball bond formation). In some implementations, the fourth conductive bond formation 132 may be formed first as a first attachment such that the second end 130 of the second bond wire 126 is attached first, and then the third conductive bond formation 128 is formed as a second attachment after the fourth conductive bond formation 132 is formed such that the first end 124 of the second bond wire 126 is attached second.
In addition, the fourth conductive bond formation 132 may be laterally separated from the second conductive bond formation 120 on the second conductive bonding surface 108. For example, the second conductive bond formation 120 and the fourth conductive bond formation 132 may be formed directly on the second conductive bonding surface 108, and may be separated from each other in a lateral dimension. Thus, the first bond wire 114 and the second bond wire 126 may be coupled to the first conductive bonding surface 104 and the second conductive bonding surface 108 in a V-configuration to form an electrically parallel connection between the first conductive bonding surface 104 and the second conductive bonding surface 108.
The first conductive bond formation 116 may be a first conductive wedge, the second conductive bond formation 120 may be a first conductive ball, the third conductive bond formation 128 may be a second conductive wedge, and the fourth conductive bond formation 132 may be a second conductive ball. Moreover, the first conductive bump 110 may be formed directly on the first conductive bonding surface 104, the first conductive bond formation 116 may be formed directly on the first conductive bump 110, the conductive structure 122 (e.g., the second conductive bump) may be formed directly on the first conductive bond formation 116, and the third conductive bond formation 128 may be formed directly on the conductive structure 122.
As indicated above,
The first processing stage 200A may include forming a first conductive bump 210 on top of the first conductive bonding surface 104. The first processing stage 200A may also include forming a second conductive bump 212 and a third conductive bump 214 on top of the second conductive bonding surface 108. The second conductive bump 212 and the third conductive bump 214 may be laterally separated from each other on the second conductive bonding surface 108.
As indicated above,
The first processing stage 300A may include forming a first conductive bump 310 on top of the first conductive bonding surface 104.
As indicated above,
The first processing stage 400A may include wire bonding a first end of a first bond wire 402 to the first conductive bonding surface 104 to form a first conductive bond formation 404 (e.g. a conductive wedge). Thus, the first end of a first bond wire 402 may be bonded directly to the first conductive bonding surface 104. The first processing stage 400A may also include wire bonding a second end of the first bond wire 402 to the second conductive bonding surface 108 to form a second conductive bond formation 406 (e.g., a conductive wedge). Thus, the second end of the first bond wire 402 may be bonded directly to the second conductive bonding surface 108.
As indicated above,
The first processing stage 500A may include forming a first conductive bump 510 on top of the first conductive bonding surface 104.
The fourth processing stage 500D may also include wire bonding a second end of the second bond wire 520 to the second conductive bump 518 to form a fourth conductive bond formation 524, such as a conductive wedge (i.e., a wedge bond formation). Thus, the first bond wire 512 and the second bond wire 520 may be coupled to the first conductive bonding surface 104 and the second conductive bonding surface 108 in a V-configuration to form an electrically parallel connection between the first conductive bonding surface 104 and the second conductive bonding surface 108.
As indicated above,
The first processing stage 600A may include wire bonding a first end of a first bond wire 610 to the first conductive bonding surface 104 to form a first conductive bond formation 612 (e.g. a conductive wedge). Thus, the first end of a first bond wire 610 may be bonded directly to the first conductive bonding surface 104. The first processing stage 600A may also include wire bonding a second end of the first bond wire 610 to the second conductive bonding surface 108 to form a second conductive bond formation 614 (e.g., a conductive ball). Thus, the second end of the first bond wire 610 may be bonded directly to the second conductive bonding surface 108. In some implementations, the second conductive bond formation 614 may be formed first as a first attachment such that the second end of the first bond wire 610 is attached first, and then the first conductive bond formation 612 is formed as a second attachment after the second conductive bond formation 614 is formed such that the first end of the first bond wire 610 is attached second.
The fourth conductive bond formation 622 is laterally separated from the second conductive bond formation 614 on the second conductive bonding surface 108. Thus, the first bond wire 610 and the second bond wire 618 may be coupled to the first conductive bonding surface 104 and the second conductive bonding surface 108 in a V-configuration to form an electrically parallel connection between the first conductive bonding surface 104 and the second conductive bonding surface 108.
As indicated above,
The first processing stage 700A may include forming a first conductive bump 710 on top of the first conductive bonding surface 104.
As indicated above,
The first processing stage 800A may include forming a first conductive bump 810 on top of the first conductive bonding surface 104. The first processing stage 800A may also include forming a second conductive bump 812 on top of the second conductive bonding surface 108.
As a result, the first conductive bump 810, the first conductive bond formation 816, the third conductive bump 820, and the third conductive bond formation 826 may be arranged in a vertical stack on the first conductive bonding surface 104. Additionally, the second conductive bump 812, the second conductive bond formation 818, the fourth conductive bump 822, and the fourth conductive bond formation 828 may be arranged in a vertical stack on the second conductive bonding surface 108. Thus, the first bond wire 814 and the second bond wire 824 may be coupled to the first conductive bonding surface 104 and the second conductive bonding surface 108 in parallel to form an electrically parallel connection between the first conductive bonding surface 104 and the second conductive bonding surface 108.
As indicated above,
The first processing stage 900A may include wire bonding a first end of a first bond wire 910 to the first conductive bonding surface 104 to form a first conductive bond formation 912 (e.g. a conductive wedge). The second processing stage 900B may also include wire bonding a second end of the first bond wire 910 to the second conductive bonding surface 108 to form a second conductive bond formation 914 (e.g., a conductive wedge).
As a result, the first conductive bond formation 912, the first conductive bump 916, and the third conductive bond formation 922 may be arranged in a vertical stack on the first conductive bonding surface 104. Additionally, the second conductive bond formation 914, the second conductive bump 918, and the fourth conductive bond formation 924 may be arranged in a vertical stack on the second conductive bonding surface 108. Thus, the first bond wire 910 and the second bond wire 920 may be coupled to the first conductive bonding surface 104 and the second conductive bonding surface 108 in parallel to form an electrically parallel connection between the first conductive bonding surface 104 and the second conductive bonding surface 108.
As indicated above,
The first processing stage 1000A may include wire bonding a first end of a first bond wire 1010 to the first conductive bonding surface 104 to form a first conductive bond formation 1012 (e.g. a conductive wedge). The second processing stage 1000B may also include wire bonding a second end of the first bond wire 1010 to the second conductive bonding surface 108 to form a second conductive bond formation 1014 (e.g., a conductive wedge).
As a result, the first conductive bond formation 1012, the first conductive bump 1016, and the third conductive bond formation 1022 may be arranged in a vertical stack on the first conductive bonding surface 104. Additionally, the second conductive bond formation 1014, the second conductive bump 1018, and the fourth conductive bond formation 1024 may be arranged in a vertical stack on the second conductive bonding surface 108. Thus, the first bond wire 910 and the second bond wire 920 may be coupled to the first conductive bonding surface 104 and the second conductive bonding surface 108 in parallel to form an electrically parallel connection between the first conductive bonding surface 104 and the second conductive bonding surface 108.
As indicated above,
The following provides an overview of some Aspects of the present disclosure:
Aspect 1: A method of forming a wire bond assembly, the method comprising: wire bonding a first end of a first bond wire to a first conductive bonding surface arranged on a first substrate to form a first conductive bond formation; wire bonding a second end of the first bond wire to a second conductive bonding surface arranged on a second substrate to form a second conductive bond formation; forming a conductive structure on top of the first conductive bond formation; wire bonding a first end of a second bond wire to a top of the conductive structure to form a third conductive bond formation; and wire bonding a second end of the second bond wire to the second conductive bonding surface to form a fourth conductive bond formation, wherein the fourth conductive bond formation is laterally separated from the second conductive bond formation on the second conductive bonding surface.
Aspect 2: The method of Aspect 1, wherein the first bond wire and the second bond wire are coupled to the first conductive bonding surface and the second conductive bonding surface in a v-configuration to form an electrically parallel connection between the first conductive bonding surface and the second conductive bonding surface.
Aspect 3: The method of any of Aspects 1-2, wherein the first conductive bond formation, the conductive structure, and the third conductive bond formation form a vertical stack on the first conductive bonding surface.
Aspect 4: The method of any of Aspects 1-3, wherein the first conductive bond formation is a first conductive wedge, wherein the second conductive bond formation is a first conductive ball, wherein the third conductive bond formation is a second conductive wedge, and wherein the fourth conductive bond formation is a second conductive ball.
Aspect 5: The method of any of Aspects 1-4, further comprising: forming a first conductive bump on top of the first conductive bonding surface, wherein the conductive structure is a second conductive bump, and wherein the first conductive bond formation is formed on top of the first conductive bump.
Aspect 6: The method of Aspect 5, wherein the first conductive bump is formed directly on the first conductive bonding surface, the first conductive bond formation is formed directly on the first conductive bump, the second conductive bump is formed directly on the first conductive bond formation, and the third conductive bond formation is formed directly on the second conductive bump.
Aspect 7: The method of Aspect 5, further comprising: forming a third conductive bump on top of the second conductive bonding surface; and forming a fourth conductive bump on top of the second conductive bonding surface, wherein the fourth conductive bump is laterally separated from the third conductive bump on the second conductive bonding surface, wherein the second conductive bond formation is formed on top of the third conductive bump, and wherein the fourth conductive bond formation is formed on top of the fourth conductive bump.
Aspect 8: The method of Aspect 7, wherein the first conductive bond formation is a first conductive wedge, wherein the second conductive bond formation is a second conductive wedge, wherein the third conductive bond formation is a third conductive wedge, and wherein the fourth conductive bond formation is a fourth conductive wedge.
Aspect 9: The method of any of Aspects 1-8, further comprising: forming a first conductive bump on top of the first conductive bonding surface, wherein the conductive structure is a second conductive bump, wherein the first conductive bond formation is formed on top of the first conductive bump, wherein the second conductive bond formation is a first conductive wedge formed directly on the second conductive bonding surface, and wherein the fourth conductive bond formation is a second conductive wedge formed directly on the second conductive bonding surface.
Aspect 10: The method of any of Aspects 1-9, wherein the first conductive bond formation is formed directly on the first conductive bonding surface, wherein the second conductive bond formation is a first conductive wedge formed directly on the second conductive bonding surface, and wherein the fourth conductive bond formation is a second conductive wedge formed directly on the second conductive bonding surface.
Aspect 11: The method of any of Aspects 1-10, further comprising: forming a first conductive bump on top of the first conductive bonding surface, wherein the first conductive bond formation is formed on top of the first conductive bump; and forming a second conductive bump on top of the second conductive bonding surface, wherein the fourth conductive bond formation is formed on top of the second conductive bump, wherein the conductive structure is a first conductive ball, wherein the first conductive bond formation is a first conductive wedge, wherein the fourth conductive bond formation is a second conductive wedge, wherein the second conductive bond formation is a second conductive ball, and wherein the third conductive bond formation is formed on top of the first conductive ball.
Aspect 12: The method of any of Aspects 1-11, wherein the conductive structure is a conductive bump, wherein the first conductive bond formation is a first conductive wedge formed directly on the first conductive bonding surface, wherein the third conductive bond formation is a second conductive wedge formed directly on the conductive bump, wherein the second conductive bond formation is a first conductive ball formed directly on the second conductive bonding surface, and wherein the fourth conductive bond formation is a second conductive ball formed directly on the second conductive bonding surface.
Aspect 13: The method of any of Aspects 1-12, further comprising: forming a first conductive bump on top of the first conductive bonding surface, wherein the conductive structure is a second conductive bump, wherein the first conductive bond formation is a first conductive wedge formed on top of the first conductive bump, wherein the second conductive bond formation is a conductive ball formed directly on the second conductive bonding surface, wherein the third conductive bond formation is a second conductive wedge formed directly on the second conductive bump, and wherein the fourth conductive bond formation is a third conductive wedge formed directly on the second conductive bonding surface.
Aspect 14: The method of any of Aspects 1-13, wherein the first substrate is a first circuit substrate or a first semiconductor substrate of a first semiconductor chip, and wherein the second substrate is a second circuit substrate or a second semiconductor substrate of a second semiconductor chip.
Aspect 15: A method of forming a wire bond assembly, the method comprising: wire bonding a first end of a first bond wire to a first conductive bonding surface arranged on a first substrate to form a first conductive bond formation; wire bonding a second end of the first bond wire to a second conductive bonding surface arranged on a second substrate to form a second conductive bond formation; forming a first conductive structure on top of the first conductive bond formation; forming a second conductive structure on top of the second conductive bond formation; wire bonding a first end of a second bond wire to a top of the first conductive structure to form a third conductive bond formation; and wire bonding a second end of the second bond wire to a top of the second conductive structure to form a fourth conductive bond formation.
Aspect 16: The method of Aspect 15, wherein the first conductive bond formation, the first conductive structure, and the third conductive bond formation form a first vertical stack on the first conductive bonding surface, and wherein the second conductive bond formation, the second conductive structure, and the fourth conductive bond formation form a second vertical stack on the second conductive bonding surface.
Aspect 17: The method of any of Aspects 15-16, wherein the first bond wire and the second bond wire are coupled to the first conductive bonding surface and the second conductive bonding surface in parallel.
Aspect 18: The method of any of Aspects 15-17, further comprising: forming a first conductive bump on top of the first conductive bonding surface, wherein the first conductive bond formation is formed on top of the first conductive bump; and forming a second conductive bump on top of the second conductive bonding surface, wherein the fourth conductive bond formation is formed on top of the second conductive bump, wherein the first conductive structure is a third conductive bump, wherein the second conductive structure is a fourth conductive bump, and wherein the first conductive bond formation, the second conductive bond formation, the third conductive bond formation, and the fourth conductive bond formation are conductive wedges.
Aspect 19: The method of any of Aspects 15-18, wherein the first conductive bond formation is a first conductive wedge formed directly on the first conductive bonding surface, wherein the second conductive bond formation is a second conductive wedge formed directly on the second conductive bonding surface, wherein the first conductive structure is a first conductive bump, wherein the second conductive structure is a second conductive bump, wherein the third conductive bond formation is a third conductive wedge formed directly on the first conductive bump, and wherein the fourth conductive bond formation is a fourth conductive wedge formed directly on the second conductive bump.
Aspect 20: The method of any of Aspects 15-19, wherein the first conductive bond formation is a first conductive wedge formed directly on the first conductive bonding surface, wherein the second conductive bond formation is a second conductive wedge formed directly on the second conductive bonding surface, wherein the first conductive structure is a first conductive bump, wherein the second conductive structure is a second conductive bump, wherein the third conductive bond formation is a third conductive wedge formed directly on the first conductive bump, and wherein the fourth conductive bond formation is a conductive ball formed directly on the second conductive bump.
Aspect 21: A wire bond assembly, comprising: a first substrate comprising a first conductive bonding surface; a second substrate comprising a second conductive bonding surface; a first conductive bump arranged on the first conductive bonding surface; a first conductive ball arranged on the second conductive bonding surface, wherein the first conductive ball is bonded to a first end of a first bond wire; a second conductive ball arranged on the second conductive bonding surface, wherein the second conductive ball is bonded to a first end of a second bond wire, and wherein the second conductive ball is laterally separated from the first conductive ball on the second conductive bonding surface; and a second conductive bump, wherein a second end of the first bond wire is wire bonded to a top of the first conductive bump to form a first conductive bond formation, wherein the second conductive bump is arranged on the first conductive bond formation, and wherein a second end of the second bond wire is wire bonded to a top of the second conductive bump to form a second conductive bond formation.
Aspect 22: The wire bond assembly of Aspect 21, wherein the first bond wire and the second bond wire are coupled to the first conductive bonding surface and the second conductive bonding surface in a v-configuration to form an electrically parallel connection between the first conductive bonding surface and the second conductive bonding surface.
Aspect 23: The wire bond assembly of any of Aspects 21-22, wherein the first conductive bump, the first conductive bond formation, the second conductive bump, and the second conductive bond formation form a vertical stack on the first conductive bonding surface.
Aspect 24: The wire bond assembly of any of Aspects 21-23, wherein the first conductive bump is directly coupled to the first conductive bonding surface, the first conductive bond formation is directly coupled to the first conductive bump, the second conductive bump is directly coupled to the first conductive bond formation, and the second conductive bond formation is directly coupled to the second conductive bump.
Aspect 25: A system configured to perform one or more operations recited in one or more of Aspects 1-24.
Aspect 26: An apparatus comprising means for performing one or more operations recited in one or more of Aspects 1-24.
Aspect 27: A non-transitory computer-readable medium storing a set of instructions, the set of instructions comprising one or more instructions that, when executed by a device, cause the device to perform one or more operations recited in one or more of Aspects 1-24.
Aspect 28: A computer program product comprising instructions or code for executing one or more operations recited in one or more of Aspects 1-24.
The foregoing disclosure provides illustration and description, but is not intended to be exhaustive or to limit the implementations to the precise forms disclosed. Modifications and variations may be made in light of the above disclosure or may be acquired from practice of the implementations. Furthermore, any of the implementations described herein may be combined unless the foregoing disclosure expressly provides a reason that one or more implementations may not be combined.
It will be apparent that systems and/or methods described herein may be implemented in different forms of hardware, firmware, or a combination of hardware and software. The actual specialized control hardware or software code used to implement these systems and/or methods is not limiting of the implementations. Thus, the operation and behavior of the systems and/or methods are described herein without reference to specific software code—it being understood that software and hardware can be designed to implement the systems and/or methods based on the description herein.
Even though particular combinations of features are recited in the claims and/or disclosed in the specification, these combinations are not intended to limit the disclosure of various implementations. In fact, many of these features may be combined in ways not specifically recited in the claims and/or disclosed in the specification. Although each dependent claim listed below may directly depend on only one claim, the disclosure of various implementations includes each dependent claim in combination with every other claim in the claim set. As used herein, a phrase referring to “at least one of” a list of items refers to any combination of those items, including single members. As an example, “at least one of: a, b, or c” is intended to cover a, b, c, a-b, a-c, b-c, and a-b-c, as well as any combination with multiple of the same item.
No element, act, or instruction used herein should be construed as critical or essential unless explicitly described as such. Also, as used herein, the articles “a” and “an” are intended to include one or more items, and may be used interchangeably with “one or more.” Further, as used herein, the article “the” is intended to include one or more items referenced in connection with the article “the” and may be used interchangeably with “the one or more.” Furthermore, as used herein, the term “set” is intended to include one or more items (e.g., related items, unrelated items, or a combination of related and unrelated items), and may be used interchangeably with “one or more.” Where only one item is intended, the phrase “only one” or similar language is used. Also, as used herein, the terms “has,” “have,” “having,” or the like are intended to be open-ended terms. Further, the phrase “based on” is intended to mean “based, at least in part, on” unless explicitly stated otherwise. Also, as used herein, the term “or” is intended to be inclusive when used in a series and may be used interchangeably with “and/or,” unless explicitly stated otherwise (e.g., if used in combination with “either” or “only one of”). Further, spatially relative terms, such as “below,” “lower,” “above,” “upper,” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the apparatus, device, and/or element in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
This patent application claims priority to U.S. Provisional Patent Application No. 63/619,031, filed on Jan. 9, 2024, and entitled “V-BONDING USING DOUBLE STACKED STAND-OFF-STITCH FOR IMPROVED RF PERFORMANCE.” The disclosure of the prior application is considered part of and is incorporated by reference into this patent application.
| Number | Date | Country | |
|---|---|---|---|
| 63619031 | Jan 2024 | US |
