Patent Application
20240313103
The present disclosure relates to a field of semiconductors, in particular to a vertical MOSFET device and method of manufacturing a vertical MOSFET device.
Currently, a planar Metal Oxide Semiconductor Field Effect Transistor (MOSFET) may not be easily downsized because a source electrode, a gate electrode, and a drain electrode are arranged in a horizontal direction. A vertical MOSFET device has advantages over a horizontal MOSFET device because the source electrode, the gate electrode, and the drain electrode are perpendicular to a scaling direction.
However, the existing vertical MOSFET device still has technical defects that are difficult to overcome. For example, it is difficult to control a gate length of the vertical MOSFET device, especially for a single crystal channel material. In addition, if a channel material is polycrystalline, a channel resistance is much higher than that of single crystal, and it is difficult to stack a plurality of vertical devices due to a total resistance being too high.
In view of above, an object of the present disclosure is at least in part to provide a vertical MOSFET device with a self-aligned spacer and a method of manufacturing a vertical MOSFET device.
According to an aspect of the present disclosure, there is provided a vertical MOSFET device, including: a substrate; an active region including a first source/drain layer, a channel layer and a second source/drain layer vertically stacked on the substrate in sequence, wherein an outer periphery of the channel layer is recessed with respect to an outer periphery of the first source/drain layer and an outer periphery of the second source/drain layer; a spacing layer including an upper spacing layer and a lower spacing layer, wherein the upper spacing layer is formed on a lower surface of the second source/drain layer exposed by a recess of the channel layer, the lower spacing layer is formed on an upper surface of the first source/drain layer exposed by the recess of the channel layer, and the upper spacing layer and the lower spacing layer are in contact with a side surface of the channel layer and are not in communication with each other; and a gate stack formed at least on a lateral outer periphery of the channel layer and embedded in a groove space between the upper spacing layer and the lower spacing layer.
According to another aspect of the present disclosure, there is provided a method of manufacturing a vertical MOSFET device, including: forming an active region including a first source/drain layer, a channel layer and a second source/drain layer sequentially on a substrate in a vertical direction, wherein an outer periphery of the channel layer have a recess portion with respect to an outer periphery of the first source/drain layer and an outer periphery of the second source/drain layer; covering a dummy structure layer on an outer surface of the active region, selectively etching the dummy structure layer, so that an upper surface of the first source/drain layer and a lower surface of the second source/drain layer respectively retain a second portion dummy structure layer, wherein the second portion dummy structure layer sandwiches the channel layer from opposite sides of the channel layer; growing a dummy gate structure layer in a groove space formed by an inner wall of the second portion dummy structure layer and the outer periphery of the channel layer, and replacing the second portion dummy structure layer with a spacing layer; forming a first dielectric layer on the first source/drain layer, removing the dummy gate structure layer, and forming a gate dielectric layer and a gate conductor layer on the groove space and the first dielectric layer; selectively etching the gate conductor layer, and forming metal contact portions on the first source/drain layer, the gate conductor layer and the second source/drain layer, respectively.
According to another aspect of the present disclosure, there is provided an electronic device including the vertical MOSFET device described above.
The above and other objectives, features and advantages of the present disclosure will be more apparent through the following description of embodiments of the present disclosure with reference to the accompanying drawings.
Throughout the drawings, the same or similar reference numerals represent the same or similar components. The accompanying drawings are not necessarily drawn to scale, and especially for the sake of clarity, the drawing scale of the section views is different from that of the top views.
Embodiments of the present disclosure will be described below with reference to the accompanying drawings. It should be understood, however, that these descriptions are merely exemplary and are not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessarily obscuring the concepts of the present disclosure.
Various schematic structural diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. The drawings are not drawn to scale. Some details are enlarged and some details may be omitted for clarity of presentation. Shapes of various regions and layers as well as the relative size and positional relationship thereof shown in the drawings are only exemplary. In practice, there may be deviations due to manufacturing tolerances or technical limitations, and those skilled in the art may additionally design regions/layers with different shapes, sizes, and relative positions according to actual needs.
In the context of the present disclosure, when a layer/element is referred to as being “on” another layer/element, the layer/element may be directly on the other layer/element, or there may be an intermediate layer/element between them. In addition, if a layer/element is located “on” another layer/element in one orientation, the layer/element may be located “under” the other layer/element when the orientation is reversed.
The present disclosure may be presented in various forms, some examples of which will be described below. In the following descriptions, a selection of various materials is involved. In the selection of materials, in addition to a function of the material (for example, a semiconductor material may be used to form the active region, and a dielectric material may be used to form an electrical isolation), the etching selectivity is also considered. In the following descriptions, a required etching selectivity may or may not be indicated. It should be clear to those skilled in the art that when it is mentioned below that a material layer is etched, if it is not mentioned or shown that other layers are also etched, then the etching may be selective, and the material layer may have an etching selectivity relative to other layers exposed to a same etching recipe.
Embodiments of the present disclosure provide a vertical MOSFET device. The vertical MOSFET device refers to that an active region (especially a channel region) of the vertical MOSFET device extends in a vertical direction (e.g., a direction perpendicular or substantially perpendicular to a substrate surface) with respect to a substrate. The active region may be made of a single crystal semiconductor material to improve a device performance. A gate stack may be formed around an outside of a middle portion of the active region. The vertical MOSFET device may be based on a vertical type Metal Oxide Field Effect Transistor (MOSFET). Compared to a horizontal type MOSFET, the vertical type MOSFET may have a smaller footprint and a smaller leakage current, but a relatively smaller on-current.
The vertical MOSFET device provided by embodiments of the present disclosure includes: a substrate; an active region including a first source/drain layer 1003, a channel layer 200 and a second source/drain layer 1007 vertically stacked on the substrate in sequence, wherein an outer periphery of the channel layer 200 is recessed with respect to outer peripheries of the first source/drain layer 1003 and the second source/drain layer 1007; a spacing layer 3001 including an upper spacing layer and a lower spacing layer, wherein the upper spacing layer is formed on a lower surface of the second source/drain layer 1007 exposed by a recess of the channel layer 200, the lower spacing layer is formed on an upper surface of the first source/drain layer 1003 exposed by the recess of the channel layer 200, the upper spacing layer and the lower spacing layer are both in contact with a side surface of the channel layer 200 and are not in communication with each other; and a gate stack formed at least on a lateral outer periphery of the channel layer 200 and embedded in a groove space between the upper spacing layer and the lower spacing layer.
According to embodiments of the present disclosure, each of the first source/drain layer 1003, the channel layer 200 and the second source/drain layer 1007 has a thickness of 10 nm to 100 nm.
According to embodiments of the present disclosure, the gate stack includes a gate dielectric layer 3002 and a gate conductor layer 5001, and the gate conductor layer 5001 includes a work function adjusting metal and a gate conductive metal disposed on the work function adjusting metal.
According to embodiments of the present disclosure, the vertical MOSFET device further includes: a first dielectric layer 4001 disposed on the first source/drain layer 1003.
Further, a height of the first dielectric layer 4001 is higher than a bottom surface of the channel layer 200 and lower than a top surface of the lower spacing layer immediately adjacent the bottom surface of the channel layer 200.
Further, the gate dielectric layer 3002 and the gate conductor layer 5001 are further partially disposed on the first dielectric layer 4001.
Further, the gate conductor layer 5001 is exposed at a portion outside the groove space, and is exposed at another portion outside the groove space.
According to embodiments of the present disclosure, the vertical MOSFET device further includes: a second dielectric layer 4002 disposed on upper surfaces of the gate dielectric layer 3002 and the gate conductor layer 5001, wherein the second dielectric layer 4002 has a same material as the first dielectric layer 4001.
According to embodiments of the present disclosure, the spacing layer 3001 is aligned with a lateral outer edge of the first source/drain layer 1003 and a lateral outer edge of the second source/drain layer 1007.
According to embodiments of the present disclosure, the vertical MOSFET device further includes: metal contact portions respectively embedded in the first source/drain layer 1003, the gate conductor layer 5001 and the second source/drain layer 1007.
It should be noted that embodiments of the apparatus portion is similar to embodiments of the method portion, and the achieved technical effects are also similar, and for specific details, please refer to embodiments of the method portion, which is not repeated herein.
Based on a same inventive concept, embodiments of the present disclosure further provide a method of manufacturing a vertical MOSFET device, including following steps.
In Step S1, a first source/drain layer 1003, a channel layer 200 and a second source/drain layer 1007 are sequentially formed on a substrate in a vertical direction, wherein an active region includes the first source/drain layer 1003, the channel layer 200 and the second source/drain layer 1007, and an outer periphery of the channel layer 200 has a recess portion with respect to an outer periphery of the first source/drain layer 1003 and an outer periphery of the second source/drain layer 1007.
In Step S2, a dummy structure layer 1009 is covered on an outer surface of the active region; the dummy structure layer 1009 is selectively etched, so that an upper surface of the first source/drain layer 1003 and a lower surface of the second source/drain layer 1007 respectively retain a second portion dummy structure layer 10092, wherein the second portion dummy structure layer 10092 sandwiches the channel layer 200 from opposite sides of the channel layer 200.
In Step S3, a dummy gate structure layer 2001 is grown in a groove space formed by an inner wall of the second portion dummy structure layer 10092 and the outer periphery of the channel layer 200, and the second portion dummy structure layer 10092 is replaced with a spacing layer 3001.
In Step S4, a first dielectric layer 4001 is formed on the first source/drain layer 1003, the dummy gate structure layer 2001 is removed, and a gate dielectric layer 3002 and a gate conductor layer 5001 are formed on the groove space and the first dielectric layer 4001.
In Step S5, the gate conductor layer 5001 is selectively etched, and metal contact portions are formed on the first source/drain layer 1003, the gate conductor layer 5001 and the second source/drain layer 1007, respectively.
Since a function of the dummy structure layer 1009 is to fill and occupy a certain space in the recess portion of the channel layer 200 and facilitate subsequent replacement with the spacing layer 3001, the dummy structure layer 1009 may also be referred to as “a position retaining layer”, or “a sacrificial layer”.
As shown in
In the substrate 1001, a well region may be formed. If a p-type device is to be formed, the well region may be an n-type well; and if an n-type device is to be formed, the well region may be a p-type well. Generally, in a DRAM, the storage unit is based on the n-type device. Therefore, for example, the p-type well may be formed by injecting a p-type dopant such as boron (B) into the substrate 1001 and then performing a thermal annealing. For example, a doping concentration of boron (B) may be about 1E19 to 1E21/cm−3.
Hereinafter, a formation of the n-type device is illustrated by way of example. It is clear to those skilled in the art that the following description is also applicable to the p-type device by, for example, appropriately adjusting a doped conductive type.
On the substrate 1001, a first source/drain layer 1003, a channel defining layer 1005, and a second source/drain layer 1007 may be formed, for example, by an epitaxial growth. The first source/drain layer 1003 may be used to define a position of a lower source/drain portion, and may have a thickness of, for example, about 10 nm to 100 nm. The channel defining layer 1005 may be used to define a position of the channel, and may have a thickness of, for example, about 10 nm to 100 nm. The second source/drain layer 1005 may be used to define a position of an upper source/drain portion, and may have a thickness of, for example, about 10 nm to 100 nm.
Adjacent layers in the first source/drain layer 1003, the channel defining layer 1005, and the second source/drain layer 1007 may have an etching selectivity relative to each other. For example, the first source/drain layer 1003 may include Si, the channel defining layer 1005 may include SiGe (a composition of Ge may be, for example, about 10% to 40%), and the second source/drain layer 1007 may include Si.
The first source/drain layer 1003 and the second source/drain layer 1007 may adopt a low-temperature epitaxial process, and a growth temperature should be less than 900° C. to avoid impurity diffusion. In other embodiments, other doping methods may also be used, such as implantation or gas phase diffusion technology. The first source/drain layer 1003 and the second source/drain layer 1007 may be doped in situ while being grown, so as to (at least partially) define a doping characteristic of a source/drain portion.
It should also be noted that
The substrate is a (110) crystal plane, and the channel layer is a (001) crystal plane.
As shown in
The active region of the vertical MOSFET device is thereby defined, and the active region includes an upper portion of the etched first source/drain layer 1003, the channel defining layer 1005, and the second source/drain layer 1007. At this point, a spacer is formed on outer peripheries of two opposite sides of the channel defining layer 1005 in the x direction, and the spacer is the x direction crystal plane.
As shown in
Specifically, the present disclosure may perform etching along the outer periphery of the channel defining layer 1005 toward the middle, and retain the channel defining layer 1005 in the middle portion, thereby forming an approximately cylindrical channel layer 200. The recess portion formed in this way may be self-aligned to the channel layer 200.
In order to better control an etching depth, the selective etching may use wet etching or atomic layer etching (ALE). Thus, in this embodiment, the channel layer 200 having the recess portion may be formed on the substrate 1001.
As shown in
Thus, the dummy structure layer 1009 covers outer surfaces of the second source/drain layer 1007, the channel layer 200 and the first source/drain layer 1003. It should be noted that since an epitaxial growth rate in the y direction is higher than that in the x direction, during an epitaxial growth process, the dummy structure layer 1009 in the x direction in
As shown in
Specifically, the partial etching may include: dummy structure layers located on opposite sides of surfaces of the second source/drain layer 1007, the channel layer 200 and the first source/drain layer 1003 in the x direction are etched away in the x direction, and the first portion dummy structure layer 10091 in the y direction is retained.
After atomic layer etching and controlling an etching depth, the first portion dummy structure layer 10091 may retain an approximately same thickness, but the approximately same thickness is smaller than a thickness of the dummy structure layer 1009 epitaxially grown in the y direction in
As shown in
Specifically, the second portion dummy structure layer 10092 is located on the upper surface of the first source/drain layer 1003 and the lower surface of the second source/drain layer 1007, respectively, and horizontally sandwiches the channel layer 200 from opposite sides of the channel layer 200. The second portion dummy structure layer 10092 is not retained at a middle position of the channel layer 200.
As shown in
In order to control a deposition growth size, redundant dummy gate structure layer 2001 located at an edge of the second portion dummy structure layer 10092 needs to be etched away by the reactive ion etching to form the dummy gate structure layer 2001 which is aligned with outer edges of the second source/drain layer 1007 and the first source/drain layer 1003. Thus, the dummy gate structure layer 2001 is filled, so as to fill the groove space where the channel layer 200 is located.
As shown in
The spacing layer 3001 may be made of a dielectric material with a low dielectric constant or a SiN material. The deposition growth method may adopt atomic layer deposition or chemical vapor deposition.
It should be noted that, in order to control the deposition growth size, redundant spacer layer 3001 located at an outer edge of a corresponding position of the second portion dummy structure layer 10092 needs to be etched away by the reactive ion etching, so as to form the spacing layer 3001 which is aligned with the lateral outer edges of the second source/drain layer 1007 and the first source/drain layer 1003.
As shown in
A material of the first dielectric layer 4001 may be silicon oxide. The preset height of the first dielectric layer 4001 is higher than a bottom surface of the channel layer 200 and lower than a top surface of the lower spacing layer immediately adjacent the bottom surface of the channel layer 200.
Thus, a height setting of the first dielectric layer 4001 facilitates forming a self-aligned gate structure between the first source/drain layer 1003 and the second source/drain layer 1007 after removing the dummy gate structure layer 2001.
In embodiments of the present disclosure, the term “self-aligned” does not necessarily mean perfect alignment. “Self-aligned” refers to that relative positions between structures are substantially unaffected by process fluctuations, especially lithography fluctuations. Such self-aligned structures are detectable. For example, there may be a plurality of such devices in an integrated circuit (IC), and if the devices are of a self-aligned structure, a positional relationship of a low-k dielectric layer and the spacer in each device with respect to an end portion of the channel region may remain substantially unchanged, and if the devices are not a self-aligned structure, this relative positional relationship may present process fluctuations between devices.
As shown in
The gate dielectric layer 3002 may be made of a dielectric material having a high dielectric constant, such as HfO2, with a thickness of about 1 nm to 5 nm. The gate conductor layer 5001 may be deposited and formed on the surface of the gate dielectric layer 3002 in a substantially conformal manner so as to extend along the surface of the gate dielectric layer 3002. In addition, before depositing the gate dielectric layer 3002, an interface layer such as silicon oxide material (not shown in
The gate conductor layer 5001 may include a work function adjusting metal and a gate conductive metal. The work function adjusting metal may include, for example, a TiN material with a thickness of, for example, about 1 nm to 10 nm. The gate conductive metal may include, for example, a W material with a thickness of about 100 nm to 800 nm.
Thus, the gate conductor layer 5001 may fill a space between active regions of each device. The gate stack formed in this way (including the gate dielectric layer 3002 and the gate conductor layer 5001) may be embedded between the first source/drain layer 1003 and the second source/drain layer 1007, and the gate stack is formed at least on the lateral outer periphery of the channel layer 200 and embedded in the groove space between the upper spacing layer and the lower spacing layer. In order to control the etching depth, it is necessary to etch back the formed gate stack finally.
As shown in
The photoresist 500 is patterned, for example, by photolithography to cover a portion of the gate conductor layer 5001 exposed outside the groove space of the channel layer 200 (in this example, a left half of
Then, as shown in
Therefore, in addition to a portion of the gate conductor layer 5001 retained in the groove space, a portion shielded by the photoresist 500 is also retained.
As shown in
Specifically, the second dielectric layer 4002 may be the same as the first dielectric layer 4001, that is, a material of the second dielectric layer 4002 may also be silicon oxide. The metal contact portions include: a first source/drain contact portion 6001 formed on the first source/drain layer 1003, a gate contact portion 6002 formed on the gate conductor layer 5001, and a second source/drain contact portion 6003 formed on the second source/drain layer 1007. The first source/drain contact portion 6001, the gate contact portion 6002, and the second source/drain contact portion 6003 may be formed using a conventional process.
In addition, since the gate conductor layer 5001 extends beyond the outer periphery of the active region, the gate contact portion 6002 may be easily formed. Meanwhile, since the gate conductor layer 5001 does not exist over at least a portion of the first source/drain layer 1003, the first source/drain contact portion 6001 may be easily formed.
Thus, the vertical MOSFET device of embodiments of the present disclosure is manufactured. The vertical MOSFET device of embodiments has the function of self-aligned spacer, and a dummy spacer structure is formed by using the characteristic that epitaxial growth rates on different crystal planes are different, and the epitaxial growth rate in the channel direction is relatively high.
Compared with the related art, the vertical MOSFET device and the method of manufacturing a vertical MOSFET device provided by the present disclosure have at least following beneficial effects: the vertical MOSFET device has a function of self-aligned spacer, and uses a characteristic that epitaxial growth rates on different crystal planes are different to form a dummy spacer structure, and an epitaxial growth rate in a channel direction is relatively high.
The vertical MOSFET device according to embodiments of the present disclosure may be applied to various electronic devices. For example, the electronic device may include the vertical MOSFET device and a processor. The vertical MOSFET device may store data required for an operation of the electronic device or data obtained during an operation. The processor may operate based on data and/or applications stored in the vertical MOSFET device. The electronic device may include, for example, a smart phone, a personal computer (PC), a tablet computer, a wearable device, an artificial intelligence device, a portable power source, and so on.
In the above description, the technical details such as patterning and etching of each layer have not been described in detail. However, those skilled in the art should understand that various technical means may be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art may further design a method that is not completely the same as the method described above. In addition, although the various embodiments are described above separately, this does not mean that the measures in the various embodiments may not be advantageously used in combination.
The embodiments of the present disclosure have been described above. However, these embodiments are for illustrative purposes only, and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art may make various substitutions and modifications, and these substitutions and modifications should all fall within the scope of the present disclosure.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202111514468.9 | Dec 2021 | CN | national |
This application is a Section 371 National Stage Application of International Application No. PCT/CN2021/137863, filed on Dec. 14, 2021, entitled “VERTICAL MOSFET DEVICE AND METHOD OF MANUFACTURING VERTICAL MOSFET DEVICE”, which claims priority to Chinese Application No. 202111514468.9, filed on Dec. 10, 2021, incorporated herein by reference in their entirety.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/CN2021/137863 | 12/14/2021 | WO |
