The present invention relates to an evaluation (assessment) apparatus of voids in solder and an evaluation (assessment) method of voids in solder.
Japanese Laid-open Patent Application Publication No. 2006-226875 discloses a method of detecting a bonding defect of a solder ball by X-ray. In this method, the bonding defect of the solder ball is evaluated by an area, flatness and the like.
In recent years, automatic detection techniques of voids have been developed as a performance evaluation of a BGA (Ball Grid Array). These use statistical procedures as a principle of operation.
For example the number of voids and a ratio of the void area to the solder ball are used as the index indicating the reliability of the solder ball, as detailed in Non-Patent Documents 1 and 2.
Patent Document 1
However, the following problems are pointed out in the above methods. First, one problem is that only the number of voids and the ratio of the void area to the solder ball are used as the index indicating the reliability of the solder balls. Certainly, because increases of the number of voids lead to a bad connection of BGA and increases of the ratio of the void area to the solder ball lead to a poor connection of BGA, they may be an indicator of evaluation. However, the present inventors found that it is insufficient to determine an indicator of evaluation only by the number of voids and the ratio of the void area to the solder ball, and that it is more important for voids to be existed in any position for BGA. In particular, the present inventors found that the effect on joint strength becomes large as the void is located in the center of the solder ball.
Another problem is an evaluation speed. In the conventional method it takes a very long time to calculate. Because the number of solder balls per package may exceed 1000, it is not preferable to take a lot of time for evaluation.
Thus it is for an object of the present invention to provide the evaluation apparatus and the method of evaluating voids in the solder, wherein the voids in the solder can be evaluated at a high speed and more precisely.
A void evaluation apparatus in a solder according to the present invention includes:
an evaluation function calculation unit for calculating a solder evaluation function as shown the following, by using that a pixel value pi contained in the voids is set to 1 and the pixel value pi not contained in the voids is 0 for each pixel constituting an image in the solder, and by using a weight function w(ri), which is maximum at a solder center (ri=0) and is 0 at a maximum radius (ri=r0) for a distance ri from the solder center; and
a void evaluation unit for evaluating that the influence of void is larger as the evaluation function is relatively larger for the each solder.
According to the void evaluation method in the solder concerning the present invention, the voids in each solder can be evaluated at a high speed and accurately.
A void evaluation apparatus in a solder according to first aspect includes:
an evaluation function calculation unit for calculating a void evaluation function as shown the following, by using that a pixel value pi contained in the voids is set to 1 and the pixel value pi not contained in the voids is 0 for each pixel constituting an image in the solder, and by using a weight function w(ri), which is maximum at a solder center (ri=0) and is 0 at a maximum radius (ri=r0) for a distance ri from the solder center; and
a void evaluation unit for evaluating that the influence of voids is larger as the evaluation function is relatively larger for the each solder.
The void evaluation apparatus in the solder according to second aspect may further comprise an image extraction unit, which extracts an image in each solder from the two-dimensional X-ray images according to first aspect.
The void evaluation apparatus in the solder according to third aspect may further include a void detection unit, which detects voids for the images in the solder according to first or second aspect.
The void evaluation apparatus in the solder according to fourth aspect, the weighting function w(ri) may be a (r0−ri) in any one of first to third aspects.
A void evaluation method in the solder according to fifth aspect includes:
a step for calculating an evaluation function as shown the following, by using that a pixel value pi contained in the voids is set to 1 and the pixel value pi not contained in the voids is 0 for each pixel constituting an image in the solder, and by using a weight function w(ri), which is maximum at the solder center (ri=0) and is 0 at a maximum radius (ri=r0) for a distance ri from the solder center; and
a step for evaluating that the influence of void is larger as a value of the evaluation function is relatively larger for the each solder.
The void evaluation method in the solder according to sixth aspect may further include the step of extracting an image in each solder from the two-dimensional X-ray images in the above fifth aspecy, and the step of detecting the void portion of images in each solder.
In the void evaluation method in the solder according to seventh aspect, the weighting function w(ri) may be a (r0−ri) in the above fifth or sixth aspect.
The void evaluation computer program according to eighth aspect evaluates voids in the solder, by executing each step of the void evaluation method in the solder to the computer according to any of fifth to seventh aspects.
The computer-readable recording medium according to ninth aspect stores the void evaluation computer program in the solder according to eighth aspect.
(Embodiment 1)
The void evaluation apparatus 10 in this solder includes an evaluation function calculation unit 13 and a void evaluation unit 14 as a functional structure. Incidentally, an image extraction unit 11 and a void detection unit 12 may be included. The image extraction unit 11 extracts the image in the solder from the two-dimensional X-ray images. A void detection unit 12 detects voids of the image in each solder. The evaluation function calculation unit 13 calculates the evaluation function in each solder by using its pixel value and the weighting function w(ri) for each pixel constituting the image in the solder. The void evaluation unit 14 evaluates that the influence of voids is larger as the evaluation function is relatively larger for the each solder.
Further, this void evaluation apparatus 10 in the solder includes CPU 21, memory 22, storage device 23, input-output device 24, the display device 25 and an interface 26 as a physical configuration. That is, this void evaluation apparatus 10 in the solder can be realized by a personal computer, which operates the software for achieving the above-described functional configuration.
(Advantageous Effect)
The void evaluation apparatus in the solder according to the embodiment 1 can perform automatic evaluation of voids in the solder at high speed and adequately.
The influence of voids in actual solder balls, for example, appears as a connection failure because the bonding strength of the solder portion is reduced. It is believed that a crack in the solder occurs by the voids in the solder and the connection failure or the entire apparatus malfunction eventually occurs. The void evaluation apparatus in the solder according to the embodiment 1 can suppress the occurrence of the connection failure at the solder portion.
The following describes the components of the void evaluation apparatus in this solder.
<Image Extraction Unit>
An image extraction unit 11 extracts the image in the solder from the two-dimensional X-ray images. The operation of the image extraction unit 11 will be described below by using
1) Two-dimensional X-ray Images
2) Removal of Interfering Member
3) Circle Detection Corresponding to the Solder Balls
4) Extraction of Image in Each Solder
<Void Detection Unit>
A void detection unit 12 detects voids in the image of each solder. The operation of the void detection unit 12 will be described below by using
1) The Intensity Distribution of the Original Image and the Target Histogram
Even if voids in the solder balls appeared bright in the image in one solder, it was actually difficult to detect these voids by various factors. For example, poor image contrasts, irregular shapes produced by a void overlap, the various void size/position and influences of other members are cited as a factor.
2) Enhancement of the Overall Image Contrast by Using a Matching Histogram Equalization Method
The quality of the image contrast is changed in accordance with the setting of various data acquisition. Therefore, at first, the conversion of input intensity can enhance the overall image contrast and match the desired target histogram with better contrast a histogram of output intensity.
3) Enhancement of the Local Contrast Using the Applicable Histogram Equalization Method
If the image contrast of the original two-dimensional X-ray images is not good, by CLAHE (Contrast Limited Adaptive Histogram Equalization) after smoothing the images, the local contrast of the local region may be improved. In this case, in order to avoid amplification of noise, it is necessary to control the contrast level.
4) The Discovery of the Boundary between the Concatenated Voids due to the Application of the Water Shedding Algorithm.
Boundaries of each void may be effectively determined by applying the Laplacian of Gaussian filter, which detects suitable sizes of the edge. Sometimes continuous voids may be detected as a single concatenated void accidentally. Therefore, it is possible to find the boundaries separating the continuous voids by applying the Water shedding algorithm. Incidentally, the edge detection algorithm is not limited to the above Water shedding algorithm, may be used other algorithms.
5) Complete Separation of Concatenated Voids
In
<Evaluation Function Calculation Unit>
An evaluation function calculation unit 13 calculates a solder evaluation function by using that a pixel value pi contained in the voids is set to 1 and the pixel value pi not contained in the voids is 0 for each pixel constituting an image in the solder, and by using a weight function w(ri), which is maximum at the solder center (ri=0) and is 0 at a maximum radius (ri=r0) for a distance ri from the solder center.
a) The Case of the Weighting of the Pixel-by-pixel Basis
In this case, the evaluation function is defined by the following expression (1).
In the evaluation function of expression (1), i is the pixel number and is from No. 1 to N.
pi is the each pixel value and takes a 0 or 1. Moreover, the weighting function w(ri) may be determined depending on the influence of voids is represented by any function on the distance ri from the BGA center. The present inventors have been led to the present invention by setting the weighting function, wherein the influence is larger as the position of the void is closer to the BGA center and the influence is set as a 0 when it exceeds the maximum radius (r0) of the BGA. For example, weighting function w(ri) may be used as a (r0−ri). The evaluation function in this case is defined by the following expression (2).
Incidentally, the weighting function is not limited to the above case. While the boundary conditions that it is maximum at the BGA center (ri=0) and is 0 at the maximum radius (ri=r0) are satisfied, the weighting function to fit the relation between the evaluation characteristics may be selected. When receiving greater the effect of the distance ri, for example, a quadratic function ((r0−ri)2) or higher order functions or the like may be selected.
b) The Case of the Weighting for Each Void
Also, unlike in the case of each pixel, the evaluation may be performed for each void. In this case, it may be evaluated for each void area Sj. This may be calculated on the assumption that Sj number of pixels at the void center is gathered. In this case, the evaluation function is defined by the following expression (3).
Here, in the numerator, it is for pixels contained in the void to be processed about the void area Sj for the center of the j-th void rather than individual pixels. In this case, the pixels not contained in the void are not shown in the numerator because the area is treated as 0 in the same manner as described above. On the other hand, the denominator is the expression for all pixels in the same manner as the above expression (2). When dealing with solder balls of a certain size, the denominator may be treated as a constant.
Incidentally, it may be evaluated for each void volume Vj instead of each void area Sj. In this case, the evaluation function is defined by the following expression (4).
By using the area Sj, the expression (4) is expressed by the following expression (5).
The evaluation function is not limited to any shown by the above expressions (1) to (5). The evaluation function may be any one which uses the weight function w(ri), wherein the distance ri from the solder center becomes maximum at the solder center (ri=0) and becomes 0 at the maximum radius (ri=r0). For example, it may be the evaluation function which can evaluate more adequately the effects of two-dimensional/three-dimensional shape of the void.
<Void Evaluation Unit>
A void evaluation unit 14 evaluates that the influence of void is larger as the evaluation function is relatively larger for the each solder.
Conventionally, for example, the number of voids and the ratio of the void area to the solder ball area have been used as an indicator of the severity of the influence given by voids in the solder. On the contrary, according to the void evaluation apparatus in the solder on the embodiment 1, the influence of voids in the solder can be evaluated at a high speed and accurately by calculating the evaluation function that uses the weighting function to consider the void with large influence, as compared with the conventional method.
<Void Evaluation Method in the Solder>
In the void evaluation method according to the embodiment 1, it is characterized that the evaluation of voids in the solder is processed by the evaluation function weighted with a weighting function w(ri) for the distance ri from the BGA center of the void.
The void evaluation method in the solder includes the following steps.
(a) Extracting the image in each solder from the two-dimensional X-ray images (S01).
(b) Detecting the void for the image in each solder (S02).
(c) Calculating the evaluation function by using that a pixel value pi contained in the voids is set to 1 and the pixel value pi not contained in the voids is 0 for each pixel constituting an image in the solder, and by using a weight function w(ri) which is maximum at the solder center (ri=0) and is 0 at a maximum radius (ri=r0) for a distance ri from the solder center (S03).
The evaluation function, for example, is defined by the following expression.
(d) Evaluating that the influence of voids is larger as the evaluation function is relatively larger for each solder (S04). By the above steps, the voids in each solder can be automatically evaluated at a high speed and accurately.
(Advantageous Effect)
According to the void evaluation method in the solder concerning the present invention, the automatic evaluation of the voids in the solder can be performed at a high speed and accurately.
<Void Evaluation Computer Program in the Solder>
By executing the steps of the method of evaluating the voids in the solder to a computer, it is possible to be the void evaluation computer program in the solder for performing the evaluation of voids in the solder. Moreover, this void evaluation computer program in the solder may be stored in a computer-readable recording medium. The compute -readable recording medium may be any of the following: a floppy disk, magnetic recording media such as magnetic tape, compact disc (CD), digital versatile disk (DVD), Blu-Ray (registered trademark) disk (BD) or the like of the optical recording medium , a magneto-optical recording medium, USB memory and any of a semiconductor storage medium such as a flash memory.
According to the void evaluation apparatus and the void evaluation method in the solder concerning the present invention, the automatic evaluation of the voids in the solder can be performed at a high speed and accurately. Therefore, the present invention is useful in the evaluation apparatus of the soldered circuit board or the manufacturing apparatus of a semiconductor device including these applications.
Number | Date | Country | Kind |
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2013-237024 | Nov 2013 | JP | national |
Filing Document | Filing Date | Country | Kind |
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PCT/JP2014/079717 | 11/10/2014 | WO | 00 |
Publishing Document | Publishing Date | Country | Kind |
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WO2015/072424 | 5/21/2015 | WO | A |
Number | Name | Date | Kind |
---|---|---|---|
20110081070 | Yamamoto | Apr 2011 | A1 |
20110255768 | McElfresh | Oct 2011 | A1 |
20160148899 | Ichimura | May 2016 | A1 |
Number | Date | Country |
---|---|---|
2004-198206 | Jul 2004 | JP |
2004198206 | Jul 2004 | JP |
2006-226875 | Aug 2006 | JP |
2007-121082 | May 2007 | JP |
Entry |
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International Search Report dated Feb. 10, 2015 in corresponding Japanese Application No. PCT/JP2014/079717; 1 pg. |
Asaad F. Said et al., “Robust Automatic Void Detection in Solder Balls”, ICASSP 2010, p. 1650-1653, IEEE International Conference on IEEE, 2010, 4 pgs. |
Shao-hu Peng, Hyun Do Nam, “Void defect detection in ball grid array X-ray images using a new blob filter”, Journal of Zhejiang University—Science C, 2012, p. 840-849, 10 pgs. |
Notification of Transmittal of Translation of the International Preliminary Report on Patentability dated May 26, 2016, in connection with corresponding PCT Application No. PCT/JP2014/079717 (7 pgs). |
Number | Date | Country | |
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20160267646 A1 | Sep 2016 | US |