Patent Application
20230031722
With advances in semiconductor technology, there has been an increasing demand for higher storage capacity, faster processing systems, higher performance, and lower costs. To meet these demands, the semiconductor industry continues to scale down the dimensions of semiconductor devices. Such scaling down has increased the complexity of semiconductor manufacturing processes and the demands for the precision of features in semiconductor manufacturing systems.
Aspects of this disclosure are best understood from the following detailed description when read with the accompanying figures.
Illustrative embodiments will now be described with reference to the accompanying drawings. In the drawings, like reference numerals generally indicate identical, functionally similar, and/or structurally similar elements.
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. As used herein, the formation of a first feature on a second feature means the first feature is formed in direct contact with the second feature. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” and the like may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
It is noted that references in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” “exemplary,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phases do not necessarily refer to the same embodiment. Further, when a particular feature, structure or characteristic is described in connection with an embodiment, it would be within the knowledge of one skilled in the art to effect such feature, structure or characteristic in connection with other embodiments whether or not explicitly described.
It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by those skilled in relevant art(s) in light of the teachings herein.
In some embodiments, the terms “about” and “substantially” can indicate a value of a given quantity that varies within 5% of the value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of the value). These values are merely examples and are not intended to be limiting. The terms “about” and “substantially” can refer to a percentage of the values as interpreted by those skilled in relevant art(s) in light of the teachings herein.
Ion beam etching (IBE) is a process that utilizes an inert gas plasma to bombard an etching target (e.g., a wafer) with ions to remove materials from the wafer. An IBE system includes a plasma chamber and a multi-grid (e.g., three-grid) optics system. In description below, a three-grid system is used as an example of a multi-grid optics system. The three-grid system has numerous electrostatic apertures (holes) separated from each other, e.g., sometimes by a few millimeters. Applying specific voltages to each grid, the three-grid system controls the holes and ion beams through the holes. In detail, the three-grid system extracts positively charged ions from inductively coupled plasma (ICP, also referred to as inductively coupled discharge plasma) generated in the plasma chamber. In addition, the three-grid system further accelerates and directs the ions through the holes to form mono-energetic beams of the ions, or ion beams, to etch materials by physical sputtering on the wafer. Controlled by the three-grid system, an individual ion beam is created through each hole. The combination of the ion beams controlled by the three-grid system form a single broad beam to bombard the etching target. In an IBE process, an etching target (e.g., a wafer) can be placed with a tilted angle and/or a rotated angle to allow an angle of incidence of the ions onto the surface of the wafer. Such control of the ion incidence on the wafer affects sputtering yield and the resulting topography, hence substantially improving etching profiles of the etching target.
Accordingly, an IBE process can provide directional flexibility that is not available in other plasma processes. An IBE system can perform a directional etching process to create a feature (e.g., an opening) on a photoresist layer or a physical layer of a wafer, where the opening can have different lengths in different dimensions. For example, an IBE system can expand a square opening with a critical dimension (CD) to be larger in one dimension along an X-axis without changing a dimension along a Y-axis. As a result, the IBE process can compensate the extreme ultraviolet (EUV) lithography resolution limitation at small critical dimension patterning. While the etching rate with the IBE process is typically lower than the etching rate for a reactive ion etching (RIE) process, the IBE process can offer a high precision for applications that demand high dimension profile control. Also, the IBE process can be used to remove materials where an RIE process may not be successful. The IBE process can etch alloys and composite materials that are not compatible with an RIE process.
One of the challenges of the IBE process can be preventing asymmetry etching. When a wafer is placed within a process chamber of an IBE system with a tilted angle and/or rotated angle, different ion beams through the holes of the three-grid system have different incidence distances to the wafer. An incidence distance of an ion beam to the wafer is a distance from the source of the ion, or simply referred to as an ion source, to a location of the wafer, where the location is an incidence point of the ion beam on the surface of the wafer. Therefore, ions in different ion beams travel different incidence distances to reach the different locations of the wafer surface, resulting in different etching rates at different locations of the wafer surface. The etching rate at a first location of the tilted wafer by a first ion beam is lower when an incidence distance of the first ion beam is longer, while the etching rate at a second location of the tilted wafer by a second ion beam is higher when an incidence distance of the second ion beam is shorter. As a result, the etching amount at the first location is smaller than the etching amount at the second location, resulting in an asymmetry etching behavior for the IBE process. In general, the etching rate at a location of a tilted wafer surface is inversely proportional to an incidence distance of the corresponding ion beam incidence to the location. Rotation of the tilted wafer does not overcome the challenges of preventing asymmetry etching.
In an IBE system, the three-grid system includes a screen grid, an accelerator grid, and a decelerator grid to control the ion beams to strike the wafer. The screen grid, the accelerator grid, or the decelerator grid, includes multiple elements, such as multiple screen grid elements, multiple accelerator grid elements, and multiple decelerator grid elements. A screen grid element, an accelerator grid element, and a decelerator grid element together control a hole and an ion beam through the hole. All the screen grid elements are supplied by a same screen voltage, all the accelerator grid elements are supplied by a same accelerator voltage, and all the decelerator grid elements are supplied by a same decelerator voltage. Therefore, all the ion beams of the IBE systems are controlled by electric fields of the same energy. Under the same energy, when ions in two different ion beams go through two different incidence distances to reach two locations of the wafer surface, two different etching rates are resulted at the two locations.
The present disclosure provides example IBE systems that can generate substantially uniformly etching across different locations of a surface of a tilted wafer within the process chamber of the IBE systems. In some embodiments, the voltages supplied to the accelerator grid elements can be varied to control different ion beams. Instead of having a same voltage supplied to different accelerator grid elements, some embodiments have different voltages supplied to different accelerator grid elements. As a result, an accelerator grid element controlling an ion beam having a longer incidence distance can be supplied a voltage to create an electric field with a higher energy to transport the ions in the ion beam. Thus, the higher the energy in the electric field generated by the voltage, the longer the incidence distance the accelerator grid element can compensate, resulting in uniformly etching across a surface of a tilted wafer. Accordingly, the multiple voltages for multiple accelerator grid elements can balance all locations in the rotated tilted wafer with equal directional etching. As a result, embodiments herein reduce IBE asymmetry etching behavior. A tilted wafer has uniformly etching across different locations of a surface of the tilted wafer when an etching amount at a first location is substantially same as an etching amount at a second location, where the first location and the second location can be any location of the surface of the tilted wafer.
In some embodiments, holes of a three-grid system in the IBE system can be divided into multiple zones separated by an insulator. A first zone includes a first group of one or more holes controlled by a first group of one or more accelerator grid elements coupled to a first wire to receive a first voltage. Similarly, a second zone includes a second group of one or more holes controlled by a second group of one or more accelerator grid elements coupled to a second wire to receive a second voltage. The second voltage is different from the first voltage. As a result, the first group of one or more accelerator grid elements has an energy different from the second group of one or more accelerator grid elements to transport ions in ion beams through the first group of one or more holes. The voltage difference between the first voltage and the second voltage is determined so that the energy difference for controlling the ion beams compensates the difference of the incidence distances of the ion beams. Hence, the IBE asymmetry etching behavior can be reduced.
In some embodiments, as shown in
IBE system 100 can use an inert gas (e.g., argon or a noble gas) received from inlet 102 to generate ICP in plasma chamber 103. In addition, being electrically biased, three-grid system 150 can extract positively charged ions from the ICP and provide ions as ion beams through the multiple holes of three-grid system 150 to bombard wafer 154 to remove material from wafer 154. For example, argon ions can be extracted from an ICP source, accelerated and directed by three-grid system 150 to form mono-energetic beams, such as ion beam 141, ion beam 142, and ion beam 143 to etch any materials, such as piezoelectric and ferroelectrics, magnetics materials, group III-V elements of the periodic table (e.g., GaAs, InP, GaN, AlN . . . ), ohmic metals (e.g., Au, Pt, Cu, Ir . . . ), and hard mask materials (e.g., Ag, TiWN, Ni . . . ) on wafer 154. In some embodiments, IBE system 100 can have a wide range energy capability (from about 50 V to about 800 V) for low ion damage or for fast etch of various materials.
In some embodiments, plasma chamber 103, which can be an ICP source, can include a 350 mm diameter quartz vessel with a radio frequency (RF) plasma generator. An antenna (not shown) can be wrapped around the quartz vessel for inductive coupling. The antenna can operate at about 1.8 MHz and about 2 kW power. The oscillating current in the antenna at about 1.8 MHz can induce an electromagnetic field in the quartz vessel. During plasma ignition, some primary electrons can collect the electromagnetic field energy and agitate accordingly. Main plasma can be created inside the quartz vessel of plasma chamber 103 by inelastic collisions between hot electrons and neutrals (injected Argon gas) which generate ions/electrons pairs.
Three-grid system 150 can extract ions from plasma within plasma chamber 103, and accelerate the ions to build mono-energetic beams, e.g., ion beam 141, ion beam 142, ion beam 143 through multiple holes of three-grid system 150. This can be done by applying specific voltages to each grid of three-grid system 150, which will be shown in more details in
Mechanical shutter 105 can be placed downstream of three-grid system 150. When closed, process chamber 101 is protected and no etching takes place. This closed position allows for stabilization of the different parts such as plasma source, beam voltage, ions acceleration, and more. Mechanical shutter 105 is open when the whole system is stable (e.g. ions beam fully collimated and mon-energetic, substrate fixture correctly clamped and cooled-down, etc.) to ensure constant, precise, and repeatable processes.
Plasma bridge neutralizer (PBN) 106 is an electrons source placed downstream from three-grid system 150 to neutralize the charged ion beam. The electrons cannot back-stream into three-grid system 150 because of the negative decelerator-accelerator electric field. These electrons do not combine with the ions present in the beam, but they provide a charge balance for the ions in order to avoid space or surface charging on wafer 154.
Secondary ions mass spectrometer 108 can be used to monitor sputtered material species, allowing etching to be stopped at specific layers. When wafer 154 is bombarded by the ion beams, e.g., ion beam 141, ion beam 142, and/or ion beam 143, secondary ions can be ejected from the surface of wafer 154. These ejected secondary ions can be collected and a mass analyzer (quadrupole) can isolate them according to their mass in order to determine the elemental composition of the sputtered surface. A detection system (electron multiplier) can amplify and display the counts (magnitude) of the secondary ions in real time.
In addition, IBE system 100 can include other structural and functional components, such as RF generators, matching circuits, chamber liners, control circuits, actuators, power supplies, exhaust systems, etc. which are not shown for simplicity.
As shown in
Referring back to
Ions generated from the plasma within plasma chamber 103 go through the multiple holes to form multiple ion beams, e.g., ion beam 141 through hole 151, ion beam 142 through hole 152, ion beam 143 through hole 153, and more. The multiple ion beams perform directional etching on wafer 154. An ion beam through a hole is controlled by a combination of a screen grid element, an accelerator grid element, and a decelerator grid element. For example, ion beam 141 is controlled by screen grid element 111, accelerator grid element 121, and decelerator grid element 131. Similarly, ion beam 142 is controlled by screen grid element 112, accelerator grid element 122, and decelerator grid element 132. Ion beam 143 is controlled by screen grid element 113, accelerator grid element 123, and decelerator grid element 133.
Ion beam 141 reaches the surface of wafer 154 at an incidence point 155. Hence, ion beam 141 has an incidence distance D1 measured from the source of ion beam 141, or an ion source, to point 155. The source of ion beam 141 can be counted as the external edge of plasma chamber 103 where the ions are extracted from. Similarly, ion beam 142 has an incidence distance D2 measured from the source of ion beam 142 to an incidence point 156 of ion beam 142. Ion beam 143 has an incidence distance D3 measured from the source of ion beam 143 to an incidence point 157 of ion beam 143. The source of ion beam 141, the source of ion beam 142, and the source of ion beam 143, can be a same or parallel aligned. In some embodiments, the incidence distance D1, the incidence distance D2, and incidence distance D3, are different from each other.
Therefore, ions in different ion beams travel different incidence distances to reach the different locations of the wafer surface. The differences in the incidence distances of ion beams can result in different etching rates at different locations of the wafer surface. An etching rate at a point of wafer 154 can be a function of the energy of the ions reaching the point and the distance of the ions travel to reach the point, e.g., the incidence distance of the ion beam. In general, the etching rate at a location of a tilted wafer surface is near inversely proportional to an incidence distance of the corresponding ion beam incidence to the location. When all ion beams are supplied by the same energy, the etching rate of point 157 by ion beam 143 can be lower than the etching rate of point 156 by ion beam 142, since the incidence distance of ion beam 143 is longer than the incidence distance of ion beam 142. Rotation of the tilted wafer would not be able to solve the asymmetry etching behavior problem for the IBE process.
In some embodiments, accelerator grid element 121, accelerator grid element 122, and accelerator grid element 123 are supplied by different voltages to generate electric fields of different energies. Thus, compared to accelerator grid element 122, accelerator grid element 123 is supplied by the third voltage to generate an electric field of higher energy since ion beam 143 from hole 153 controlled by accelerator grid element 123 has longer incidence distance than ion beam 142 from hole 152 controlled by accelerator grid element 122. As a result, the etching rate at point 157 by ion beam 143 can be the same as the etching rate at point 156 by ion beam 142. Similarly, the etching rate at point 156 by ion beam 142 can be the same as the etching rate at point 155 by ion beam 141 when accelerator grid element 122 is supplied by the second voltage to generate an electric field of higher energy. Ion beam 142 from hole 152 controlled by accelerator grid element 122 has longer incidence distance than ion beam 141 from hole 151. As a result, by adjusting the different voltages supplied to the different accelerator grid elements to vary the energy of the electric field for the ion beams, an improved or close to uniformed distributed etching rate can be achieved for different points, e.g., point 155, point 156, and point 157.
In some embodiments, point 155, point 156, and point 157 can be located near the top edge, the middle, and the bottom edge of wafer 154 with about equal distance between them. Therefore, the first voltage supplied to accelerator grid element 121, the second voltage supplied to accelerator grid element 122, and the third voltage supplied to accelerator grid element 123, can have equal difference between them. For example, the first voltage can be about −200 volt, the second voltage can be about −240 volt, and the third voltage can be about −280 volt. In some embodiments, a difference between the first voltage and the second voltage is about 100 volt when the tilted angle θ of wafer 154 is between about 300 and about 600 degrees, the difference between the first voltage and the second voltage is about 400 volt when the tilted angle θ is between about 5° and about 300 degrees.
In some embodiments,
Referring back to
Table 1 below shows example voltages supplied to the screen grid, the decelerator grid, and the various accelerator grid elements in different zones. In addition, the supplied voltage can be impacted by the tilted angle θ of wafer 154. For example, when the tilted angle is 01, the accelerated voltage assigned to the accelerated elements in different zones can be about −200 V, about −240 V, about −280 V, and about −320 V. On the other hand, when the tilted angle is 02<01, the accelerated voltage assigned to the accelerated elements in different zones can be about −200 V, about −220 V, about −240 V, and about −260 V. The detailed voltage assignments can be determined based on experience and data set collected from etching wafer 154.
Referring to
FET 200 can be formed on a substrate 206. There may be other FETs and/or structures (e.g., isolation structures) formed on substrate 206. Substrate 206 can be a semiconductor material, such as silicon, germanium (Ge), silicon germanium (SiGe), a silicon-on-insulator (SOI) structure, and a combination thereof. In some embodiments, fin structure 208 can include a material similar to substrate 206 and extend along an X-axis.
Referring to
Referring to
In some embodiments, such dimensions of gate contact structure 232 can be formed using IBE system 100. The use of IBE system 100 to form gate contact structure 232 with different dimensions along X- and Y-axis can simplify the fabrication of gate contact structure 232 and improve its fabrication process control, as described below. In some embodiments, sidewalls of gate contact structure 232 formed using IBE system 100 can have different angles with the top surface and base of gate contact structure 232 along different planes. For example, the sidewalls of gate contact structure 232 extending along a ZY-plane can form angle A with the top surface and angle B with the base of gate contact structure 232, as shown in
Referring
The formation of gate contact opening 232* can be followed by the formation of gate contact opening 232**, as shown in
In some embodiments, similar to gate contact structures 232, S/D contact structures 230 can also be formed with different dimensions along X- and Y-axes using IBE system 100.
In some embodiments, to perform directional etching, wafer 154 is placed on a rotating fixture 107 in process chamber 101, which can be a vacuum chamber. A gas is introduced through inlet 102. The pressure of process chamber 101 can be reduced in a range from about 0.15 mT to about 0.2 mT. An RF plasma generator can be turned on and a plasma is struck (ignited) within the plasma chamber 103. Ions are extracted by screen grid 110, and further accelerated by accelerator grid 120 as they move toward the wafer to form ion beams, e.g., ion beam 141, ion beam 142, ion beam 143. Ions in the ion beams hit wafer 154, sputtering materials from the surface. The process continues until pattern is etched exposing the underlying layer for wafer 154. The high level description of the process is described below in more details in various operations.
In operation 305 of
In operation 310 of
In operation 315 of
In operation 320 of
In operation 325 of
In operation 330 of
In operation 335 of
In operation 340 of
In operation 345 of
In operation 350 of
Ions are extracted by screen grid 110, and further accelerated by accelerator grid 120 as they move toward the wafer to form ion beams, e.g., ion beam 141, ion beam 142, ion beam 143. Ion beam 141 moves through hole 151, ion beam 142 moves through hole 152, and ion beam 143 moves through hole 153. Ions in the ion beams hit wafer 154, sputtering materials from the surface. Ion beam 141 having the incidence distance D1 reaches the surface of wafer 154 at incidence point 155. Similarly, ion beam 142 having the incidence distance D2 reaches incidence point 156, and ion beam 143 having the incidence distance D3 reaches incidence point 157. Wafer 154 can have a feature 401 at incidence point 155, have a feature 402 at incidence point 156, and have a feature 403 at incidence point 157.
As shown in
As shown in
The present disclosure provides example three-grid system (e.g., three-grid system 150) in an IBE system (e.g., IBE system 100) for directional etching to prevent and/or mitigate the asymmetry etching behavior of a current IBE system. An IBE system with the example three-grid system can generate improved or close to uniformly distributed etching across different locations of a surface of a tilted wafer within the process chamber of the IBE system. The three-grid system includes a screen grid, an accelerator grid, and a decelerator grid to control the ion beams to strike the wafer. Instead of having a same accelerator voltage supplied to different accelerator grid elements, some embodiments have different voltages supplied to different accelerator grid elements. As a result, an accelerator grid element controlling an ion beam having a longer incidence distance can be supplied by a voltage to create an electric field with larger energy to transport the ions in the ion beam. Accordingly, the multiple accelerate grid voltages for multiple accelerate grid elements are able to balance all locations in the rotated tilted wafer with equal directional etching amounts. As a result, embodiments herein reduce IBE asymmetry etching behavior.
In some embodiments, a method for directional etching by an IBE system includes placing a wafer onto a rotating fixture within a process chamber of the IBE system, where the wafer has a tilted angle θ and a rotated angle of α. The method further includes setting up one or more directional etching process parameters of the IBE system. In addition, the method includes assigning a screen grid voltage to supply a screen grid included in a three-grid system to extract ions from plasma within a plasma chamber within the process chamber. The three-grid system includes the screen grid, an accelerator grid, and a decelerator grid with multiple holes including a first hole and a second hole through the screen grid, the accelerator grid, and the decelerator grid. Moreover, the method includes assigning a first voltage to supply a first accelerator grid element of the accelerator grid through a first wire, and assigning a second voltage different from the first voltage to supply a second accelerator grid element of the accelerator grid through a second wire. The first accelerator grid element controls a first ion beam through the first hole, while the second accelerator grid element controls a second ion beam through the second hole. The first ion beam has a first incidence distance to the wafer, and the second ion beam has a second incidence distance to the wafer different from the first incidence distance. In addition, the method includes performing directional etching of the wafer by multiple ion beams through the multiple holes including the first ion beam and the second ion beam.
In some embodiments, an IBE system includes a process chamber. The process chamber includes a plasma chamber configured to provide plasma. In addition, the process chamber includes a screen grid having multiple screen grid elements in contact with the plasma chamber, and an accelerator grid having multiple accelerator grid elements including a first accelerator grid element and a second accelerator grid element. The screen grid is supplied by a screen grid voltage to extract ions from the plasma within the plasma chamber. A first wire is coupled to the first accelerator grid element and configured to supply a first voltage to the first accelerator grid element. A second wire is coupled to the second accelerator grid element and configured to supply a second voltage to the second accelerator grid element, wherein the second voltage is different from the first voltage. Multiple holes including a first hole and a second hole through the screen grid and the accelerator grid are configured to provide multiple ion beams. The process chamber further includes a rotating fixture configured to hold a wafer having a tilted angle. A first ion beam through the first hole controlled by the first accelerator grid element has a first incidence distance to the wafer, and a second ion beam through the second hole controlled by the second accelerator grid element has a second incidence distance to the wafer. The second incidence distance is different from the first incidence distance. The first ion beam and the second ion beam perform directional etching on the wafer.
In some embodiments, a method for directional etching by an IBE system includes assigning a screen grid voltage to supply a screen grid included in a three-grid system to extract ions from plasma within a plasma chamber within a process chamber of the IBE system. The three-grid system includes the screen grid, an accelerator grid, and a decelerator grid with multiple holes including a first hole and a second hole through the screen grid, the accelerator grid, and the decelerator grid. Moreover, the method includes assigning a first voltage to supply a first accelerator grid element of the accelerator grid through a first wire, and assigning a second voltage different from the first voltage to supply a second accelerator grid element of the accelerator grid through a second wire. The first accelerator grid element controls a first ion beam through the first hole, while the second accelerator grid element controls a second ion beam through the second hole. The first ion beam has a first incidence distance to the wafer, and the second ion beam has a second incidence distance to the wafer different from the first incidence distance. In addition, the method includes performing a first phase of directional etching of the wafer by multiple ion beams through the multiple holes including the first ion beam and the second ion beam. Afterwards, the method includes rotating the wafer 180° to have a rotated angle of 180°+α degree while maintaining the tilted angle θ, and further performing a second phase directional etching of the wafer by the multiple ion beams.
The foregoing disclosure outlines features of several embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
