The present invention relates to a voltage protection device.
Electro-Static Discharge ESD and Electrical Over Stress EOS can both produce high transient electric fields that can result in damage, if not destruction, of an electronic circuit.
Consequently, to minimise the risk of ESD and EOS damage to an electronic circuit ESD and EOS protection is typically incorporated within the electronic circuit design. However, the use of ESD/EOS protection devices can result in an increase in size of the required silicon area of an electronic circuit by up to 10% to 30%.
One solution to this problem, as described in U.S. Pat. No. 6,211,544, has been the use of voltage variable material sandwiched between the contacts of an integrated circuit and a conducting rail.
Voltage variable material is designed to have a high electrical resistance value at low or normal operating voltages and currents but is arranged to switch to a low electrical resistance value in response to an essentially instantaneous change in voltage (e.g. at the start of an ESD and/or EOS transient).
Accordingly, on the occurrence of an ESD/EOS transient to an integrated circuit having voltage variable material sandwiched between the contacts of the integrated circuit and a conducting rail associated with the integrated circuit the voltage variable material goes low resistance allowing the ESD/EOS transient to be conducted away from the integrated circuit to the conducting rail.
However, the arrangement described in U.S. Pat. No. 6,211,544 only applies to a limited voltage range and requires the addition of one or more discrete voltage suppression devices, for example a diode, thyristor or transistor, to provide protection across a wider range of voltages It is desirable to improve this situation.
In accordance with a first aspect of the present invention there is provided a voltage protection device according to claim 1.
This provides the advantage of allowing ESD/EOS protection to be provided outside of a silicon die, thereby minimising the size of required silicon, while also providing protection over a wide range of ESD/EOS transient voltages.
In accordance with a second aspect of the present invention there is provided a method for manufacturing a voltage protection device according to claim 10.
An embodiment of the invention will now be described, by way of example, with reference to the drawings, of which:
The silicon part 11 is mounted on a lead frame 14 with each input/output pad 13 being coupled to appropriate input/output lines 15 with the appropriate input/output lines 15 additionally being connected to a respective element of voltage variable material 16 where each voltage variable element 16 is arranged to have different voltage variable characteristics, as described below. The respective voltage variable elements 16 are mounted on the lead frame 14 via a conductive element 17, where the conductive element 17 is connected to a ground rail or a positive/negative power supply rail (not shown).
At normal operating voltages (e.g. 3 V) the voltage variable materials of the voltage variable elements 16 exhibit a relatively high electrical resistance thereby ensuring that any voltage signals on the input/output lines 15 are conducted to the input/output pads 13 of the silicon area.
However, on application of an EOS or ESD transient voltage the voltage variable materials of the voltage variable elements 16 switch to a relatively low electrical resistance which causes the input/output lines 15 to be electrically connected to the conductive element 17. Consequently, the voltage variable elements 16 create a conductive path away from the silicon chip when an EOS or ESD transient voltage is applied to the silicon chip 11, thereby ensuring that the integrated circuit on the silicon chip 11 is protected from the harmful affects of the EOS or ESD transient energy.
The plurality of voltage variable elements 16 associated with the silicon die 12 are arranged to have different voltage variable characteristics such that the voltage at which each voltage variable element 16 switches to a relatively low electrical resistance is different, thereby providing voltage protection for a wide range of voltages.
U.S. Pat. No. 4,977,357 describes how the non-linear characteristics of voltage variable material is determined by the inter-particle spacing within the binder as well as by the electrical properties of the insulating binding.
To provide protection over the range of voltages covered by the different elements 16 all the input/output lines 15 to/from the input/output pads 13 are connected to each of the voltage variable elements 16. To ensure that a short circuit does not occur between the different input/output lines 15 the height between each connection should be different.
One technique for providing different voltage variable characteristics using the same material is to vary the thickness of the individual elements. For example, one well known technique for creating elements of ceramic material (e.g. ZnO), a well known voltage variable material, having different heights is to sinter or pile-up the ceramic material until the required height is obtained.
The ESD protection provided by the voltage variable material is defined by its static (DC) and dynamic (TLP) characteristics. As described below, the protection is provided by causing a short-circuit to occur for rapid changes in voltage, which could damage the circuit. The protection should be inactive during normal operating modes and arranged to be triggered for an electrical over voltage before the breakdown voltage of the protected devices is reached. As shown in
Alternatively, however, different types of voltage variable materials, having different voltage variable characteristics can by used, where the type of materials are selected to provide EOS/ESD protection over a required voltage range.
The voltage variable component 302 is mounted on a conductive element 306 such that the elements 303 of the voltage variable component 302 create a conductive path away from the silicon die 301 when an EOS or ESD transient voltage is applied to the silicon wafer 301, thereby ensuring that the integrated circuit on the silicon wafer 301 is protected from the harmful affects of the EOS or ESD transient energy.
It will be apparent to those skilled in the art that the disclosed subject matter may be modified in numerous ways and may assume may embodiments other than the preferred forms specifically set out as described above, for example any suitable type of voltage variable material could be used and any multi-level voltage variable component that provides voltage variable elements having different voltage variable characteristics could be used.
Number | Date | Country | Kind |
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03291609.0 | Jun 2003 | EP | regional |