This application claims priority to Japanese Patent Application No. 2004-283567, filed Sep. 29, 2004.
This invention relates to semiconductor wafers, and more specifically to those particularly well suited for use in making such compound semiconductor devices as light-emitting diodes (LEDs), high-electron-mobility transistors (HEMTs), and field-effect transistors (FETs). The invention also concerns a method of making such semiconductor wafers.
The wafer for the fabrication of nitride-based compound semiconductor devices, for example, consists of a sapphire, silicon carbide, or silicon substrate and, grown thereon by epitaxy, a lamination of semiconductor layers constituting the matrices of the desired devices. Japanese Unexamined Patent Publication No. 2003-59948 suggests use of a silicon substrate as a less expensive substitute for a sapphire or silicon carbide one. One of the problems encountered in use of a silicon substrate was a difference in linear expansion coefficient between the silicon substrate and the main semiconductor region of nitride-based chemical compounds grown thereon to provide the matrices of desired semiconductor devices to be made. Stressed as a result of this difference, the main semiconductor region was highly susceptible to such defects as cracks and dislocations.
In order to overcome this weakness of the silicon substrate, the noted Japanese patent application teaches a so-called buffer region of multilayered design through which the main semiconductor region is grown on the substrate. Itself incorporating dislocations, the multilayered buffer region mitigates stresses and so saves the overlying main semiconductor region from cracks and dislocations.
This solution has proved not totally satisfactory, however, as semiconductor makers today develop and use larger and larger wafers for reduction of the manufacturing costs. The silicon wafers having the main semiconductor region grown thereon via the buffer region become increasingly more susceptible to warpage as they become larger. Take, for instance, the silicon substrate wafers of two-inch diameter and those of five-inch diameter. The two-inch wafers have an average warpage of fifty micrometers whereas the five-inch wafers have that of one hundred micrometers. It has also proved that wafers warp more with an increase in the thickness of the semiconductor region grown thereon, despite the fact that thicker semiconductor regions enable the resulting devices to withstand higher voltages. Out-of-shape wafers must be avoided as far as possible since they impede such indispensable manufacturing processes of semiconductor devices as photolithography.
Another requirement that has been left not totally met in conjunction with silicon substrate wafers is the improvement of the crystallinity of the main semiconductor region. The crystallinity of the main semiconductor region depends much upon the buffer region. Difficulties have been experienced in growing relatively thick main semiconductor regions of good crystallinity on the buffer region of conventional make.
Before making this invention the present applicant tentatively made a buffer region explicitly designed for reduction of the warping of wafers. That tentative buffer region was in the form of alternating two different kinds of layers, consisting of first buffer layers each having several sublayers and second buffer layers having no sublayers. The lattice constant of the non-sublayered second buffer layers was made closer to that of one of the sublayers of each multi-sublayered first buffer layer that contained a relatively high proportion of aluminum, than to that of the main semiconductor region grown on this tentative buffer region. The stresses exerted by the non-sublayered second buffer layers on the main semiconductor region were opposite in direction to those exerted by the multi-sublayered first buffer layers thereon. Although this prior buffer configuration was expected to lessen the warping of the wafers significantly, it actually proved incapable of alleviating the stresses without sacrificing the crystallinity of the main semiconductor region.
The problems to be solved by the instant invention have been discussed hereinbefore as limited to the silicon substrate wafers. It is to be noted, however, that the same problems occur with substrates that are made from materials other than silicon but that are nearly as different in linear expansion coefficient from the nitride semiconductor region as the silicon substrate is.
The present invention has it as an object to reduce the warpage of the wafers for nitrides and other compound semiconductor devices to a minimum.
Another object of the invention is to improve the crystallinity of the main semiconductor region grown on a silicon or other substrate to provide matrices of desired semiconductor devices.
Briefly, the present invention concerns a wafer for fabrication of compound semiconductor devices, having a substrate, a buffer region formed on the substrate, and a main semiconductor region of compound semiconductors providing matrices of the semiconductor devices to be made. The invention particularly pertains to improvements in the configuration of the buffer region of the wafer. The improved buffer region comprises two or more alternations of first and second buffer layers. Each buffer layer has alternating first and second sublayers. The first sublayers of each first buffer layer are made from a nitride semiconductor containing a prescribed proportion of aluminum, and the second sublayers of each first buffer layer from a nitride semiconductor containing aluminum in a proportion that is either zero or less than the aluminum proportion of the first sublayers of the first buffer layers. The second buffer layers on the other hand are made from a nitride semiconductor containing aluminum in a proportion that is either zero or less than the aluminum proportion of the first sublayers of the first buffer layers. Each second buffer layer is thicker than each first or second sublayer of the first buffer layers and has a multiplicity of voids created therein.
Thus, in essence, the improved buffer region of this invention is comprised of alternating multi-sublayered first buffer layers and non-sublayered, open-worked second buffer layers. The two different kinds of buffer layers in combination attain the above stated objectives of wafer warpage reduction and the improvement of the crystallinity of the main semiconductor region formed thereon.
The invention also concerns a method of fabricating the wafer of the above summarized construction. All the constituent layers of the buffer region and the main semiconductor region thereon are successively formed by vapor-phase growth of nitride semiconductors on the substrate. Even the required voids in the second buffer layers are formed in the course of such vapor-phase growth of the successive layers, simply by, after the growth of each second buffer layer, introducing materials for the lowermost first sublayer of the next first buffer layer into the reactor at a rate low enough for the voids to be created by the etching action of the reactor atmosphere.
The above and other objects, features and advantages of this invention will become more apparent, and the invention itself will best be understood, from a study of the following description and appended claims, with reference had to the attached drawings showing some preferable embodiments of the invention.
The present invention will now be described more specifically as applied to a wafer or base plate for fabrication of high-electron-mobility heterojunction FETs (hereinafter referred to simply as transistors). Such a wafer is drawn schematically in
The main semiconductor region 4 is shown to have two semiconductor layers 5 and 6 of Groups III-V compound semiconductors for providing respectively the electron transit layer 5a,
AlaMbGa1-a-bN
where M is at least either of indium and boron; the subscript a is a numeral that is equal to or greater than zero and equal to or less than one; the subscript b is a numeral that is equal to or greater than zero and less than one; and the sum of a and b is equal to or less than one. Particularly preferred is undoped aluminum gallium nitride, AlGaN (the subscript b is zero in the formula above).
The second semiconductor layer 6 of the main semiconductor region 4 is made from any of the nitride semiconductors, plus an n-type impurity such as silicon, that are generally defined as:
AlxGa1-xN
where the subscriptx is a numeral that is greater than zero and less than one. Silicon-doped Al0.2Ga0.8N is particularly preferred.
The silicon substrate 2 is of p-type monocrystalline silicon, containing boron or other Group III elements as a conductivity type determinant. The major surface of the silicon substrate 2 on which is formed the buffer region 3 is exactly (111) in terms of Miller indices. The impurity concentration of the silicon substrate 2 is in the range of 1×1013 through 1×1014 cm−3, and its resistivity in the range of 100 to 1000 ohm-centimeters. The silicon substrate 2 should have a thickness Ts of 300 to 1000 micrometers, which is greater than the total thickness of the buffer region 3 and main semiconductor region 4, in order to serve the additional purpose of mechanically supporting these regions 3 and 4. The silicon substrate 2 could be of n-type.
As depicted fragmentarily and on an enlarged scale in
Speaking more broadly, the first buffer layers 9 may be from two to fifty in number, preferably from three to fifty, and most desirably from five to ten. The second buffer layers 10 may be from one to 49 in number, preferably from two to forty-nine, and most desirably from five to nine. Generally, the greater the numbers of pairs of first and second buffer layers 9 and 10, the better will they buffer the stresses due to the difference in linear expansion coefficient between the silicon substrate 2 and the nitride-based semiconductor region 4. The thickness Tb of the buffer region 3 may be from 70 to 3000 nanometers. The thickness of each first buffer layer 9 may be from 20 to 400 nanometers, preferably from 50 to 150 nanometers. The thickness of each second buffer layer 10 may be from 20 to 400 nanometers, preferably from 100 to 200 nanometers.
Generally speaking, the first sublayers L1 of each buffer layer 9 may be from three to fifth in number, preferably from five to twenty. The second sublayers L2 of each buffer layer 9 may be from two to forty-nine in number, preferably from four to nineteen.
The first sublayers L1 of the first buffer layers 9 are all made from an aluminum-containing nitride semiconductor selected from among the Groups III-V compound semiconductors that are generally defined as:
AlxMyGa1-x-yN
where M is at least either of indium and boron; the subscript x is a numeral that is greater than zero and equal to or less than one; the subscript y is a numeral that is equal to or greater than zero and less than one; and the sum of x and y is equal to or less than one. Specific examples meeting this formula are aluminum nitride (AlN), aluminum indium nitride (AlInN), aluminum gallium nitride (AlGaN), and aluminum indium aluminum nitride (AlInGaN). AlN is currently recommended. The thickness of each first sublayer L1 may be from 0.2 to 20 nanometers, preferably from one to seven nanometers, and most desirably from one to five nanometers. Made in this most desirable thickness range, the first sublayers L1 will offer the quantum-mechanical tunnel effect.
The second sublayers L2 of the first buffer layers 9 are all made from a nitride semiconductor that does not contain aluminum or that does contain aluminum in a proportion less than that of the first sublayers L1. The possible materials for the second sublayers L2 are the Groups III-V compound semiconductors that are generally expressed by the formula:
AlaMbGa1-a-bN
where M is at least either of indium and boron; the subscript a is a numeral that is equal to or greater than zero and less than one and, additionally, less than x in the formula above defining the materials for the first buffer sublayers L1; the subscript b is also a numeral that is equal to or greater than zero and less than one; and the sum of a and b is equal to or less than one. Thus the second buffer sublayers L2 can be made from such compounds as GaN, InGaN, AlInN, AlGaN, and AlInGaN, of which GaN is currently preferred. The thickness of each second sublayer L2 may be from 0.2 to 30.0 nanometers, preferably from two to twenty nanometers, and most desirably from three to ten nanometers.
The open-worked second buffer layers 10 of the buffer region 3 are also made from a nitride semiconductor that does not contain aluminum or that does contain aluminum in a proportion less than that of the first sublayers L1 of the first buffer layers 9. The possible materials for the second sublayers L2 are the Groups III-V compound semiconductors that are generally expressed by the formula:
AlaMbGa1-a-bN
where M is at least either of indium and boron; the subscript a is a numeral that is equal to or greater than zero and equal to or less than one and, additionally, less than x in the formula above defining the materials for the first buffer sublayers L1 of the first buffer layer 9; the subscript b is a numeral that is equal to or greater than zero and less than one; and the sum of a and b is equal to or less than one. Thus the second buffer layers 10 can also be made from such compounds as GaN, InGaN, AlInN, AlGaN, and AlInGaN, of which GaN is currently preferred. The thickness of each second buffer layer 10 may be from five to fifty, preferably from ten to forty, times the thickness of each second sublayer L2 of the first buffer layers 9.
As indicated greatly simplified and idealized in both
The idealized showing in
Still further, despite the showing of
The aforesaid pyramidal columns with the latticework of grooves of divergent cross section, in particular, have proved to serve most efficaciously the purpose of cutting short the transfer of dislocations. A possible explanation for this will be that upon extension of dislocations into each second buffer layer 10 from the underlying first buffer layer 9, the slanting walls of the voids 15 deflect and terminate such dislocations. Thus is the dislocation density of the main semiconductor region 4 particularly well reduced.
Despite the showing of
It is unnecessary, either, that the voids 15 be of constant width as in
The fabrication of the semiconductor wafer 1, configured as above described with reference to
The lowermost non-sublayered, open-worked second buffer layer 10 is created upon completion of the lowermost multi-sublayered first buffer layer 9. The same material as that of the second sublayers L2 of the first buffer layer 9 may be grown in the same MOVPE reactor for creation of the second buffer layer 10. However, the second buffer layers 10 may be made from a different material, such as InGaN, from that of the second sublayers L2 of the first buffer layer 9. The lowermost second buffer layer 10 thus grown on the lowermost first buffer layer 9 is not yet open-worked but is to be in the course of the ensuing fabrication of the lowest first sublayer L1 of the second lowest multi-sublayered first buffer layer 9.
Then comes the fabrication of that lowest first sublayer L1 of the second lowest multi-sublayered first buffer layer 9 following the creation of the not-yet-open-worked lowermost second buffer layer 10. The lowest first sublayer L1 of the second lowest first buffer layer 9 is grown on the not-yet-open-worked lowermost second buffer layer 10 by introducing TMA into the reactor at a reduced rate. As the lowest first sublayer L1 is thus grown at a reduced rate, there will be an initial phase of such growth in which AlN will crystallize sporadically, rather than uniformly, over the surface of the GaN second buffer layer 10. Those parts of the surface of the second buffer layer 10 which are left exposed by the sparse deposition of AlN will then be subjected to the etching action of the reactor atmosphere, with the consequent creation of the voids 15 in the second buffer layer.
For example, if AlN crystallizes in discrete islandlike regions, arranged more or less in columns and rows, on the surface of the second buffer layer 10, then the voids 15 will appear more or less in latticework. The open-worked second buffer layer 10 will then be constituted of a multiplicity of islandlike regions. If AlN crystallizes more or less in continuous, latticelike arrangement, on the other hand, then the voids 15 will be etched in the discrete parts of the surface of the second buffer layer 10 which are left uncovered by the latticed AlN deposit. The open-worked second buffer layer 10 will then be lattice-shaped.
Now has been formed the lowermost first sublayer L1 of the second lowest first buffer layer 9, with the concurrent creation of the voids 15 in the lowermost second buffer layer 10. The fabrication of the second lowest first buffer layer 9 may be continued by repeatedly and alternately creating the second buffer sublayers L2 and first buffer sublayers L1 by the same method as in the creation of the lowermost first buffer layer 9 explained above. The formation of the buffer region 3 comes to an end as the required number of pairs of the first and second buffer layers 9 and 10 are fabricated by the same method as the above-described lowermost pair of first and second buffer layers.
Next comes the growth of the main semiconductor region 4,
Then the wafer 1 is electroded for providing the transistors each constructed as in
The advantages gained by this particular wafer 1 may now be briefly studied. Constituted of alternating multi-sublayered first buffer layers 9 and open-worked, non-sublayered second buffer layers 10, the buffer region 3 according to the invention can better keep the wafer 1 from warping then heretofore. Generally, a wafer incorporating a conventional buffer region tends to warp as indicated by the broken line 13 in
The open-worked second buffer layers 10 in particular have a lattice constant that is closer to that of the main semiconductor region 4, particularly to that of the electron transit layer 5a, than to that of the first sublayers L1 of the first buffer layers 9. Consequently, the second buffer layers 10 tend to stress the main semiconductor region 4 in a direction opposite to that in which the first buffer layers 9 do. Thus the alternating first and second buffer layers 9 and 10 counteract each other to mitigate the transfer of stresses to the main semiconductor region 4. The stresses are particularly well dispersed by reason of the voids 15 in the second buffer layers 10.
It is a well known fact that that wafers must be as far free from warpage as possible (e.g., less than 40 micrometers in the case of a five-inch-diameter wafer) for execution of photolithographic and other manufacturing processes thereon as required. The wafers of this invention, fabricated by the method set forth above, with a five-inch diameter and having the main semiconductor region 4 formed to a thickness of 1.2 to 2.0 micrometers, had a warpage averaging fourteen micrometers in the direction indicated by the broken line 14 in
Additional advantages are as follows:
1. The open-worked second layers 10 of the buffer region 3 effectively terminate the dislocations that have occurred in the first layers 9 of the buffer region, with a consequent decrease in the dislocation density of the main semiconductor region 4. The dislocation density at the first major surface 11 of the main semiconductor region 4 was 5×108 cm−2, compared to that of 2×1010 cm−2 according to the noted prior art with the buffer region of AlN and GaN layers.
2. The surface roughness δ rms of the wafer 1 was less than 0.2 nanometer, a drastic improvement over that of 0.48 nanometer according to the same prior art.
3. Electron mobility at the electron transit layer 6a of the transistor 40 was 1600 cm2/Vs, much higher than 1200 cm2/Vs according to the same prior art.
4. The transistor 40, or any other semiconductor device made according to the invention, has proved to withstand a voltage of as high as 600 volts or more by making the thickness Tm of the main semiconductor region 4 not less than 1.2 micrometers.
5. The current leakage of the semiconductor device is reducible by making the main semiconductor region 4 as thick as 1.2 micrometers or more.
In
The silicon substrate 2a differs from its
Although the n-type buffer region 3′ is shown to be in direct contact with the p-type silicon substrate 2a, a voltage drop across the boundary between these regions is negligible when a forward bias voltage is impressed between anode 54 and cathode 55. This is because, first of all, the substrate 2a and buffer region 3′ are in heterojunction and secondly because a layer of an alloy, not shown, is invariably created between them. Alternatively, the silicon substrate 2a could be of n-type and be overlaid with the n-type buffer region 3′.
The main semiconductor region 4b comprises an n-type nitride semiconductor layer or lower cladding 51, an active layer 52, and a p-type nitride semiconductor region or upper cladding 53. These three layers constitute in combination the light-generating part of the LED 50. A more detailed description of the compositions of these light-generating layers 51-53 follows.
Grown epitaxially on the buffer region 3′, the n-type nitride semiconductor layer 51 is made by adding an n-type dopant to any of the nitride semiconductors that are generally defined by the formula:
AlxInyGa1-x-yN
where the subscripts x and y are both numerals that are equal to or greater than zero and less than one. Particularly preferred is n-type GaN (both x and y are zero in the formula above).
The active layer 52 is made from any of the undoped nitride semiconductors that are generally defined as:
AlxInyGa1-x-yN
where the subscripts x and y are both numerals that are equal to or greater than zero and less than one. Particularly preferred is InGaN (x is zero in the formula above). The active layer 52 may be of a single layer as shown or, preferably, of the known multiple quantum well configuration. Also, this layer 52 may be doped with a conductivity type determinant. It may be mentioned that the LED will generate light even without the active layer 52.
The p-type nitride semiconductor layer 53 is made by adding a p-type dopant to any of the nitride semiconductors that are generally defined as:
AlxInyGa1-x-yN
where the subscripts x and y are both numerals that are equal to or greater than zero and less than one. Particularly preferred is p-type GaN (both x and y are zero in the formula above).
Made up of the three layers 51-53 of the foregoing compositions, the main semiconductor region 4b is grown on the silicon substrate 2a via the buffer region 3′. The main semiconductor region 4b of the LED 50 is therefore just as favorable in crystallinity and flatness as the main semiconductor region 4a,
As shown also in
Incorporating the multilayered buffer region 3′ similar to its
Although the semiconductor wafer with the multilayered buffer region according to the present invention has been shown and described hereinbefore in terms of but two currently preferred forms, it is understood that the invention may be embodied in a variety of other forms within the usual knowledge of the semiconductor specialists. The following is a brief list of possible modifications, alterations and adaptations of the illustrated embodiments which are all believed to fall within the scope of the invention:
1. The invention is applicable to the fabrication of various semiconductor devices other than the exemplified heterojunction HEMTs and LEDs, such as bipolar transistors, insulated-gate field-effect transistors, rectifier diodes, and metal-semiconductor field-effect transistors.
2. The substrate can be made from materials other than silicon adoptable as long as they permit epitaxial growth of nitride semiconductors, examples being sapphire, silicon compound, zinc oxide, neodymium gallium oxide, and gallium arsenide.
3. The buffer region 3 or 3′ could be constituted of arbitrary numbers of first layers 9 and second layers 10. Normally, the number of the first layers 9 may be from two to fifth, and that of the second layers 10 from one to forty-nine.
4. The numbers of the sublayers L1 and L2 of each first buffer layer 9 are also variable as required or desired. Normally, the number of the first sublayers L1 of each first buffer layer may be from two to fifty, and that of the second sublayers L2 from one to forty-nine.
5. The multi-sublayered first layers 9 of the buffer region 3 or 3′ need not be all of the same make. For example, the second sublayers L2 of the first layers 9 may be made progressively thicker or thinner as they come closer to the main semiconductor region 4a or 4b. Or the numbers of the sublayers L1 and L2 in each first layer 9 may be made progressively more or less as it comes closer to the main semiconductor region 4a or 4b.
6. The open-worked second layers 10 of the buffer region 3 or 3′ need not be all of the same make, either. For example, they may be made progressively thicker or thinner as they come closer to the main semiconductor region 4a or 4b.
7. The voids 15 in the second buffer layers 10 of the buffer region 3 or 3′ may be created by masking and etching.
8. The wafer suggested by the instant invention may be made by various known methods besides the method proposed herein. One such known method is use of the so-called off-angled substrate having the step-like surface, on which the multi-sublayered first buffer layers 9 may be grown in fractional superlattice configuration. This method is called step-flow method.
9. All or some constituent layers of the buffer region 3 may be doped with, for example, an n-type impurity.
Number | Date | Country | Kind |
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2004-283567 | Sep 2004 | JP | national |