Erik L. Hedberg

Person

Essex Junction, VT, US

People

Patents Grantslast 30 patents

Information Patent Grant
Multiple manufacturing line qualification
- Patent number 9,536,796
- Issue date Jan 3, 2017
- Globalfoundries Inc.
- Jeanne P. Bickford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Systems and methods for semiconductor line scribe line centering
- Patent number 9,514,999
- Issue date Dec 6, 2016
- GLOBALFOUNDRIES Inc.
- Jeanne P. Bickford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor timing improvement
- Patent number 8,966,431
- Issue date Feb 24, 2015
- International Business Machines Corporation
- Jeanne P. Bickford
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Structure for implementing dynamic refresh protocols for DRAM based...
- Patent number 8,108,609
- Issue date Jan 31, 2012
- International Business Machines Corporation
- John E. Barth
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Method and system for implementing dynamic refresh protocols for DR...
- Patent number 8,024,513
- Issue date Sep 20, 2011
- International Business Machines Corporation
- John E. Barth, Jr.
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Laser fuse structures for high power applications
- Patent number 7,701,035
- Issue date Apr 20, 2010
- International Business Machines Corporation
- Stephen E. Greco
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Customizing back end of the line interconnects
- Patent number 7,300,825
- Issue date Nov 27, 2007
- International Business Machines Corporation
- Nancy Anne Greco
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming a voltage programming element
- Patent number 6,812,122
- Issue date Nov 2, 2004
- International Business Machines Corporation
- Claude L. Bertin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electronic fuse structure and method of manufacturing
- Patent number 6,633,055
- Issue date Oct 14, 2003
- International Business Machines Corporation
- Claude L. Bertin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for semiconductor integrated circuit testing a...
- Patent number 6,574,763
- Issue date Jun 3, 2003
- International Business Machines Corporation
- Claude L. Bertin
- G01 - MEASURING TESTING
Information Patent Grant
Electrical mask identification of memory modules
- Patent number 6,570,254
- Issue date May 27, 2003
- International Business Machines Corporation
- John B. DeForge
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Dynamically replacing a failed chip
- Patent number 6,567,950
- Issue date May 20, 2003
- International Business Machines Corporation
- Claude L. Bertin
- G11 - INFORMATION STORAGE
Information Patent Grant
High performance, low power vertical integrated CMOS devices
- Patent number 6,518,112
- Issue date Feb 11, 2003
- International Business Machines Corporation
- Michael D. Armacost
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structures for wafer level test and burn-in
- Patent number 6,426,904
- Issue date Jul 30, 2002
- International Business Machines Corporation
- John E. Barth
- G01 - MEASURING TESTING
Information Patent Grant
High performance direct coupled FET memory cell
- Patent number 6,426,530
- Issue date Jul 30, 2002
- International Business Machines Corporation
- Claude L. Bertin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Programmable latch device with integrated programmable element
- Patent number 6,420,925
- Issue date Jul 16, 2002
- International Business Machines Corporation
- John A. Fifield
- G11 - INFORMATION STORAGE
Information Patent Grant
Silicon anti-fuse structures, bulk and silicon on insulator fabrica...
- Patent number 6,396,120
- Issue date May 28, 2002
- International Business Machines Corporation
- Claude L Bertin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electrically programmable antifuses and methods for forming the same
- Patent number 6,388,305
- Issue date May 14, 2002
- International Business Machines Corporation
- Claude L. Bertin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High performance, low power vertical integrated CMOS devices
- Patent number 6,297,531
- Issue date Oct 2, 2001
- International Business Machines Corporation
- Michael D. Armacost
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electrical mask identification of memory modules
- Patent number 6,268,228
- Issue date Jul 31, 2001
- International Business Machines Corporation
- John B. DeForge
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Selective wafer-level testing and burn-in
- Patent number 6,255,208
- Issue date Jul 3, 2001
- International Business Machines Corporation
- William Emmett Bernier
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for increasing interchip communications rates
- Patent number 6,255,899
- Issue date Jul 3, 2001
- International Business Machines Corporation
- Claude L. Bertin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Impedance control using fuses
- Patent number 6,243,283
- Issue date Jun 5, 2001
- International Business Machines Corporation
- Claude Louis Bertin
- G11 - INFORMATION STORAGE
Information Patent Grant
Switched body SOI (silicon on insulator) circuits and fabrication m...
- Patent number 6,239,649
- Issue date May 29, 2001
- International Business Machines Corporation
- Claude Louis Bertin
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Structures for wafer level test and burn-in
- Patent number 6,233,184
- Issue date May 15, 2001
- International Business Machines Corporation
- John E. Barth
- G01 - MEASURING TESTING
Information Patent Grant
Chip thermal protection device
- Patent number 6,219,215
- Issue date Apr 17, 2001
- International Business Machines Corporation
- Claude Louis Bertin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High bandwidth DRAM with low operating power modes
- Patent number 6,178,517
- Issue date Jan 23, 2001
- International Business Machines Corporation
- Claude L. Bertin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High frequency valid data strobe
- Patent number 6,177,807
- Issue date Jan 23, 2001
- International Business Machines Corporation
- Claude L. Bertin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Impedance control using fuses
- Patent number 6,141,245
- Issue date Oct 31, 2000
- International Business Machines Corporation
- Claude Louis Bertin
- G11 - INFORMATION STORAGE
Information Patent Grant
High performance direct coupled FET memory cell
- Patent number 6,137,129
- Issue date Oct 24, 2000
- International Business Machines Corporation
- Claude L. Bertin
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
SYSTEMS AND METHODS FOR SEMICONDUCTOR LINE SCRIBE CENTERING
- Publication number 20140188265
- Publication date Jul 3, 2014
- International Business Machines Corporation
- Jeanne P. BICKFORD
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
In-Line Transistor Bandwidth Measurement
- Publication number 20140184242
- Publication date Jul 3, 2014
- International Business Machines Corporation
- Erik L. Hedberg
- G01 - MEASURING TESTING
Information Patent Application
MULTIPLE MANUFACTURING LINE QUALIFICATION
- Publication number 20140188266
- Publication date Jul 3, 2014
- International Business Machines Corporation
- Jeanne P. BICKFORD
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR TIMING IMPROVEMENT
- Publication number 20140143748
- Publication date May 22, 2014
- International Business Machines Corporation
- Jeanne P. BICKFORD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STRUCTURE FOR IMPLEMENTING DYNAMIC REFRESH PROTOCOLS FOR DRAM BASED...
- Publication number 20090144492
- Publication date Jun 4, 2009
- International Business Machines Corporation
- John E. Barth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR IMPLEMENTING REFRESHLESS SINGLE TRANSISTOR...
- Publication number 20090144507
- Publication date Jun 4, 2009
- International Business Machines Corporation
- John E. Barth, JR.
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STRUCTURE FOR IMPLEMENTING REFRESHLESS SINGLE TRANSISTOR CELL eDRAM...
- Publication number 20090144504
- Publication date Jun 4, 2009
- International Business Machines Corporation
- John E. Barth, JR.
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM FOR IMPLEMENTING DYNAMIC REFRESH PROTOCOLS FOR DR...
- Publication number 20090144506
- Publication date Jun 4, 2009
- John E. Barth, JR.
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LASER FUSE STRUCTURES FOR HIGH POWER APPLICATIONS
- Publication number 20070120232
- Publication date May 31, 2007
- International Business Machines Corporation
- Stephen E. Greco
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Customizing back end of the line interconnects
- Publication number 20050242442
- Publication date Nov 3, 2005
- Nancy Anne Greco
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Antifuses and methods for forming the same
- Publication number 20020093074
- Publication date Jul 18, 2002
- International Business Machines Corporation
- Claude L. Bertin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PROGRAMMABLE LATCH DEVICE WITH INTEGRATED PROGRAMMABLE ELEMENT
- Publication number 20020089363
- Publication date Jul 11, 2002
- International Business Machines Corporation, Armonk, NY 10504
- John A. Fifield
- G11 - INFORMATION STORAGE
Information Patent Application
ELECTRONIC FUSE STRUCTURE AND METHOD OF MANUFACTURING
- Publication number 20020011645
- Publication date Jan 31, 2002
- CLAUDE L. BERTIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
High performance, low power vertical integrated CMOS devices
- Publication number 20020008280
- Publication date Jan 24, 2002
- Michael D. Armacost
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Structures for wafer level test and burn -in
- Publication number 20010046168
- Publication date Nov 29, 2001
- John E. Barth
- G01 - MEASURING TESTING
Information Patent Application
HIGH PERFORMANCE, LOW POWER VERTICAL INTEGRATED CMOS DEVICES
- Publication number 20010002715
- Publication date Jun 7, 2001
- MICHAEL D. ARMACOST
- H01 - BASIC ELECTRIC ELEMENTS

Erik L. Hedberg

Person

Patents Grantslast 30 patents

Multiple manufacturing line qualification

Systems and methods for semiconductor line scribe line centering

Semiconductor timing improvement

Structure for implementing dynamic refresh protocols for DRAM based...

Method and system for implementing dynamic refresh protocols for DR...

Laser fuse structures for high power applications

Customizing back end of the line interconnects

Method for forming a voltage programming element

Electronic fuse structure and method of manufacturing

Method and apparatus for semiconductor integrated circuit testing a...

Electrical mask identification of memory modules

Dynamically replacing a failed chip

High performance, low power vertical integrated CMOS devices

Structures for wafer level test and burn-in

High performance direct coupled FET memory cell

Programmable latch device with integrated programmable element

Silicon anti-fuse structures, bulk and silicon on insulator fabrica...

Electrically programmable antifuses and methods for forming the same

High performance, low power vertical integrated CMOS devices

Electrical mask identification of memory modules

Selective wafer-level testing and burn-in

Method and apparatus for increasing interchip communications rates

Impedance control using fuses

Switched body SOI (silicon on insulator) circuits and fabrication m...

Structures for wafer level test and burn-in

Chip thermal protection device

High bandwidth DRAM with low operating power modes

High frequency valid data strobe

Impedance control using fuses

High performance direct coupled FET memory cell

Patents Applicationslast 30 patents

SYSTEMS AND METHODS FOR SEMICONDUCTOR LINE SCRIBE CENTERING

In-Line Transistor Bandwidth Measurement

MULTIPLE MANUFACTURING LINE QUALIFICATION

SEMICONDUCTOR TIMING IMPROVEMENT

STRUCTURE FOR IMPLEMENTING DYNAMIC REFRESH PROTOCOLS FOR DRAM BASED...

APPARATUS AND METHOD FOR IMPLEMENTING REFRESHLESS SINGLE TRANSISTOR...

STRUCTURE FOR IMPLEMENTING REFRESHLESS SINGLE TRANSISTOR CELL eDRAM...

METHOD AND SYSTEM FOR IMPLEMENTING DYNAMIC REFRESH PROTOCOLS FOR DR...

LASER FUSE STRUCTURES FOR HIGH POWER APPLICATIONS

Customizing back end of the line interconnects

Antifuses and methods for forming the same

PROGRAMMABLE LATCH DEVICE WITH INTEGRATED PROGRAMMABLE ELEMENT

ELECTRONIC FUSE STRUCTURE AND METHOD OF MANUFACTURING

High performance, low power vertical integrated CMOS devices

Structures for wafer level test and burn -in

HIGH PERFORMANCE, LOW POWER VERTICAL INTEGRATED CMOS DEVICES