Janet S. Y. Wang

Person

San Francisco, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method of programming a non-volatile memory cell using a baking pro...
- Patent number 6,618,290
- Issue date Sep 9, 2003
- Advanced Micro Devices, Inc.
- Janet S. Y. Wang
- G11 - INFORMATION STORAGE
Information Patent Grant
Higher program VT and faster programming rates based on improved er...
- Patent number 6,590,811
- Issue date Jul 8, 2003
- Advanced Micro Devices, Inc.
- Darlene G. Hamilton
- G11 - INFORMATION STORAGE
Information Patent Grant
Charge injection
- Patent number 6,567,303
- Issue date May 20, 2003
- Advanced Micro Devices, Inc.
- Darlene G. Hamilton
- G11 - INFORMATION STORAGE
Information Patent Grant
Simultaneous formation of charge storage and bitline to wordline is...
- Patent number 6,555,436
- Issue date Apr 29, 2003
- Advanced Micro Devices, Inc.
- Mark T. Ramsbey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Planar structure for non-volatile memory devices
- Patent number 6,541,816
- Issue date Apr 1, 2003
- Advanced Micro Devices, Inc.
- Mark T. Ramsbey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of erasing a non-volatile memory cell using a substrate bias
- Patent number 6,490,205
- Issue date Dec 3, 2002
- Advanced Micro Devices, Inc.
- Janet S. Y. Wang
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of simultaneous formation of bitline isolation and periphery...
- Patent number 6,468,865
- Issue date Oct 22, 2002
- Advanced Micro Devices, Inc.
- Jean Y. Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Simultaneous formation of charge storage and bitline to wordline is...
- Patent number 6,465,306
- Issue date Oct 15, 2002
- Advanced Micro Devices, Inc.
- Mark T. Ramsbey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of manufacturing spacer etch mask for silicon-oxide-nitride-...
- Patent number 6,465,303
- Issue date Oct 15, 2002
- Advanced Micro Devices, Inc.
- Mark T. Ramsbey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of programming a non-volatile memory cell using a drain bias
- Patent number 6,459,618
- Issue date Oct 1, 2002
- Advanced Micro Devices, Inc.
- Janet S. Y. Wang
- G11 - INFORMATION STORAGE
Information Patent Grant
Higher program VT and faster programming rates based on improved er...
- Patent number 6,456,533
- Issue date Sep 24, 2002
- Advanced Micro Devices, Inc.
- Darlene G. Hamilton
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of programming a non-volatile memory cell using a substrate...
- Patent number 6,456,536
- Issue date Sep 24, 2002
- Advanced Micro Devices, Inc.
- Daniel Sobek
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of drain avalanche programming of a non-volatile memory cell
- Patent number 6,456,531
- Issue date Sep 24, 2002
- Advanced Micro Devices, Inc.
- Janet S. Y. Wang
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and system for using a spacer to offset implant damage and r...
- Patent number 6,410,956
- Issue date Jun 25, 2002
- Advanced Micro Devices, Inc.
- Vei-Han Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Intelligent ramped gate and ramped drain erasure for non-volatile m...
- Patent number 6,331,953
- Issue date Dec 18, 2001
- Advanced Micro Devices
- Janet S. Y. Wang
- G11 - INFORMATION STORAGE
Information Patent Grant
Positive gate erasure for non-volatile memory cells
- Patent number 6,331,952
- Issue date Dec 18, 2001
- Advanced Micro Devices, Inc.
- Janet S. Y. Wang
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of programming a non-volatile memory cell using a current li...
- Patent number 6,269,023
- Issue date Jul 31, 2001
- Advanced Micro Devices, Inc.
- Narbeh Derhacobian
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of erasing non-volatile memory cells
- Patent number 6,266,281
- Issue date Jul 24, 2001
- Advanced Micro Devices, Inc.
- Narbeth Derhacobian
- G11 - INFORMATION STORAGE
Information Patent Grant
Self-limiting multi-level programming states
- Patent number 6,233,175
- Issue date May 15, 2001
- Advanced Micro Devices, Inc.
- Janet Wang
- G11 - INFORMATION STORAGE
Information Patent Grant
Flash EPROM cell with reduced short channel effect and method for p...
- Patent number 6,188,101
- Issue date Feb 13, 2001
- Advanced Micro Devices, Inc.
- Janet Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Ramped gate technique for soft programming to tighten the Vt distri...
- Patent number 6,172,909
- Issue date Jan 9, 2001
- Advanced Micro Devices, Inc.
- Sameer S. Haddad
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and system for using a spacer to offset implant damage and r...
- Patent number 6,025,240
- Issue date Feb 15, 2000
- Advanced Micro Devices, Inc.
- Vei-Han Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Non-uniform threshold voltage adjustment in flash eproms through ga...
- Patent number 5,888,867
- Issue date Mar 30, 1999
- Advanced Micro Devices, Inc.
- Janet Wang
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Method and Apparatus for Controlling Leakage in a Circuit
- Publication number 20090179664
- Publication date Jul 16, 2009
- Janet Wang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Simultaneous formation of charge storage and bitline to wordline is...
- Publication number 20020192910
- Publication date Dec 19, 2002
- Mark T. Ramsbey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGHER PROGRAM VT AND FASTER PROGRAMMING RATES BASED ON IMPROVED ER...
- Publication number 20020159293
- Publication date Oct 31, 2002
- Darlene G. Hamilton
- G11 - INFORMATION STORAGE
Information Patent Application
Planar structure for non-volatile memory devices
- Publication number 20020063277
- Publication date May 30, 2002
- Mark T. Ramsbey
- H01 - BASIC ELECTRIC ELEMENTS

Janet S. Y. Wang

Person

Patents Grantslast 30 patents

Method of programming a non-volatile memory cell using a baking pro...

Higher program VT and faster programming rates based on improved er...

Charge injection

Simultaneous formation of charge storage and bitline to wordline is...

Planar structure for non-volatile memory devices

Method of erasing a non-volatile memory cell using a substrate bias

Method of simultaneous formation of bitline isolation and periphery...

Simultaneous formation of charge storage and bitline to wordline is...

Method of manufacturing spacer etch mask for silicon-oxide-nitride-...

Method of programming a non-volatile memory cell using a drain bias

Higher program VT and faster programming rates based on improved er...

Method of programming a non-volatile memory cell using a substrate...

Method of drain avalanche programming of a non-volatile memory cell

Method and system for using a spacer to offset implant damage and r...

Intelligent ramped gate and ramped drain erasure for non-volatile m...

Positive gate erasure for non-volatile memory cells

Method of programming a non-volatile memory cell using a current li...

Method of erasing non-volatile memory cells

Self-limiting multi-level programming states

Flash EPROM cell with reduced short channel effect and method for p...

Ramped gate technique for soft programming to tighten the Vt distri...

Method and system for using a spacer to offset implant damage and r...

Non-uniform threshold voltage adjustment in flash eproms through ga...

Patents Applicationslast 30 patents

Method and Apparatus for Controlling Leakage in a Circuit

Simultaneous formation of charge storage and bitline to wordline is...

HIGHER PROGRAM VT AND FASTER PROGRAMMING RATES BASED ON IMPROVED ER...

Planar structure for non-volatile memory devices