Lawrence T. Clark

Person

Scottsdale, AZ, US

People

Patents Grantslast 30 patents

Information Patent Grant
Multi-mode radiation hardened multi-core microprocessors
- Patent number 10,579,536
- Issue date Mar 3, 2020
- Arizona Board of Regents on behalf of Arizona State University
- Lawrence T. Clark
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Digital circuits having improved transistors, and methods therefor
- Patent number 10,250,257
- Issue date Apr 2, 2019
- Mie Fujitsu Semiconductor Limited
- Scott E. Thompson
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Secure true random number generation using 1.5-T transistor flash m...
- Patent number 10,078,494
- Issue date Sep 18, 2018
- Arizona Board of Regents on behalf of Arizona State University
- Lawrence T. Clark
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Digital circuits having improved transistors, and methods therefor
- Patent number 9,985,631
- Issue date May 29, 2018
- MIE FUJITSU SEMICONDUCTOR LIMITED
- Scott E. Thompson
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Integrated circuit devices and methods
- Patent number 9,966,130
- Issue date May 8, 2018
- Mie Fujitsu Semiconductor Limited
- Lawrence T. Clark
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit device body bias circuits and methods
- Patent number 9,853,019
- Issue date Dec 26, 2017
- Mie Fujitsu Semiconductor Limited
- Lawrence T. Clark
- G05 - CONTROLLING REGULATING
Information Patent Grant
Digital circuits having improved transistors, and methods therefor
- Patent number 9,838,012
- Issue date Dec 5, 2017
- Mie Fujitsu Semiconductor Limited
- Scott E. Thompson
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Muller C-element as majority gate for self-correcting triple modula...
- Patent number 9,780,788
- Issue date Oct 3, 2017
- Arizona Board of Regents on behalf of Arizona State University
- Lawrence T. Clark
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Integrated circuit devices and methods
- Patent number 9,741,428
- Issue date Aug 22, 2017
- Mie Fujitsu Semiconductor Limited
- Lawrence T. Clark
- G11 - INFORMATION STORAGE
Information Patent Grant
Low complexity out-of-order issue logic using static circuits
- Patent number 9,740,494
- Issue date Aug 22, 2017
- Arizona Board of Regents for and on behalf of Arizona State University
- Lawrence T. Clark
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques for generating physical layouts of in silico multi mode...
- Patent number 9,734,272
- Issue date Aug 15, 2017
- Arizona Board of Regents on behalf of Arizona State University
- Lawrence T. Clark
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Digital circuits having improved transistors, and methods therefor
- Patent number 9,680,470
- Issue date Jun 13, 2017
- Mie Fujitsu Semiconductor Limited
- Scott E. Thompson
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Integrated circuit device body bias circuits and methods
- Patent number 9,548,086
- Issue date Jan 17, 2017
- Mie Fujitsu Semiconductor Limited
- Lawrence T. Clark
- G05 - CONTROLLING REGULATING
Information Patent Grant
Radiation hardened digital circuit
- Patent number 9,467,144
- Issue date Oct 11, 2016
- Arizona Board of Regents on behalf of Arizona State University
- Lawrence T. Clark
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dynamic random access memory (DRAM) with low variation transistor p...
- Patent number 9,431,068
- Issue date Aug 30, 2016
- Mie Fujitsu Semiconductor Limited
- Lawrence T. Clark
- G11 - INFORMATION STORAGE
Information Patent Grant
SRAM cell layout structure and devices therefrom
- Patent number 9,424,385
- Issue date Aug 23, 2016
- Mie Fujitsu Semiconductor Limited
- George Tien
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit devices and methods
- Patent number 9,362,291
- Issue date Jun 7, 2016
- Mie Fujitsu Semiconductor Limited
- Lawrence T. Clark
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuits and methods for measuring circuit elements in an integrate...
- Patent number 9,297,850
- Issue date Mar 29, 2016
- Mie Fujitsu Semiconductor Limited
- Lawrence T. Clark
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit process and bias monitors and related methods
- Patent number 9,276,561
- Issue date Mar 1, 2016
- Mie Fujitsu Semiconductor Limited
- Lawrence T. Clark
- G05 - CONTROLLING REGULATING
Information Patent Grant
Radiation hardened by design digital input/output circuits and rela...
- Patent number 9,191,009
- Issue date Nov 17, 2015
- Arizona Board of Regents, for and on behalf of Arizona State University
- Lawrence T. Clark
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Digital circuits having improved transistors, and methods therefor
- Patent number 9,184,750
- Issue date Nov 10, 2015
- Mie Fujitsu Semiconductor Limited
- Scott E. Thompson
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Longest prefix match internet protocol content addressable memories...
- Patent number 9,159,421
- Issue date Oct 13, 2015
- Arizona Board of Regents for and on behalf of Arizona State University
- Satendra Kumar Maurya
- G11 - INFORMATION STORAGE
Information Patent Grant
Body bias circuits and methods
- Patent number 9,154,123
- Issue date Oct 6, 2015
- Mie Fujitsu Semiconductor Limited
- Lawrence T. Clark
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Methods and apparatus to selectively power functional units
- Patent number 9,146,607
- Issue date Sep 29, 2015
- Marvell International Ltd.
- Dennis M. O'Connor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Porting a circuit design from a first semiconductor process to a se...
- Patent number 9,117,746
- Issue date Aug 25, 2015
- Mie Fujitsu Semiconductor Limited
- Lawrence T. Clark
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit process and bias monitors and related methods
- Patent number 9,112,484
- Issue date Aug 18, 2015
- Mie Fujitsu Semiconductor Limited
- Lawrence T. Clark
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Integrated circuit device body bias circuits and methods
- Patent number 9,112,495
- Issue date Aug 18, 2015
- Mie Fujitsu Semiconductor Limited
- Lawrence T. Clark
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Bit interleaved low voltage static random access memory (SRAM) and...
- Patent number 9,070,477
- Issue date Jun 30, 2015
- Mie Fujitsu Semiconductor Limited
- Lawrence T. Clark
- G11 - INFORMATION STORAGE
Information Patent Grant
Sequential state elements radiation hardened by design
- Patent number 9,054,688
- Issue date Jun 9, 2015
- Arizona Board of Regents, a body corporate of the State of Arizona, acting fo...
- Lawrence T. Clark
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Sequential state elements for triple-mode redundant state machines,...
- Patent number 9,041,429
- Issue date May 26, 2015
- Arizona Board of Regents, a body corporate of the State of Arizona, acting fo...
- Lawrence T. Clark
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
Digital Circuits Having Improved Transistors, and Methods Therefor
- Publication number 20180248548
- Publication date Aug 30, 2018
- MIE Fujitsu Semiconductor Limited
- Scott E. Thompson
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
MULTI-MODE RADIATION HARDENED MULTI-CORE MICROPROCESSORS
- Publication number 20180046580
- Publication date Feb 15, 2018
- Arizona Board of Regents on behalf of Arizona State University
- Lawrence T. Clark
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Digital Circuits Having Improved Transistors, and Methods Therefor
- Publication number 20180048311
- Publication date Feb 15, 2018
- Scott E. Thompson
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated Circuit Devices and Methods
- Publication number 20170301395
- Publication date Oct 19, 2017
- MIE Fujitsu Semiconductor Limited
- Lawrence T. Clark
- G11 - INFORMATION STORAGE
Information Patent Application
Digital Circuits Having Improved Transistors, and Methods Therefor
- Publication number 20170214404
- Publication date Jul 27, 2017
- MIE Fujitsu Semiconductor Limited
- Scott E. Thompson
- G11 - INFORMATION STORAGE
Information Patent Application
MULLER C-ELEMENT AS MAJORITY GATE FOR SELF-CORRECTING TRIPLE MODULA...
- Publication number 20170117895
- Publication date Apr 27, 2017
- Arizona Board of Regents on behalf of Arizona State University
- Lawrence T. Clark
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SECURE TRUE RANDOM NUMBER GENERATION USING 1.5-T TRANSISTOR FLASH M...
- Publication number 20170090873
- Publication date Mar 30, 2017
- Arizona Board of Regents on behalf of Arizona State University
- Lawrence T. Clark
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Integrated Circuit Device Body Boas Circuits and Methods
- Publication number 20170047100
- Publication date Feb 16, 2017
- MIE Fujitsu Semiconductor Limited
- Lawrence T. Clark
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Dram-Type Device With Low Variation Transistor Peripheral Circuits,...
- Publication number 20160336056
- Publication date Nov 17, 2016
- Mie Fujitsu Semiconduictor Limited
- Lawrence T. Clark
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated Circuit Devices and Methods
- Publication number 20160232964
- Publication date Aug 11, 2016
- MIE Fujitsu Semiconductor Limited
- Lawrence T. Clark
- G11 - INFORMATION STORAGE
Information Patent Application
RADIATION HARDENING ARCHITECTURAL EXTENSIONS FOR A RADIATION HARDEN...
- Publication number 20160065243
- Publication date Mar 3, 2016
- Arizona Board of Regents on behalf of Arizona State University
- Dan Wheeler Patterson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RADIATION HARDENED DIGITAL CIRCUIT
- Publication number 20160028397
- Publication date Jan 28, 2016
- Arizona Board of Regents on behalf of Arizona State University
- Lawrence T. Clark
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Digital Circuits Having Improved Transistors, and Methods Therefor
- Publication number 20160020768
- Publication date Jan 21, 2016
- MIE Fujitsu Semiconductor Limited
- Scott E. Thompson
- G11 - INFORMATION STORAGE
Information Patent Application
TECHNIQUES FOR GENERATING PHYSICAL LAYOUTS OF IN SILICO MULTI MODE...
- Publication number 20150363517
- Publication date Dec 17, 2015
- Arizona Board of Regents on behalf of Arizona State University
- Lawrence T. Clark
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Radiation Hardened By Design Digital Input/Output Circuits And Rela...
- Publication number 20150349775
- Publication date Dec 3, 2015
- Arizona Board of Regents, for and on behalf of Arizona State University
- Lawrence T. Clark
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated Circuit Process and Bias Monitors and Related Methods
- Publication number 20150333738
- Publication date Nov 19, 2015
- MIE Fujitsu Semiconductor Limited
- Lawrence T. Clark
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Integrated Circuit Device Body Bias Circuits and Methods
- Publication number 20150318026
- Publication date Nov 5, 2015
- MIE Fujitsu Semiconductor Limited
- Lawrence T. Clark
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ANALOG CIRCUITS HAVING IMPROVED TRANSISTORS, AND METHODS THEREFOR
- Publication number 20150015334
- Publication date Jan 15, 2015
- SUVOLTA, INC.
- Lawrence T. Clark
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SEQUENTIAL STATE ELEMENTS IN TRIPLE-MODE REDUNDANT (TMR) STATE MACH...
- Publication number 20140331197
- Publication date Nov 6, 2014
- Arizona Board of Regents on behalf of Arizona State University
- Lawrence T. Clark
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LONGEST PREFIX MATCH INTERNET PROTOCOL CONTENT ADDRESSABLE MEMORIES...
- Publication number 20140204644
- Publication date Jul 24, 2014
- Arizona Board of Regents for and on behalf of Arizona State University
- Satendra Kumar Maurya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DRAM-TYPE DEVICE WITH LOW VARIATION TRANSISTOR PERIPHERAL CIRCUITS,...
- Publication number 20140119099
- Publication date May 1, 2014
- SUVOLTA, INC.
- Lawrence T. Clark
- G11 - INFORMATION STORAGE
Information Patent Application
SEQUENTIAL STATE ELEMENTS RADIATION HARDENED BY DESIGN
- Publication number 20140077854
- Publication date Mar 20, 2014
- Arizona Board of Regents, a body corporated of the State of Arizona, acting f...
- Lawrence T. Clark
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEQUENTIAL STATE ELEMENTS FOR TRIPLE-MODE REDUNDANT STATE MACHINES,...
- Publication number 20140049286
- Publication date Feb 20, 2014
- Arizona Board of Regents, a body Corporate of the State of Arizona, Acting fo...
- Lawrence T. Clark
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ANALOG CIRCUITS HAVING IMPROVED TRANSISTORS, AND METHODS THEREFOR
- Publication number 20130154739
- Publication date Jun 20, 2013
- Lawrence T. Clark
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
FAST PARALLEL TEST OF SRAM ARRAYS
- Publication number 20130111282
- Publication date May 2, 2013
- Lawrence T. Clark
- G11 - INFORMATION STORAGE
Information Patent Application
CIRCUIT DEVICES AND METHODS HAVING ADJUSTABLE TRANSISTOR BODY BIAS
- Publication number 20120327725
- Publication date Dec 27, 2012
- SUVOLTA, INC.
- Lawrence T. Clark
- G11 - INFORMATION STORAGE
Information Patent Application
STRUCTURES AND METHODS FOR DESIGN AUTOMATION OF RADIATION HARDENED...
- Publication number 20120306535
- Publication date Dec 6, 2012
- Arizona Board of Regents for and on behalf of Arizona State University
- Lawrence T. Clark
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW COMPLEXITY OUT-OF-ORDER ISSUE LOGIC USING STATIC CIRCUITS
- Publication number 20120278593
- Publication date Nov 1, 2012
- ARIZONA TECHNOLOGY ENTERPRISES, LLC
- Lawrence T. Clark
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ANALOG CIRCUITS HAVING IMPROVED TRANSISTORS, AND METHODS THEREFOR
- Publication number 20120242409
- Publication date Sep 27, 2012
- Lawrence T. Clark
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SRAM CIRCUITS FOR CIRCUIT IDENTIFICATION USING A DIGITAL FINGERPRINT
- Publication number 20120230087
- Publication date Sep 13, 2012
- ARIZONA TECHNOLOGY ENTERPRISES, LLC
- Srivatsan Chellappa
- G11 - INFORMATION STORAGE

Lawrence T. Clark

Person

Patents Grantslast 30 patents

Multi-mode radiation hardened multi-core microprocessors

Digital circuits having improved transistors, and methods therefor

Secure true random number generation using 1.5-T transistor flash m...

Digital circuits having improved transistors, and methods therefor

Integrated circuit devices and methods

Integrated circuit device body bias circuits and methods

Digital circuits having improved transistors, and methods therefor

Muller C-element as majority gate for self-correcting triple modula...

Integrated circuit devices and methods

Low complexity out-of-order issue logic using static circuits

Techniques for generating physical layouts of in silico multi mode...

Digital circuits having improved transistors, and methods therefor

Integrated circuit device body bias circuits and methods

Radiation hardened digital circuit

Dynamic random access memory (DRAM) with low variation transistor p...

SRAM cell layout structure and devices therefrom

Integrated circuit devices and methods

Circuits and methods for measuring circuit elements in an integrate...

Integrated circuit process and bias monitors and related methods

Radiation hardened by design digital input/output circuits and rela...

Digital circuits having improved transistors, and methods therefor

Longest prefix match internet protocol content addressable memories...

Body bias circuits and methods

Methods and apparatus to selectively power functional units

Porting a circuit design from a first semiconductor process to a se...

Integrated circuit process and bias monitors and related methods

Integrated circuit device body bias circuits and methods

Bit interleaved low voltage static random access memory (SRAM) and...

Sequential state elements radiation hardened by design

Sequential state elements for triple-mode redundant state machines,...

Patents Applicationslast 30 patents

Digital Circuits Having Improved Transistors, and Methods Therefor

MULTI-MODE RADIATION HARDENED MULTI-CORE MICROPROCESSORS

Digital Circuits Having Improved Transistors, and Methods Therefor

Integrated Circuit Devices and Methods

Digital Circuits Having Improved Transistors, and Methods Therefor

MULLER C-ELEMENT AS MAJORITY GATE FOR SELF-CORRECTING TRIPLE MODULA...

SECURE TRUE RANDOM NUMBER GENERATION USING 1.5-T TRANSISTOR FLASH M...

Integrated Circuit Device Body Boas Circuits and Methods

Dram-Type Device With Low Variation Transistor Peripheral Circuits,...

Integrated Circuit Devices and Methods

RADIATION HARDENING ARCHITECTURAL EXTENSIONS FOR A RADIATION HARDEN...

RADIATION HARDENED DIGITAL CIRCUIT

Digital Circuits Having Improved Transistors, and Methods Therefor

TECHNIQUES FOR GENERATING PHYSICAL LAYOUTS OF IN SILICO MULTI MODE...

Radiation Hardened By Design Digital Input/Output Circuits And Rela...

Integrated Circuit Process and Bias Monitors and Related Methods

Integrated Circuit Device Body Bias Circuits and Methods

ANALOG CIRCUITS HAVING IMPROVED TRANSISTORS, AND METHODS THEREFOR

SEQUENTIAL STATE ELEMENTS IN TRIPLE-MODE REDUNDANT (TMR) STATE MACH...

LONGEST PREFIX MATCH INTERNET PROTOCOL CONTENT ADDRESSABLE MEMORIES...

DRAM-TYPE DEVICE WITH LOW VARIATION TRANSISTOR PERIPHERAL CIRCUITS,...

SEQUENTIAL STATE ELEMENTS RADIATION HARDENED BY DESIGN

SEQUENTIAL STATE ELEMENTS FOR TRIPLE-MODE REDUNDANT STATE MACHINES,...

ANALOG CIRCUITS HAVING IMPROVED TRANSISTORS, AND METHODS THEREFOR

FAST PARALLEL TEST OF SRAM ARRAYS

CIRCUIT DEVICES AND METHODS HAVING ADJUSTABLE TRANSISTOR BODY BIAS

STRUCTURES AND METHODS FOR DESIGN AUTOMATION OF RADIATION HARDENED...

LOW COMPLEXITY OUT-OF-ORDER ISSUE LOGIC USING STATIC CIRCUITS

ANALOG CIRCUITS HAVING IMPROVED TRANSISTORS, AND METHODS THEREFOR

SRAM CIRCUITS FOR CIRCUIT IDENTIFICATION USING A DIGITAL FINGERPRINT