Michael P. Duane

Person

Houston, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Semiconductor structure with multiple transistors having various th...
- Patent number 10,217,838
- Issue date Feb 26, 2019
- Mie Fujitsu Semiconductor Limited
- Dalong Zhao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor structure with multiple transistors having various th...
- Patent number 10,014,387
- Issue date Jul 3, 2018
- Mie Fujitsu Semiconductor Limited
- Dalong Zhao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor structure with multiple transistors having various th...
- Patent number 9,812,550
- Issue date Nov 7, 2017
- Mie Fujitsu Semiconductor Limited
- Dalong Zhao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
CMOS structures and processes based on selective thinning
- Patent number 9,391,076
- Issue date Jul 12, 2016
- Mie Fujitsu Semiconductor Limited
- Scott E. Thompson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating a transistor with reduced junction leakage c...
- Patent number 9,368,624
- Issue date Jun 14, 2016
- Mie Fujitsu Semiconductor Limited
- Scott E. Thompson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor structure with multiple transistors having various th...
- Patent number 9,299,698
- Issue date Mar 29, 2016
- Mie Fujitsu Semiconductor Limited
- Dalong Zhao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High uniformity screen and epitaxial layers for CMOS devices
- Patent number 9,196,727
- Issue date Nov 24, 2015
- Mie Fujitsu Semiconductor Limited
- Scott E. Thompson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Deeply depleted MOS transistors having a screening layer and method...
- Patent number 9,041,126
- Issue date May 26, 2015
- Mie Fujitsu Semiconductor Limited
- Thomas Hoffmann
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor structure with substitutional boron and method for fa...
- Patent number 8,999,861
- Issue date Apr 7, 2015
- SuVolta, Inc.
- Lance Scudder
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Transistor having reduced junction leakage and methods of forming t...
- Patent number 8,883,600
- Issue date Nov 11, 2014
- SuVolta, Inc.
- Scott E. Thompson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
CMOS structures and processes based on selective thinning
- Patent number 8,614,128
- Issue date Dec 24, 2013
- SuVolta, Inc.
- Scott E. Thompson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Double exposure patterning with carbonaceous hardmask
- Patent number 8,293,460
- Issue date Oct 23, 2012
- Applied Materials, Inc.
- Hui W. Chen
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Method and apparatus for characterizing features formed on a substrate
- Patent number 7,459,319
- Issue date Dec 2, 2008
- Applied Materials, Inc.
- Michael C. Smayling
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for characterizing features formed on a substrate
- Patent number 7,196,350
- Issue date Mar 27, 2007
- Applied Materials, Inc.
- Michael C. Smayling
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method for lowering miller capacitance for...
- Patent number 6,743,685
- Issue date Jun 1, 2004
- Advanced Micro Devices, Inc.
- David D. Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Channel isolation using dielectric isolation structures
- Patent number 6,727,558
- Issue date Apr 27, 2004
- Advanced Micro Devices, Inc.
- Michael P. Duane
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method for lowering miller capacitance by...
- Patent number 6,617,219
- Issue date Sep 9, 2003
- Advanced Micro Devices, Inc.
- Michael P. Duane
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Elevated transistor fabrication technique
- Patent number 6,420,730
- Issue date Jul 16, 2002
- Advanced Micro Devices, Inc.
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming low resistance gate electrode
- Patent number 6,376,350
- Issue date Apr 23, 2002
- Advanced Micro Devices, Inc.
- Michael P. Duane
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Merged sidewall spacer formed between series-connected MOSFETs for...
- Patent number 6,329,695
- Issue date Dec 11, 2001
- Advanced Micro Devices, Inc.
- Michael P. Duane
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Mutual implant region used for applying power/ground to a source of...
- Patent number 6,300,661
- Issue date Oct 9, 2001
- Advanced Micro Devices, Inc.
- Daniel Kadosh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Mask for asymmetrical transistor formation with paired transistors
- Patent number 6,200,862
- Issue date Mar 13, 2001
- Advanced Micro Devices, Inc.
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and structure for elevated source/drain with polished gate e...
- Patent number 6,140,190
- Issue date Oct 31, 2000
- Advanced Micro Devices
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Etch stop layer formed within a multi-layered gate conductor to pro...
- Patent number 6,111,298
- Issue date Aug 29, 2000
- Advanced Micro Devices, Inc.
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Asymmetrical transistor structure
- Patent number 6,104,064
- Issue date Aug 15, 2000
- Advanced Micro Devices, Inc.
- Daniel Kadosh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device having an elevated active region formed in an...
- Patent number 6,104,069
- Issue date Aug 15, 2000
- Advanced Micro Devices, Inc.
- Michael Duane
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device having reduced overlap capacitance and method...
- Patent number 6,091,118
- Issue date Jul 18, 2000
- Advanced Micro Devices, Inc.
- Michael Duane
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Advanced trench isolation fabrication scheme for precision polysili...
- Patent number 6,077,748
- Issue date Jun 20, 2000
- Advanced Micro Devices, Inc.
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Elevated transistor fabrication technique
- Patent number 6,075,258
- Issue date Jun 13, 2000
- Advanced Micro Devices, Inc.
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Transistor fabrication employing implantation of dopant into juncti...
- Patent number 6,069,046
- Issue date May 30, 2000
- Advanced Micro Devices, Inc.
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Semiconductor Structure With Multiple Transistors Having Various Th...
- Publication number 20180261683
- Publication date Sep 13, 2018
- MIE Fujitsu Semiconductor Limited
- Dalong Zhao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Structure with Multiple Transistors Having Various Th...
- Publication number 20170141209
- Publication date May 18, 2017
- MIE Fujitsu Semiconductor Limited
- Dalong Zhao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CMOS Structures and Processes Based on Selective Thinning
- Publication number 20160307907
- Publication date Oct 20, 2016
- MIE Fujitsu Semiconductor Limited
- Scott E. Thompson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Structure with Multiple Transistors Having Various Th...
- Publication number 20160163823
- Publication date Jun 9, 2016
- MIE Fujitsu Semiconductor Limited
- Dalong Zhao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
High Uniformity Screen and Epitaxial Layers for CMOS Devices
- Publication number 20150333144
- Publication date Nov 19, 2015
- MIE Fujitsu Semiconductor Limited
- Scott E. Thompson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH UNIFORMITY SCREEN AND EPITAXIAL LAYERS FOR CMOS DEVICES
- Publication number 20150061012
- Publication date Mar 5, 2015
- SUVOLTA, INC.
- Scott E. Thompson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEEPLY DEPLETED MOS TRANSISTORS HAVING A SCREENING LAYER AND METHOD...
- Publication number 20140084385
- Publication date Mar 27, 2014
- SUVOLTA, INC.
- Thomas Hoffmann
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR STRUCTURE WITH MULTIPLE TRANSISTORS HAVING VARIOUS TH...
- Publication number 20140001571
- Publication date Jan 2, 2014
- Dalong Zhao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DOUBLE EXPOSURE PATTERNING WITH CARBONACEOUS HARDMASK
- Publication number 20090311635
- Publication date Dec 17, 2009
- HUI W. CHEN
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
METHOD AND APPARATUS FOR CHARACTERIZING FEATURES FORMED ON A SUBSTRATE
- Publication number 20070145998
- Publication date Jun 28, 2007
- Michael C. Smayling
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated circuit layout methods
- Publication number 20070074142
- Publication date Mar 29, 2007
- APPLIED MATERIALS, INC.
- Michael C. Smayling
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
Method and apparatus for characterizing features formed on a substrate
- Publication number 20060255825
- Publication date Nov 16, 2006
- Michael C. Smayling
- H01 - BASIC ELECTRIC ELEMENTS

Michael P. Duane

Person

Patents Grantslast 30 patents

Semiconductor structure with multiple transistors having various th...

Semiconductor structure with multiple transistors having various th...

Semiconductor structure with multiple transistors having various th...

CMOS structures and processes based on selective thinning

Method for fabricating a transistor with reduced junction leakage c...

Semiconductor structure with multiple transistors having various th...

High uniformity screen and epitaxial layers for CMOS devices

Deeply depleted MOS transistors having a screening layer and method...

Semiconductor structure with substitutional boron and method for fa...

Transistor having reduced junction leakage and methods of forming t...

CMOS structures and processes based on selective thinning

Double exposure patterning with carbonaceous hardmask

Method and apparatus for characterizing features formed on a substrate

Method and apparatus for characterizing features formed on a substrate

Semiconductor device and method for lowering miller capacitance for...

Channel isolation using dielectric isolation structures

Semiconductor device and method for lowering miller capacitance by...

Elevated transistor fabrication technique

Method of forming low resistance gate electrode

Merged sidewall spacer formed between series-connected MOSFETs for...

Mutual implant region used for applying power/ground to a source of...

Mask for asymmetrical transistor formation with paired transistors

Method and structure for elevated source/drain with polished gate e...

Etch stop layer formed within a multi-layered gate conductor to pro...

Asymmetrical transistor structure

Semiconductor device having an elevated active region formed in an...

Semiconductor device having reduced overlap capacitance and method...

Advanced trench isolation fabrication scheme for precision polysili...

Elevated transistor fabrication technique

Transistor fabrication employing implantation of dopant into juncti...

Patents Applicationslast 30 patents

Semiconductor Structure With Multiple Transistors Having Various Th...

Semiconductor Structure with Multiple Transistors Having Various Th...

CMOS Structures and Processes Based on Selective Thinning

Semiconductor Structure with Multiple Transistors Having Various Th...

High Uniformity Screen and Epitaxial Layers for CMOS Devices

HIGH UNIFORMITY SCREEN AND EPITAXIAL LAYERS FOR CMOS DEVICES

DEEPLY DEPLETED MOS TRANSISTORS HAVING A SCREENING LAYER AND METHOD...

SEMICONDUCTOR STRUCTURE WITH MULTIPLE TRANSISTORS HAVING VARIOUS TH...

DOUBLE EXPOSURE PATTERNING WITH CARBONACEOUS HARDMASK

METHOD AND APPARATUS FOR CHARACTERIZING FEATURES FORMED ON A SUBSTRATE

Integrated circuit layout methods

Method and apparatus for characterizing features formed on a substrate