Richard S. Roy

Person

Dublin, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method for making a semiconductor device including threshold voltag...
- Patent number 10,191,105
- Issue date Jan 29, 2019
- ATOMERA INCORPORATED
- Richard Stephen Roy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dram architecture to reduce row activation circuitry power and peri...
- Patent number 10,109,342
- Issue date Oct 23, 2018
- ATOMERA INCORPORATED
- Richard Stephen Roy
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor device including threshold voltage measurement circuitry
- Patent number 10,107,854
- Issue date Oct 23, 2018
- ATOMERA INCORPORATED
- Richard Stephen Roy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit devices and methods
- Patent number 9,966,130
- Issue date May 8, 2018
- Mie Fujitsu Semiconductor Limited
- Lawrence T. Clark
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit devices and methods
- Patent number 9,741,428
- Issue date Aug 22, 2017
- Mie Fujitsu Semiconductor Limited
- Lawrence T. Clark
- G11 - INFORMATION STORAGE
Information Patent Grant
Transistor array structure
- Patent number 9,449,967
- Issue date Sep 20, 2016
- Fujitsu Semiconductor Limited
- Richard S. Roy
- G01 - MEASURING TESTING
Information Patent Grant
Dynamic random access memory (DRAM) with low variation transistor p...
- Patent number 9,431,068
- Issue date Aug 30, 2016
- Mie Fujitsu Semiconductor Limited
- Lawrence T. Clark
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit devices and methods
- Patent number 9,362,291
- Issue date Jun 7, 2016
- Mie Fujitsu Semiconductor Limited
- Lawrence T. Clark
- G11 - INFORMATION STORAGE
Information Patent Grant
High utilization multi-partitioned serial memory
- Patent number 9,342,471
- Issue date May 17, 2016
- MoSys, Inc.
- Michael J. Miller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuits and methods for measuring circuit elements in an integrate...
- Patent number 9,297,850
- Issue date Mar 29, 2016
- Mie Fujitsu Semiconductor Limited
- Lawrence T. Clark
- G11 - INFORMATION STORAGE
Information Patent Grant
Porting a circuit design from a first semiconductor process to a se...
- Patent number 9,117,746
- Issue date Aug 25, 2015
- Mie Fujitsu Semiconductor Limited
- Lawrence T. Clark
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Hierarchical multi-bank multi-port memory organization
- Patent number 9,030,894
- Issue date May 12, 2015
- MoSys, Inc.
- Richard S. Roy
- G11 - INFORMATION STORAGE
Information Patent Grant
Multiple VDD clock buffer
- Patent number 8,994,415
- Issue date Mar 31, 2015
- SuVolta, Inc.
- Richard S. Roy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Ring oscillator with NMOS or PMOS variation insensitivity
- Patent number 8,988,153
- Issue date Mar 24, 2015
- SuVolta, Inc.
- Richard S. Roy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Semiconductor chip layout
- Patent number 8,901,747
- Issue date Dec 2, 2014
- MoSys, Inc.
- Michael J. Miller
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor chip layout with staggered Tx and Tx data lines
- Patent number 8,890,332
- Issue date Nov 18, 2014
- MoSys, Inc.
- Michael J. Miller
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Circuits and methods for measuring circuit elements in an integrate...
- Patent number 8,837,230
- Issue date Sep 16, 2014
- SuVolta, Inc.
- Lawrence T Clark
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit devices and methods
- Patent number 8,811,068
- Issue date Aug 19, 2014
- SuVolta, Inc.
- Lawrence T. Clark
- G11 - INFORMATION STORAGE
Information Patent Grant
Porting a circuit design from a first semiconductor process to a se...
- Patent number 8,806,395
- Issue date Aug 12, 2014
- SuVolta, Inc.
- Lawrence T. Clark
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Separate pass gate controlled sense amplifier
- Patent number 8,681,574
- Issue date Mar 25, 2014
- MoSys, Inc.
- Richard S. Roy
- G11 - INFORMATION STORAGE
Information Patent Grant
Porting a circuit design from a first semiconductor process to a se...
- Patent number 8,645,878
- Issue date Feb 4, 2014
- SuVolta, Inc.
- Lawrence T. Clark
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuits and methods for measuring circuit elements in an integrate...
- Patent number 8,599,623
- Issue date Dec 3, 2013
- SuVolta, Inc.
- Lawrence T Clark
- G11 - INFORMATION STORAGE
Information Patent Grant
Hierarchical multi-bank multi-port memory organization
- Patent number 8,547,774
- Issue date Oct 1, 2013
- MoSys, Inc.
- Richard S. Roy
- G11 - INFORMATION STORAGE
Information Patent Grant
Hierarchical organization of large memory blocks
- Patent number 8,539,196
- Issue date Sep 17, 2013
- MoSys, Inc.
- Richard S. Roy
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods for accessing DRAM cells using separate bit line control
- Patent number 8,451,675
- Issue date May 28, 2013
- MoSys, Inc.
- Richard S. Roy
- G11 - INFORMATION STORAGE
Information Patent Grant
Multiple cycle memory write completion
- Patent number 8,446,755
- Issue date May 21, 2013
- MoSys, Inc.
- Richard S. Roy
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit package with segregated Tx and Rx data channels
- Patent number 8,368,217
- Issue date Feb 5, 2013
- MoSys, Inc.
- Michael J. Miller
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multiple cycle memory write completion
- Patent number 8,139,399
- Issue date Mar 20, 2012
- MoSys, Inc.
- Richard S. Roy
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Dynamic Random Access Memory System Including Single-Ended Sense Am...
- Publication number 20240221823
- Publication date Jul 4, 2024
- ATOMERA INCORPORATED
- Richard S. Roy
- G11 - INFORMATION STORAGE
Information Patent Application
Multi-Chip Memory System Including DRAM Chips With Integrated Compa...
- Publication number 20240164082
- Publication date May 16, 2024
- ATOMERA INCORPORATED
- Richard Stephen Roy
- G11 - INFORMATION STORAGE
Information Patent Application
DRAM SENSE AMPLIFIER ARCHITECTURE WITH REDUCED POWER CONSUMPTION AN...
- Publication number 20230363150
- Publication date Nov 9, 2023
- ATOMERA INCORPORATED
- Richard Stephen Roy
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD FOR MAKING A SEMICONDUCTOR DEVICE INCLUDING THRESHOLD VOLTAG...
- Publication number 20180052205
- Publication date Feb 22, 2018
- ATOMERA INCORPORATED
- Richard Stephen Roy
- G01 - MEASURING TESTING
Information Patent Application
SEMICONDUCTOR DEVICE INCLUDING THRESHOLD VOLTAGE MEASUREMENT CIRCUITRY
- Publication number 20180052196
- Publication date Feb 22, 2018
- ATOMERA INCORPORATED
- Richard Stephen Roy
- G01 - MEASURING TESTING
Information Patent Application
DRAM ARCHITECTURE TO REDUCE ROW ACTIVATION CIRCUITRY POWER AND PERI...
- Publication number 20170330609
- Publication date Nov 16, 2017
- ATOMERA INCORPORATED
- Richard Stephen Roy
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated Circuit Devices and Methods
- Publication number 20170301395
- Publication date Oct 19, 2017
- MIE Fujitsu Semiconductor Limited
- Lawrence T. Clark
- G11 - INFORMATION STORAGE
Information Patent Application
Dram-Type Device With Low Variation Transistor Peripheral Circuits,...
- Publication number 20160336056
- Publication date Nov 17, 2016
- Mie Fujitsu Semiconduictor Limited
- Lawrence T. Clark
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated Circuit Devices and Methods
- Publication number 20160232964
- Publication date Aug 11, 2016
- MIE Fujitsu Semiconductor Limited
- Lawrence T. Clark
- G11 - INFORMATION STORAGE
Information Patent Application
DRAM-TYPE DEVICE WITH LOW VARIATION TRANSISTOR PERIPHERAL CIRCUITS,...
- Publication number 20140119099
- Publication date May 1, 2014
- SUVOLTA, INC.
- Lawrence T. Clark
- G11 - INFORMATION STORAGE
Information Patent Application
Hierarchical Multi-Bank Multi-Port Memory Organization
- Publication number 20130336074
- Publication date Dec 19, 2013
- MoSys, Inc.
- Richard S. Roy
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR CHIP LAYOUT WITH STAGGERED TX AND TX DATA LINESS
- Publication number 20130313723
- Publication date Nov 28, 2013
- MoSys, Inc.
- Michael J. Miller
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGE WITH SEGREGATED TX AND RX DATA CHANNELS
- Publication number 20120267769
- Publication date Oct 25, 2012
- MoSys, Inc.
- Michael J. Miller
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Separate Pass Gate Controlled Sense Amplifier
- Publication number 20120250441
- Publication date Oct 4, 2012
- MoSys, Inc.
- Richard S. Roy
- G11 - INFORMATION STORAGE
Information Patent Application
Methods For Accessing DRAM Cells Using Separate Bit Line Control
- Publication number 20120250442
- Publication date Oct 4, 2012
- MoSys, Inc.
- Richard S. Roy
- G11 - INFORMATION STORAGE
Information Patent Application
Multiple Cycle Memory Write Completion
- Publication number 20120140581
- Publication date Jun 7, 2012
- MoSys, Inc.
- Richard S. Roy
- G11 - INFORMATION STORAGE
Information Patent Application
High Utilization Multi-Partitioned Serial Memory
- Publication number 20110191548
- Publication date Aug 4, 2011
- MOSYS, INC.
- Michael J. Miller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Hierarchical Multi-Bank Multi-Port Memory Organization
- Publication number 20110188335
- Publication date Aug 4, 2011
- MOSYS, INC.
- Richard S. Roy
- G11 - INFORMATION STORAGE
Information Patent Application
Hierarchical Organization Of Large Memory Blocks
- Publication number 20110191564
- Publication date Aug 4, 2011
- MOSYS, INC.
- Richard S. Roy
- G11 - INFORMATION STORAGE
Information Patent Application
Multiple Cycle Memory Write Completion
- Publication number 20110085398
- Publication date Apr 14, 2011
- MOSYS, INC.
- Richard S. Roy
- G11 - INFORMATION STORAGE

Richard S. Roy

Person

Patents Grantslast 30 patents

Method for making a semiconductor device including threshold voltag...

Dram architecture to reduce row activation circuitry power and peri...

Semiconductor device including threshold voltage measurement circuitry

Integrated circuit devices and methods

Integrated circuit devices and methods

Transistor array structure

Dynamic random access memory (DRAM) with low variation transistor p...

Integrated circuit devices and methods

High utilization multi-partitioned serial memory

Circuits and methods for measuring circuit elements in an integrate...

Porting a circuit design from a first semiconductor process to a se...

Hierarchical multi-bank multi-port memory organization

Multiple VDD clock buffer

Ring oscillator with NMOS or PMOS variation insensitivity

Semiconductor chip layout

Semiconductor chip layout with staggered Tx and Tx data lines

Circuits and methods for measuring circuit elements in an integrate...

Integrated circuit devices and methods

Porting a circuit design from a first semiconductor process to a se...

Separate pass gate controlled sense amplifier

Porting a circuit design from a first semiconductor process to a se...

Circuits and methods for measuring circuit elements in an integrate...

Hierarchical multi-bank multi-port memory organization

Hierarchical organization of large memory blocks

Methods for accessing DRAM cells using separate bit line control

Multiple cycle memory write completion

Integrated circuit package with segregated Tx and Rx data channels

Multiple cycle memory write completion

Patents Applicationslast 30 patents

Dynamic Random Access Memory System Including Single-Ended Sense Am...

Multi-Chip Memory System Including DRAM Chips With Integrated Compa...

DRAM SENSE AMPLIFIER ARCHITECTURE WITH REDUCED POWER CONSUMPTION AN...

METHOD FOR MAKING A SEMICONDUCTOR DEVICE INCLUDING THRESHOLD VOLTAG...

SEMICONDUCTOR DEVICE INCLUDING THRESHOLD VOLTAGE MEASUREMENT CIRCUITRY

DRAM ARCHITECTURE TO REDUCE ROW ACTIVATION CIRCUITRY POWER AND PERI...

Integrated Circuit Devices and Methods

Dram-Type Device With Low Variation Transistor Peripheral Circuits,...

Integrated Circuit Devices and Methods

DRAM-TYPE DEVICE WITH LOW VARIATION TRANSISTOR PERIPHERAL CIRCUITS,...

Hierarchical Multi-Bank Multi-Port Memory Organization

SEMICONDUCTOR CHIP LAYOUT WITH STAGGERED TX AND TX DATA LINESS

INTEGRATED CIRCUIT PACKAGE WITH SEGREGATED TX AND RX DATA CHANNELS

Separate Pass Gate Controlled Sense Amplifier

Methods For Accessing DRAM Cells Using Separate Bit Line Control

Multiple Cycle Memory Write Completion

High Utilization Multi-Partitioned Serial Memory

Hierarchical Multi-Bank Multi-Port Memory Organization

Hierarchical Organization Of Large Memory Blocks

Multiple Cycle Memory Write Completion