Srinivas T. Reddy

Person

Fremont, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Dynamic scan chain and method
- Patent number 10,977,404
- Issue date Apr 13, 2021
- Xilinx, Inc.
- Srinivas T. Reddy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
FPGA configuration bitstream protection using multiple keys
- Patent number 9,208,357
- Issue date Dec 8, 2015
- Altera Corporation
- Martin Langhammer
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
PLD architecture for flexible placement of IP function blocks
- Patent number 9,094,014
- Issue date Jul 28, 2015
- Altera Corporation
- Andy L. Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
FPGA configuration bitstream protection using multiple keys
- Patent number 8,826,038
- Issue date Sep 2, 2014
- Altera Corporation
- Martin Langhammer
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
PLD architecture for flexible placement of IP function blocks
- Patent number 8,732,646
- Issue date May 20, 2014
- Altera Corporation
- Andy L. Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
PLD architecture for flexible placement of IP function blocks
- Patent number 8,407,649
- Issue date Mar 26, 2013
- Altera Corporation
- Andy L. Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
FPGA configuration bitstream protection using multiple keys
- Patent number 8,209,545
- Issue date Jun 26, 2012
- Altera Corporation
- Martin Langhammer
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
PLD architecture for flexible placement of IP function blocks
- Patent number 8,201,129
- Issue date Jun 12, 2012
- Altera Corporation
- Andy L. Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Apparatus and methods for adjusting performance of programmable log...
- Patent number 8,198,914
- Issue date Jun 12, 2012
- Altera Corporation
- Andy L. Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Apparatus and methods for adjusting performance of programmable log...
- Patent number 7,936,184
- Issue date May 3, 2011
- Altera Corporation
- Andy L. Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
FPGA configuration bitstream protection using multiple keys
- Patent number 7,725,738
- Issue date May 25, 2010
- Altera Corporation
- Martin Langhammer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reducing false positives in configuration error detection for progr...
- Patent number 7,620,876
- Issue date Nov 17, 2009
- Altera Corporation
- David Lewis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
PLD architecture for flexible placement of IP function blocks
- Patent number 7,584,447
- Issue date Sep 1, 2009
- Altera Corporation
- Andy L. Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Multiplexing device including a hardwired multiplexer in a programm...
- Patent number 7,253,660
- Issue date Aug 7, 2007
- Altera Corporation
- Paul Leventis
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Multiple size memories in a programmable logic device
- Patent number 7,236,008
- Issue date Jun 26, 2007
- Altera Corporation
- Richard G. Cliff
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable clock network for distributing clock signals to and be...
- Patent number 7,228,451
- Issue date Jun 5, 2007
- Altera Corporation
- Triet Nguyen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple size memories in a programmable logic device
- Patent number 7,161,381
- Issue date Jan 9, 2007
- Altera Corporation
- Srinivas Reddy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Methods for designing PLD architectures for flexible placement of I...
- Patent number 7,058,920
- Issue date Jun 6, 2006
- Altera Corporation
- Andy L. Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Memory array operating as a shift register
- Patent number 7,051,153
- Issue date May 23, 2006
- Altera Corporation
- Yi-Wen Lin
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable clock network for distributing clock signals to and be...
- Patent number 6,996,736
- Issue date Feb 7, 2006
- Altera Corporation
- Triet Nguyen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Routing architecture for a programmable logic device
- Patent number 6,970,014
- Issue date Nov 29, 2005
- Altera Corporation
- David M. Lewis
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic device with circuitry for observing programmable...
- Patent number 6,897,678
- Issue date May 24, 2005
- Altera Corporation
- Ketan Zaveri
- G01 - MEASURING TESTING
Information Patent Grant
System and method for optimizing routing lines in a programmable lo...
- Patent number 6,895,570
- Issue date May 17, 2005
- Altera Corporation
- David M. Lewis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Tristate structures for programmable logic devices
- Patent number 6,882,177
- Issue date Apr 19, 2005
- Altera Corporation
- Srinivas Reddy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic device architectures with super-regions having l...
- Patent number 6,879,183
- Issue date Apr 12, 2005
- Altera Corporation
- David E. Jefferson
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Fast signal conductor networks for programmable logic devices
- Patent number 6,819,135
- Issue date Nov 16, 2004
- Altera Corporation
- Christopher F. Lane
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic array integrated circuit devices
- Patent number 6,815,981
- Issue date Nov 9, 2004
- Altera Corporation
- Richard G. Cliff
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic device with hierarchical interconnection resources
- Patent number 6,798,242
- Issue date Sep 28, 2004
- Altera Corporation
- Srinivas T. Reddy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Multiple size memories in a programmable logic device
- Patent number 6,720,796
- Issue date Apr 13, 2004
- Altera Corporation
- Srinivas Reddy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic with on-chip DLL or PLL to distribute clock
- Patent number 6,657,456
- Issue date Dec 2, 2003
- Altera Corporation
- David E. Jefferson
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
PLD ARCHITECTURE FOR FLEXIBLE PLACEMENT OF IP FUNCTION BLOCKS
- Publication number 20140210515
- Publication date Jul 31, 2014
- Altera Corporation
- Andy L. Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PLD ARCHITECTURE FOR FLEXIBLE PLACEMENT OF IP FUNCTION BLOCKS
- Publication number 20130214815
- Publication date Aug 22, 2013
- Altera Corporation
- Andy L. Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PLD ARCHITECTURE FOR FLEXIBLE PLACEMENT OF IP FUNCTION BLOCKS
- Publication number 20120217998
- Publication date Aug 30, 2012
- Altera Corporation
- Andy L. Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Apparatus and methods for adjusting performance of programmable log...
- Publication number 20110204919
- Publication date Aug 25, 2011
- Altera Corporation
- Andy L. Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PLD ARCHITECTURE FOR FLEXIBLE PLACEMENT OF IP FUNCTION BLOCKS
- Publication number 20090224800
- Publication date Sep 10, 2009
- Altera Corporation
- Andy L. Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Apparatus and methods for adjusting performance of programmable log...
- Publication number 20070200596
- Publication date Aug 30, 2007
- Andy L. Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Reducing false positives in configuration error detection for progr...
- Publication number 20070011578
- Publication date Jan 11, 2007
- Altera Corporation
- David Lewis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PLD architecture for flexible placement of IP functions blocks
- Publication number 20060033527
- Publication date Feb 16, 2006
- ALTERA CORPORATION, a corporation of Delaware
- Andy L. Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Fast signal conductor networks for programmable logic devices
- Publication number 20040075465
- Publication date Apr 22, 2004
- Christopher F. Lane
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PLD architecture for flexible placement of IP function blocks
- Publication number 20030237071
- Publication date Dec 25, 2003
- Andy L. Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Programmable logic device with hierarchical interconnection resources
- Publication number 20030201794
- Publication date Oct 30, 2003
- Altera Corporation
- Srinivas T. Reddy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Programmable logic array integrated circuit devices
- Publication number 20030128051
- Publication date Jul 10, 2003
- Richard G. Cliff
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Programmable logic device architectures with super-regions having l...
- Publication number 20030080778
- Publication date May 1, 2003
- Altera Corporation
- David E. Jefferson
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Programmable logic device with hierarchical interconnection resources
- Publication number 20030076130
- Publication date Apr 24, 2003
- Srinivas T. Reddy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Programmable logic device with circuitry for observing programmable...
- Publication number 20030033584
- Publication date Feb 13, 2003
- Altera Corporation
- Ketan Zaveri
- G01 - MEASURING TESTING
Information Patent Application
Programmable logic array integrated circuit devices
- Publication number 20030016053
- Publication date Jan 23, 2003
- Richard G. Cliff
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PLD architecture for flexible placement of IP function blocks
- Publication number 20020163356
- Publication date Nov 7, 2002
- Andy L. Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
System and method for asymmetric routing lines
- Publication number 20020166106
- Publication date Nov 7, 2002
- David M. Lewis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Programmable logic device architectures with super-regions having l...
- Publication number 20020084801
- Publication date Jul 4, 2002
- Altera Corporation
- David E. Jefferson
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Programmable logic device with hierarchical interconnection resources
- Publication number 20020041191
- Publication date Apr 11, 2002
- Altera Corporation
- Srinivas T. Reddy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Programmable logic array integrated circuit architectures
- Publication number 20010022519
- Publication date Sep 20, 2001
- Altera Corporation
- Richard G. Cliff
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Dual port programmable logic device variable depth and width memory...
- Publication number 20010015933
- Publication date Aug 23, 2001
- Altera Corporation
- Srinivas T. Reddy
- G11 - INFORMATION STORAGE
Information Patent Application
Redundancy circuitry for programmable logic devices with interleave...
- Publication number 20010006347
- Publication date Jul 5, 2001
- Altera Corporation
- David E. Jefferson
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Programmable logic device architectures
- Publication number 20010006348
- Publication date Jul 5, 2001
- Altera Corporation
- David E. Jefferson
- H03 - BASIC ELECTRONIC CIRCUITRY

Srinivas T. Reddy

Person

Patents Grantslast 30 patents

Dynamic scan chain and method

FPGA configuration bitstream protection using multiple keys

PLD architecture for flexible placement of IP function blocks

FPGA configuration bitstream protection using multiple keys

PLD architecture for flexible placement of IP function blocks

PLD architecture for flexible placement of IP function blocks

FPGA configuration bitstream protection using multiple keys

PLD architecture for flexible placement of IP function blocks

Apparatus and methods for adjusting performance of programmable log...

Apparatus and methods for adjusting performance of programmable log...

FPGA configuration bitstream protection using multiple keys

Reducing false positives in configuration error detection for progr...

PLD architecture for flexible placement of IP function blocks

Multiplexing device including a hardwired multiplexer in a programm...

Multiple size memories in a programmable logic device

Programmable clock network for distributing clock signals to and be...

Multiple size memories in a programmable logic device

Methods for designing PLD architectures for flexible placement of I...

Memory array operating as a shift register

Programmable clock network for distributing clock signals to and be...

Routing architecture for a programmable logic device

Programmable logic device with circuitry for observing programmable...

System and method for optimizing routing lines in a programmable lo...

Tristate structures for programmable logic devices

Programmable logic device architectures with super-regions having l...

Fast signal conductor networks for programmable logic devices

Programmable logic array integrated circuit devices

Programmable logic device with hierarchical interconnection resources

Multiple size memories in a programmable logic device

Programmable logic with on-chip DLL or PLL to distribute clock

Patents Applicationslast 30 patents

PLD ARCHITECTURE FOR FLEXIBLE PLACEMENT OF IP FUNCTION BLOCKS

PLD ARCHITECTURE FOR FLEXIBLE PLACEMENT OF IP FUNCTION BLOCKS

PLD ARCHITECTURE FOR FLEXIBLE PLACEMENT OF IP FUNCTION BLOCKS

Apparatus and methods for adjusting performance of programmable log...

PLD ARCHITECTURE FOR FLEXIBLE PLACEMENT OF IP FUNCTION BLOCKS

Apparatus and methods for adjusting performance of programmable log...

Reducing false positives in configuration error detection for progr...

PLD architecture for flexible placement of IP functions blocks

Fast signal conductor networks for programmable logic devices

PLD architecture for flexible placement of IP function blocks

Programmable logic device with hierarchical interconnection resources

Programmable logic array integrated circuit devices

Programmable logic device architectures with super-regions having l...

Programmable logic device with hierarchical interconnection resources

Programmable logic device with circuitry for observing programmable...

Programmable logic array integrated circuit devices

PLD architecture for flexible placement of IP function blocks

System and method for asymmetric routing lines

Programmable logic device architectures with super-regions having l...

Programmable logic device with hierarchical interconnection resources

Programmable logic array integrated circuit architectures

Dual port programmable logic device variable depth and width memory...

Redundancy circuitry for programmable logic devices with interleave...

Programmable logic device architectures