William M. Clark, Jr.

Person

Camarillo, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Cryptographic bus architecture for the prevention of differential p...
- Patent number 8,296,577
- Issue date Oct 23, 2012
- HRL Laboratories, LLC
- David B. Shu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Conductive channel pseudo block process and circuit to inhibit reve...
- Patent number 8,258,583
- Issue date Sep 4, 2012
- HRL Laboratories, LLC
- Lap-Wai Chow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable connection and isolation of active regions in an integ...
- Patent number 8,168,487
- Issue date May 1, 2012
- HRL Laboratories, LLC
- William M. Clark, Jr.
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Cryptographic architecture with random instruction masking to thwar...
- Patent number 8,065,532
- Issue date Nov 22, 2011
- HRL Laboratories, LLC
- David B. Shu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Symmetric non-intrusive and covert technique to render a transistor...
- Patent number 8,049,281
- Issue date Nov 1, 2011
- HRL Laboratories, LLC
- Lap-Wai Chow
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Cryptographic CPU architecture with random instruction masking to t...
- Patent number 7,949,883
- Issue date May 24, 2011
- HRL Laboratories, LLC
- David B. Shu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Symmetric non-intrusive and covert technique to render a transistor...
- Patent number 7,935,603
- Issue date May 3, 2011
- HRL Laboratories, LLC
- Lap-Wai Chow
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Conductive channel pseudo block process and circuit to inhibit reve...
- Patent number 7,888,213
- Issue date Feb 15, 2011
- HRL Laboratories, LLC
- Lap-Wai Chow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Covert transformation of transistor properties as a circuit protect...
- Patent number 7,541,266
- Issue date Jun 2, 2009
- HRL Laboratories, LLC
- Lap-Wai Chow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit modification using well implants
- Patent number 7,514,755
- Issue date Apr 7, 2009
- HRL Laboratories LLC
- Lap-Wai Chow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Use of silicon block process step to camouflage a false transistor
- Patent number 7,344,932
- Issue date Mar 18, 2008
- HRL Laboratories, LLC
- Lap-Wai Chow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuits protected against reverse engineering and metho...
- Patent number 7,294,935
- Issue date Nov 13, 2007
- HRL Laboratories, LLC
- Lap-Wai Chow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Symmetric non-intrusive and covert technique to render a transistor...
- Patent number 7,242,063
- Issue date Jul 10, 2007
- HRL Laboratories, LLC
- Lap-Wai Chow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Covert transformation of transistor properties as a circuit protect...
- Patent number 7,217,977
- Issue date May 15, 2007
- HRL Laboratories, LLC
- Lap-Wai Chow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Implanted hidden interconnections in a semiconductor device for pre...
- Patent number 7,166,515
- Issue date Jan 23, 2007
- HRL Laboratories, LLC
- William M. Clark, Jr.
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Conductive channel pseudo block process and circuit to inhibit reve...
- Patent number 7,049,667
- Issue date May 23, 2006
- HRL Laboratories, LLC
- Lap-Wai Chow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit with reverse engineering protection
- Patent number 7,008,873
- Issue date Mar 7, 2006
- HRL Laboratories, LLC
- Lap-Wai Chow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Use of silicon block process step to camouflage a false transistor
- Patent number 6,979,606
- Issue date Dec 27, 2005
- HRL Laboratories, LLC
- Lap-Wai Chow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory with a bit line block and/or a word line block for preventin...
- Patent number 6,940,764
- Issue date Sep 6, 2005
- HRL Laboratories LLC
- William M. Clark, Jr.
- G11 - INFORMATION STORAGE
Information Patent Grant
Multilayered integrated circuit with extraneous conductive traces
- Patent number 6,924,552
- Issue date Aug 2, 2005
- HRL Laboratories, LLC
- James P. Baukus
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Permanently on transistor implemented using a double polysilicon la...
- Patent number 6,919,600
- Issue date Jul 19, 2005
- HRL Laboratories, LLC
- James P. Baukus
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit with reverse engineering protection
- Patent number 6,897,535
- Issue date May 24, 2005
- HRL Laboratories, LLC
- Lap-Wai Chow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Programmable connector/isolator and double polysilicon layer CMOS p...
- Patent number 6,893,916
- Issue date May 17, 2005
- HRL Laboratories, LLC
- James P. Baukus
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Cryptographic Architecture with Instruction Masking and other Techn...
- Publication number 20120144205
- Publication date Jun 7, 2012
- HRL LABORATORIES, LLC
- David B. Shu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT MODIFICATION USING WELL IMPLANTS
- Publication number 20090170255
- Publication date Jul 2, 2009
- HRL LABORATORIES, LLC
- Lap-Wai Chow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Memory with a bit line block and/or a word line block for preventin...
- Publication number 20040047188
- Publication date Mar 11, 2004
- William M. Clark ,Jr
- G11 - INFORMATION STORAGE

William M. Clark, Jr.

Person

Patents Grantslast 30 patents

Cryptographic bus architecture for the prevention of differential p...

Conductive channel pseudo block process and circuit to inhibit reve...

Programmable connection and isolation of active regions in an integ...

Cryptographic architecture with random instruction masking to thwar...

Symmetric non-intrusive and covert technique to render a transistor...

Cryptographic CPU architecture with random instruction masking to t...

Symmetric non-intrusive and covert technique to render a transistor...

Conductive channel pseudo block process and circuit to inhibit reve...

Covert transformation of transistor properties as a circuit protect...

Integrated circuit modification using well implants

Use of silicon block process step to camouflage a false transistor

Integrated circuits protected against reverse engineering and metho...

Symmetric non-intrusive and covert technique to render a transistor...

Covert transformation of transistor properties as a circuit protect...

Implanted hidden interconnections in a semiconductor device for pre...

Conductive channel pseudo block process and circuit to inhibit reve...

Integrated circuit with reverse engineering protection

Use of silicon block process step to camouflage a false transistor

Memory with a bit line block and/or a word line block for preventin...

Multilayered integrated circuit with extraneous conductive traces

Permanently on transistor implemented using a double polysilicon la...

Integrated circuit with reverse engineering protection

Programmable connector/isolator and double polysilicon layer CMOS p...

Patents Applicationslast 30 patents

Cryptographic Architecture with Instruction Masking and other Techn...

INTEGRATED CIRCUIT MODIFICATION USING WELL IMPLANTS

Memory with a bit line block and/or a word line block for preventin...