3617822

Information

• Patent Grant
• 3617822

• References
• Source

• Patent Number

  3,617,822

• Date Filed

  Not available

• Date Issued

  Tuesday, November 2, 1971
  53 years ago

• CPC

  • H01L27/0826 - Combination of vertical complementary transistors
  • H01L21/00 - Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02381 - Silicon, silicon germanium, germanium
  • H01L21/02532 - Silicon, silicon germanium, germanium
  • H01L21/02579 - P-type
  • H01L21/0262 - Reduction or decomposition of gaseous compounds
  • H01L21/02639 - Preparation of substrate for selective deposition
  • H01L21/2205 - from the substrate during epitaxy
  • H01L21/74 - Making of localized buried regions
  • H01L21/761 - PN junctions
  • H01L21/763 - Polycristalline semiconductor regions
  • H01L27/0652 - Vertical bipolar transistor in combination with diodes, or capacitors, or resistors
  • H01L27/0658 - Vertical bipolar transistor in combination with resistors or capacitors
  • Y10S148/026 - Deposition thru hole in mask
  • Y10S148/037 - Diffusion-deposition
  • Y10S148/085 - Isolated-integrated
  • Y10S148/098 - Layer conversion
  • Y10S148/122 - Polycrystalline
  • Y10S148/151 - Simultaneous diffusion
  • Y10S438/969 - Simultaneous formation of monocrystalline and polycrystalline regions

• US Classifications

  • 257 - Active solid-state devices
  • 148 - Metal treatment
  • 438 - Semiconductor device manufacturing: process