Patent Application
20240389366
This application relates to the general field of Integrated Circuit (IC) devices and fabrication methods, and more particularly to multilayer or Three Dimensional Integrated Memory Circuit (3D-Memory) and Three Dimensional Integrated Logic Circuit (3D-Logic) devices and fabrication methods.
Over the past 40 years, there has been a dramatic increase in functionality and performance of Integrated Circuits (ICs). This has largely been due to the phenomenon of “scaling”, i.e., component sizes such as lateral and vertical dimensions within ICs have been reduced (“scaled”) with every successive generation of technology. There are two main classes of components in Complementary Metal Oxide Semiconductor (CMOS) ICs, namely transistors and wires. With “scaling”, transistor performance and density typically improve and this has contributed to the previously-mentioned increases in IC performance and functionality. However, wires (interconnects) that connect together transistors degrade in performance with “scaling”. The situation today is that wires dominate the performance, functionality and power consumption of ICs.
3D stacking of semiconductor devices or chips is one avenue to tackle the wire issues. By arranging transistors in 3 dimensions instead of 2 dimensions (as was the case in the 1990s), the transistors in ICs can be placed closer to each other. This reduces wire lengths and keeps wiring delay low and wire.
There are many techniques to construct 3D stacked integrated circuits or chips including:
Additionally the 3D technology according to some embodiments of the invention may enable some very innovative IC devices alternatives with reduced development costs, novel and simpler process flows, increased yield, and other illustrative benefits.
The invention relates to multilayer or Three Dimensional Integrated Circuit (3D IC) devices and fabrication methods. Important aspects of 3D IC are technologies that allow layer transfer. These technologies include technologies that support reuse of the donor wafer, and technologies that support fabrication of active devices on the transferred layer to be transferred with it.
In one aspect, a 3D semiconductor device, the device including: a first level; and a second level, where the first level includes single crystal silicon and a plurality of logic circuits, where the second level is disposed above the first level and includes a plurality of arrays of memory cells, where the single crystal silicon includes an area, and where the area is greater than 1,000 mm2.
In another aspect, a 3D semiconductor device, the device including: a first level; and a second level, where the first level includes single crystal silicon and a plurality of logic circuits, where the second level is disposed above the first level and includes a plurality of RF circuits, where the single crystal silicon includes an area, and where the area is greater than 1,000 mm2.
In another aspect, a 3D semiconductor device, the device including: a first level; and a second level, where the first level includes single crystal silicon and a plurality of logic circuits, where the second level is disposed above the first level and includes a plurality of transistors, where the single crystal silicon includes channels adapted for fluid cooling, where the single crystal silicon includes an area, and where the area is greater than 1,000 mm2.
In another aspect, a 3D semiconductor device, the device including: a first level; and a second level, wherein said first level comprises single crystal silicon and a plurality of logic circuits, wherein said plurality of logic circuits each comprise first transistors, wherein said second level is disposed above said first level and comprises a plurality of arrays of memory cells, said second level comprises a plurality of second transistors, wherein each of said memory cells comprises at least one of said second transistors, wherein said first level is bonded to said second level, wherein said bonded comprises regions of oxide to oxide bonds, wherein said bonded comprises regions of metal to metal bonds; and a thermal isolation layer disposed between said first level and said second level, wherein said thermal isolation layer provides a greater than 20° C. differential temperature between said first level and said second level during nominal operation of said device.
In another aspect, a 3D semiconductor device, the device including: a first level; and a second level, wherein said first level comprises single crystal silicon and a plurality of logic circuits, wherein said plurality of logic circuits each comprise first transistors, wherein said second level is disposed above said first level and comprises a plurality of arrays of memory cells, said second level comprises a plurality of second transistors, wherein each of said memory cells comprises at least one of said second transistors, wherein said first level is bonded to said second level, wherein said bonded comprises regions of oxide to oxide bonds, wherein said bonded comprises regions of metal to metal bonds, wherein said single crystal silicon comprises an area, and wherein said area is greater than 1,000 mm2.
In another aspect, a 3D semiconductor device, the device including: a first level; and a second level, wherein said first level comprises single crystal silicon and a plurality of logic circuits, wherein said plurality of logic circuits each comprise first transistors, wherein said second level is disposed above said first level and comprises a plurality of arrays of memory cells, wherein said second level comprises a plurality of second transistors, wherein each of said memory cells comprises at least one of said second transistors, wherein said first level is bonded to said second level, wherein said bonded comprises regions of oxide to oxide bonds, wherein said bonded comprises regions of metal to metal bonds, wherein said single crystal silicon comprises an area, and wherein said memory cells comprise Dynamic Random Access Memory (“DRAM”) cells.
In another aspect, an integrated semiconductor device, the device including: a first level; a second level, where the first level includes single crystal silicon and a plurality of logic circuits, where the plurality of logic circuits each include first transistors, where the second level is disposed above the first level and includes a plurality of arrays of first memory cells, where the second level includes a plurality of second transistors, where each of the first memory cells includes at least one of the second transistors, where the first level is bonded to the second level; an array of processors; and a third level, where the third level includes a plurality of third transistors, where the third level is disposed above the second level and includes a plurality of arrays of second memory cells, where each of the second memory cells includes at least one of the third transistors, where the device includes a substrate area, and where the area is greater than 1,000 mm2.
In another aspect, an integrated semiconductor device, the device including: a first level; a second level, where the first level includes single crystal silicon and a plurality of logic circuits, where the plurality of logic circuits each include first transistors, where the second level is disposed above the first level and includes a plurality of arrays of first memory cells, where the second level includes a plurality of second transistors, where each of the first memory cells includes at least one of the second transistors, where the first level is bonded to the second level; an array of processors; a third level, where the third level includes a plurality of third transistors, where the third level is disposed above the second level and includes a plurality of arrays of second memory cells, where each of the second memory cells includes at least one of the third transistors, where the device includes a substrate area; and a bonding structure, where the bonding structure includes regions of oxide-to-oxide bonds, and where the bonding structure includes regions of metal-to-metal bonds.
In another aspect, an integrated semiconductor device, the device including: a first level; a second level, where the first level includes single crystal silicon and a plurality of logic circuits, where the plurality of logic circuits each include first transistors, where the second level is disposed above the first level and includes a plurality of arrays of first memory cells, where the second level includes a plurality of second transistors, where each of the first memory cells includes at least one of the second transistors, where the first level is bonded to the second level; an array of processors; and a third level, where the third level includes a plurality of third transistors, where the third level is disposed above the second level and includes a plurality of arrays of second memory cells, and where each of the second memory cells includes at least one of the third transistors.
Various embodiments of the invention will be understood and appreciated more fully from at least the following detailed description, taken in conjunction with the drawings in which:
An embodiment of the invention is now described with reference to the drawing figures. Persons of ordinary skill in the art will appreciate that the description and figures illustrate rather than limit the invention and that in general the figures are not drawn to scale for clarity of presentation. Such skilled persons will also realize that many more embodiments are possible by applying the inventive principles contained herein and that such embodiments fall within the scope of the invention which is not to be limited except by any appended claims.
Some drawing figures may describe process flows for building devices. The process flows, which may be a sequence of steps for building a device, may have many structures, numerals and labels that may be common between two or more adjacent steps. In such cases, some labels, numerals and structures used for a certain step's figure may have been described in the previous steps' figures.
The use of layer transfer in the construction of a 3D IC based system could enable heterogeneous integration where each of strata may include one or more of MEMS sensor, image sensor, CMOS SoC, volatile memory such as DRAM and SRAM, persistent memory, and non-volatile memory such as flash and OTP. Such could include adding memory control circuits, also known as peripheral circuits, on top or below a memory array. The memory strata may contain only memory cells but not control logic, thus the control logic may be included on a separate stratum. Alternatively, the memory strata may contain memory cells and simple control logic where the control logic on that stratum may include at least one of decoder, buffer memory, sense amplifier. The circuits may include the charge pumps and high voltage transistors, which could be made on a strata using silicon transistors or other transistor types (such as SiGe, Ge, CNT, etc.) using a manufacturing process line that is different than the low voltage control circuit manufacturing process line. The analog circuits, such as for the sense amplifiers, and other sensitive linear circuits could also be processed independently and be transferred over to the 3D fabric. Such 3D construction could include “Smart Alignment” techniques presented in this invention or leverage the repeating nature of the memory array to reduce the impact of the wafer bonder misalignments on the effectiveness of the integration.
In patents such as, for example, U.S. patent application Ser. No. 15/173,395, layer transfer techniques called ELTRAN (epitaxial layer transfer) are presented and may be part of the formation process of a 3DIC. The ELTRAN technique utilizes an epitaxial process or processes over porous layers. Alternatively other epitaxial based structures could be formed to support layer transfer techniques by leveraging the etch selectivity of these epitaxial layers, such as the very high etch selectivity of SiGe vs. Silicon, and variations such as Silicon (single crystal or poly or amorphous), SiGe (mix of silicon and Germanium), P doped silicon, N doped silicon, etc. Alternately, these layer(s) could be combined with types of detachment processes, such as ‘cold splitting,’ for example the Siltectra stress polymer and low temperature shock treatment, to provide a thin layer transfer process.
Recently it become a very attractive concept for processing gate all around horizontal transistors and has become the target flow for next generation devices such as the 5 nm technology node. Some of the work in respect to selective etching of SiGe vs. silicon has been presented in a paper by Jang-Gn Yun et al. titled: “Single-Crystalline Si Stacked Array (STAR) NAND Flash Memory” published in IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 58, NO. 4, APRIL 2011, and a more recent work by K. Wostyn et al. titled “Selective Etch of Si and SiGe for Gate All-Around Device Architecture” published in ECS Transactions, 69 (8) 147-152 (2015), and by V. Destefanis et al. titled: “HCl Selective Etching of Si1−xGex versus Si for Silicon On Nothing and Multi Gate Devices” published in ECS Transactions, 16 (10) 427-438 (2008), all of the forgoing incorporated herein by reference. Since the SiGe over Si substrate process is becoming mature, this facilitates using a SiGe layer as a sacrificial layer for production worthy 3D layer transfer.
An exemplary layer transfer process could include the steps A-K, referencing the illustrations
A. As illustrated in
B. As illustrated in
C. As illustrated in
D. As illustrated in
E. As illustrated in
F. As illustrated in
G. As illustrated in
H. As illustrated in
I. The donor structure, substantially donor wafer-base substrate 202, may be detached from bonded structure 390 leaving intermediate 3D IC structure 399 as is illustrated in
J. The top surface 213 of intermediate 3D IC structure 399 may be cleaned and prepared for interconnections. Optionally cover with isolation.
K. TLVs may be formed for interconnection from the top to the bottom strata to form the 3DIC layer interconnects if necessary.
The donor wafer ‘tearing off’ detach could be assisted by known techniques such as, for example, water-jet, wedge, laser cutting, etched assisted tearing off and mechanical twist and pull.
Alternatively, additional interconnection layers and other processing could be added in between step ‘G’ and ‘H’ above. So, the structure illustrated in
The sacrificial layer removal holes 224 process could include side wall oxide deposition to further protect the side walls from the etch process designed to remove the sacrificial layers. These holes could be later sealed by a second step of, for example, oxide deposition. Such two steps oxide fill could be visible under proper magnification or other imaging techniques.
These layer transfer techniques could allow many of the benefits associated with monolithic 3D technologies including avoiding thermal budgets associated with forming one circuit strata affecting another circuit stratum, enabling mixing of technology nodes, mixing circuit substrate types, crystal structure, orientation and many other advantages associated with heterogeneous integration without process temperature restrictions described herein and in the incorporated art.
The use of SiGe for epitaxial based ‘cut layer’ instead of porous silicon or porous SiGe ‘cut layer’ could be adapted to many of the flows presented in at least U.S. application Ser. Nos. 14/642,724, 15/095,187, and 15/173,686, all the forgoing are incorporated herein by reference. It does add some complexity related to the holding posts formation and the holes to etch the SiGe thoroughly prior to performing the layer transfer. For applications in which two layers of active silicon, and isolation layer in between, is desired, the in-between SiGe could be removed after the transfer and replaced with isolation material.
Use of SiGe as a sacrificial layer for transferring a single crystal structure of one crystal on top of another structure has been presented in U.S. patent application 2015/0137187, incorporated herein by reference. Many studies of SiGe etch selectivity in respect to silicon have been done and published such as: In a work by T. Salvetat et al titled “Comparison between three Si1−xGex versus Si selective etching processes” presented at 214th ECS Meeting; and by M. Stoffel titled “SiGe wet chemical etchants with high compositional selectivity and low strain sensitivity” published in Semicond. Sci. Technol. 23 (2008) 085021; by V. Destefanis et al titled “High pressure in situ HCl etching of Si1−xGex versus Si for advanced devices” published in Semicond. Sci. Technol. 23 (2008) 105019; by T. K. Carns et al titled “Chemical Etching of Si,Ge in HF:H202:CH3COOH” published in J. Electrochem. Soc., Vol. 142, No. 4, April 1995; and by Marius Orlowski et al titled “Si, SiGe, Ge, and III-V Semiconductor Nanomembranes and Nanowires Enabled by SiGe Epitaxy” published at ECS Transactions, 33 (6) 777-789 (2010), all of the forgoing are incorporated herein by reference.
Another alternative is to skip steps related to
Alternatively, the ‘cut’ process could be integrated with Siltectra's ‘Cold Split’ technology as has been detailed in at least U.S. Pat. Nos. 8,440,129 and 8,877,077, and U.S. applications 20160064283, 20160086839, all of which are incorporated herein by reference. These techniques would allow reuse/recycling of the donor wafer (base substrate 202A middle location inside SiGe or the interface between Si and SiGe could be used to provide the “Pre-Defined Break Initiation Point” as an alternative to the Siltectra use of laser or in addition to it. The Siltectra's ‘Cold Split’ could reduce the need for the undercut etch and posts formation processing while providing reuse of the base substrate 202. For this technique, a multilevel SiGe could be designed to support the ‘cut’ on the one hand but also to reduce damage to the device layer on the other. This could be accomplished by increasing the Ge content in the interface with the base substrate 202 to have high Ge content such as over about 20% or over about 40% or even over about 80% and then on the side interfacing with device layer 206 forming a low Ge content such as less than about 20% or even less than about 10% to reduce stress to the silicon circuit layer 206. Alternatively, a few atomic layers thick Ge rich SiGe layer or even a pure Ge layer maybe used as a predefined break layer.
Once the base substrate 202 is removed, a selective etch could be used to remove the SiGe residues. Additional thinning processes such as etch and/or CMP could be used to further thin the back side of the device layer 206. Connection layers could be added included vias aligned to the target wafer 302 using “Smart Alignment” and similar 3D integration techniques discussed here and the incorporated by reference art.
This use of Cold Split could be used to form SOI wafers and could be less expensive to manufacture when compared to the current ion-cut methods.
A variation of flow in respect to
Another alternative is to use a similar flow to form a donor substrate which could support layer transfer as an alternative to an ELTRAN based donor wafer. This embodiment offers silicon on nothing structures anchored by post structures on the silicon ends. Then, the process follows using wafers with silicon on nothing. An exemplary donor wafer construction flow could include the steps A-F, referencing the illustrations in
A. As illustrated in
B. As illustrated in
C. As illustrated in
D. As illustrated in
E. As illustrated in
F. As is illustrated in
The donor wafer illustrated in
The silicon epitaxial layer 206/406 could be constructed from two layers such as first layer doped n+ followed by p− doped layer. Such double layer construction could allow smoothing of the surface 213 of the transferred layer after the transfer. Selective etch could etch the doped n+ layer leaving a smooth p− doped layer. Alternatively, the silicon epitaxial layer 206/406 could be made with three layers as is illustrated for example in
In U.S. patent application Ser. Nos. 15/095,187 and 15/173,686 incorporated herein by reference, ELTRAN base layer transfer techniques are shown being adapted to support die to wafer 3D IC construction. Some of the die-to-wafer flows suggest transfer of dies having a relatively greater thickness such as 6 microns or even 20 microns and further thinning these dies after being bonded to the target wafer. Such die thinning could leverage a multi layers die structure. As an example, a multilayer such as is illustrated in
All these multilayer structures could be formed during the epitaxial growth by adding materials as gases to the epitaxial growth chamber as well known in the art.
These variations could be used for donor wafer substrate formation as discussed in reference to
As been stated before, a buried SiGe layer could be used as an etch stop layer. Use of buried SiGe as an etch stop layer to transfer a crystalline layer on top of another wafer structure has been presented in U.S. Pat. Nos. 6,521,041, 6,689,211, 6,940,089, 7,348,259 and U.S. patent applications 2014/0342523, and in combination with ion cut in U.S. patent applications 2007/0023066, 2008/018959 all of the forgoing are incorporated herein by reference.
An additional alternative is to combine the porous formation technology of the ELTRAN based wafer transfer with the epitaxial ease of formation of silicon-SiGe technology base layer transfer presented herein. In U.S. Pat. Nos. 5,685,946 and 5,757,024 and in paper by Mondiali, V., et al. “Micro and nanofabrication of SiGe/Ge bridges and membranes by wet-anisotropic etching.” Microelectronic Engineering 141 (2015): 256-260, all incorporated herein by reference, SiGe is shown to be stain etched forming a porous layer with about 100 to 1 selectivity with respect to silicon. Using this selectivity could allow forming a ‘cuttable substrate’ from the structure of
The stain etch of a buried (Si or Ge or) SiGe layer converting it to porous layer could also be used when thermal isolation is required. Porous layers function well as a thermal isolation layer and oxidizing it could further add mechanical strength and further decrease its thermal mobility. Accordingly such a layer process could be useful in forming thermal isolation between the stratum of the 3D structure. So, for example, using SiGe as an etch stop could be followed by, instead of etching away the SiGe after grinding and etching of the silicon substrate, stain etching the SiGe converting it to a thermal isolation layer.
Converting the buried SiGe layer to porous layer by stain etching as presented above could leverage the STI etching step to use it as access to the buried SiGe layer or could include dedicated holes 224, 424, etching step. These access holes could be designed to provide access for effective conversion of the full buried SiGe layer underneath the die to SiGe. Such full buried SiGe conversion could be engineered based on the height of the buried SiGe layer the percent of Ge and other engineering aspects. As presented in U.S. Pat. Nos. 5,685,946 and 5,757,024 the side spread of the stain etching could extend to over 1 micron from the access holes. The engineering aspect of such full SiGe conversion could include Electronic Design Automation (“EDA”) to support the design process to place these holes throughout the die surface to provide sufficient access to full SiGe stain etching. Such EDA support could include adapting the macro-cell library to include access for very large structures, providing a holes adder utility to add holes in ‘white’ spaces area that do not need holes or STI for the active circuits, and adding modules to the Design Rule Checker (“DRC”) utilities. Similar type of EDA enhancements to support process modules, is common practice in the industry.
The layer transfer process could include two steps. First step could be performed at the frontend of the line of the process optionally as part of the STI process in which the SiGe layer is stain-etched converting it to a substantially porous layer. The second step could be performed just as before the layer transfer. In this second step, the porous-SiGe layer is selectively etched to make it ready for “cut”—detach. At that point the porous-SiGe could be selectively etched with extremely high selectivity. As discussed before, etching porous layer is about 5 orders of magnitude faster than etching the respective same material in full solid form. In addition the porous-SiGe is mostly Ge which could be extremely selective etched in respect to silicon. Accordingly the porous-SiGe could be etched with many orders of magnitude selectivity vs. silicon or other elements of the active circuits. In this case, the top silicon sidewall protection process described in
Additionally, a substrate 502 similar to one illustrated in
Alternatively, the substrate 502 could be made with perforations similar to as been described in U.S. Pat. No. 8,273,610, incorporated herein by reference, in respect to at least
Additional advantage of the techniques described herein is having the transferred circuit being an SOI circuit with its active silicon thickness to be fully depleted channel. The single crystalline silicon layer such as 530 could be made thin enough and being bonded over oxide and covered with oxide effectively could provide the SOI functionality and if made thinner such as 10 nm provides FD SOI functionality.
In a 3D system such as is illustrated in respect to at least
Formation of multiple levels of arrays of transistors or other transistor formations in the structures described herein may be described at least by the terms ‘multilevel device’ or ‘multilevel semiconductor device.’ Some examples of multilevel device may include memory device such as DRAM, SRAM, and Flash memory and image sensors such as CCD and CIS.
3D devices could include redundancy for defect recovery in addition to redundancy techniques know for 2D devices. Such 3D devices could include one-time-programmable memory for at least packaged level memory repair. Such redundancy techniques and structure has been presented in U.S. Pat. No. 8,395,191, incorporated herein by reference, in respect to at least
Additional variations of redundancy and repair techniques could be integrated within the 3D SRAM. 3D DRAM or 3D NOR fabric as detailed in PCT/US patent application 16/52726 and U.S. application Ser. No. 15/333,138 (now U.S. Pat. No. 10,014,318), incorporated herein by reference. Hereinafter, the use of 3D NOR fabric in any of embodiment in this invention may be 3D SRAM fabric or 3D DRAM fabric unless otherwise specified.
An additional inventive embodiment for such a 3D system as is illustrated in at least
Such heterogeneous 3D integration allows the use of one type of fabrication facility for one of the strata, for example, a memory oriented fabrication facility to produce the memory array 1130, and very different facility for a different stratum, for example, such as a logic orientated fabrication facility producing the memory control circuit 1154, thus allowing an increased flexibility in the design of the overall system including use of much more advance fabrication lines for some of the stratum.
Use of the alignment technique we call ‘Smart Alignment’ allows connection between the upper strata and the lower strata with vias (Through Layer Via—TLV) that are as small as the thickness of the layer and the process capabilities allow. Such is useful for connecting memory control circuits in one stratum to memory control lines such as bit-lines and word-lines on the other stratum.
Yet the target wafer 1164 in most cases of memory array would have at least two set of control lines one in X direction and one in Y direction. To allow effective connectivity the ‘Smart Alignment’ technique could be enhanced to have two sets of TLV. One TLV21 aligned to target wafer's alignment mark 1162 in Y direction and to the transferred layer's alignment mark 1166 in X direction. And the other TLV12 aligned to target wafer's alignment mark 1162 in X direction and to the transferred layer's alignment mark 1166 in Y direction. This may require two step of lithography.
An additional inventive embodiment relates to monolithic 3D by layer transfer whereby a unique structure may be formed by replacing silicon with high quality oxide prior to the layer transfer at the time that high temperatures processes are acceptable. For example, the silicon in the zone 1179 that is being designated for TLVs may be etched and filled in with high quality oxide (or a lower quality oxide deposition followed by a high temperature anneal) that would have leakage current of less than one picoamp per micron at a device power supply voltage of 1.5 and at a measurement temperature of 25° C. Thus, as well, the TLVs would not require any insulative lining to pass thru the TLV transiting layer, which could be islands/mesas of silicon in a sea of oxide, or vice versa.
An alternative to, two lithography steps with two via masks, could be the smart use of direct write eBeam in which the eBeam alignment could be managed to provide proper placement for the TLV12 and TLV21.
In some applications, it could be desired to transfer stratum including interconnection performing what could be called parallel integration instead of sequential integration. Bonding layer or die in such case could utilize hybrid bonding forming bonding and direct metal to metal connection in the process. In general, such hybrid bonding utilizes connection pads that are large enough to accommodate the bonding misalignment which in advanced bonder is approaching 100 nm worst case misalignment. Yet some memory stratum might use control line pitches which could not accommodate the bonder misalignment. An alternative for such cases could be use of bonding oxide that could be made to conduct by electrical signal, using what is known as One Time Programmable—“OTP” or Resistive RAM technologies. In such case one stratum could have some control signal and power signal connected using the hybrid bonding while the memory control lines could be connected by programming.
An additional inventive embodiment is an alternative for a 3D device-system; such a system as is illustrated in
An additional advantage in such a 3D memory system relates to the potential defects in semiconductor manufacturing. For example, the structure illustrated in
Moreover, a mix of redundancy techniques could be used. As such the multi-core multi-unit 3D system of
The system control function 1940 could include input output channels to other systems, or to a communication channel such as the internet or to wireless systems such as G4, G5. This could include such as fiber optic channel, free space optical channel, wireless channel and other forms of communication channels. The Monolithic 3D technology presented herein enables heterogeneous integration to enable those forms of communication.
The 3D architecture also could be useful to enable common manufacturing of a modular system that could be customized to specific needs by techniques presented herein, such as the use of each of a continuous structure as presented U.S. Pat. No. 8,994,404 as related to at least
An additional inventive embodiment is an additional aspect of a 3D computer system, such as is related to
Such prepared stratum may be bonded onto another target wafer and once the cut is performed the target strata is ready to have additional stratum bonded and connected onto it.
The process for removing the base silicon 2146 and the SiGe cut-layer 2148 could include use of grinding and selective etch as previously discussed. First selectively etch silicon using the SiGe layer 2148 for an etch stop, and then etching selectively the SiGe using the silicon 2122 and the pads 2132 as an etch stop. Alternatively the SiGe layer 2148 could be pre etched or mostly etched similar to the process in reference to
As an additional embodiment, the per layer select circuits could be made to either the bit lines (
An additional embodiment is to have two layers of select circuits for each control line as is illustrated in
Persons in the memory art could adapt these techniques in many variations to engineer 3D Computer systems with the desired memory size with consideration to process yield. Such could include, having first the logic stratum then the memory control and then overlaying the memory stack, or having the memory stack first as illustrated in
In the 3D Memory stack presented herein, the unit partition could be symmetrical in which the length of the wordlines within a unit is similar to the length of the bitlines, or the unit partition could be very asymmetrical. These control line length and accordingly the size of the respective unit size in X direction or in Y direction could be about 50,100,200, 400 micron or even one or few millimeters. The number of connections associated with these control lines is order of magnitudes larger than the number of vertical connections associated with the access control, the per layer select (SLi). In some applications the control could be broken into a few banks, each with its own select line allowing more control flexibility to individual memory banks within the unit. Such could allow better granularity for redundancy use or parallel access to the unit memory array. These banks could be allocated horizontally (X, Y) or vertically (Z). Such could also be used for parallel access from logic overlaying and or logic underlying the array. Such could also allow for sections of the memory array to be mapped for global access across multiple units. Such variation and the support control logic to support them are known in the art and could be designed by an artisan in computer architecture and memory controls.
An additional alternative is to integrate in such 3D computing structure active cooling. Such active cooling work was recently supported by DARPA and the report on these techniques is presented in a paper by Chainer, Timothy J., et al. “Improving Data Center Energy Efficiency With Advanced Thermal Management.” IEEE Transactions on Components, Packaging and Manufacturing Technology (2017), incorporated herein by reference. Such active cooling could be incorporated in addition or as replacement of the thermal isolations 2426, 2434.
Herein the term layer transfer or layer cut could be applied to use of SiGe as a cut layer either as sacrificial layer with far different etch rate vs. silicon as presented such as in reference to
Additionally, alternative structures to SiGe could be used for the formation of the ‘cut layer’. In some embodiments, the ‘cut layer’ may also function as an etch stop layer or sacrificial layer which could be selectively removed. Such alternatives have been detailed in PCT/US patent application 16/52726 and U.S. application Ser. No. 15/333,138 (now U.S. Pat. No. 10,014,318), incorporated herein by reference. For example, one may use a highly doped layer of N+ or P+ or porous layers. A unique advantage of a doped layer used as ‘cut layer’ is the ability to make it at the processing fab as part of the conventional process flow via conventional processes such as ion implantation or in-situ doped epitaxial growth. Another aspect is the ease to make the ‘cut layer’ selectively using patterning which opens up more options; for example, instead of a full layer or to allow change in the layer thickness in different location across the wafer. The use of a doped layer as a ‘cut layer’ could be combined with other functions, such as a back bias connection for transistors or other devices. The choice of ‘cut’ between undercut and lift off or grind and etch back could be in consideration of the type of etch and its selectivity in respect to choice of the ‘cut layer’ structure.
Many other variations of 3D system could be constructed utilizing techniques presented herein or in incorporated by references. In some applications, the peripherals circuit could be placed on more than one stratum. This could be used for memory partitioning to small units such that the area of a unit is too small to fit all the require memory control on a single stratum. For example, the upper most stratum may be control logic to control about the upper half of memory stratums while the lower most stratum may be control logic to control about the lower half of the memory stratums.
Another approach that could leverage such monolithic 3D technology is multiple port access to the memory array. This could also include non-symmetrical multiport access, such as one access port could access single unit, while another access port could access multiple units. This multiport non-symmetrical access could be achieved by controlling the access to the segments of word-lines and/or bit-lines. The access from the top and the access from the bottom could be independent, yet synchronized. In such, for example, the wordlines and bitlines could be accessed by per unit memory control from the top control stratum, while the bottom control stratum provides access to the same wordlines and bitlines with multiple units control, providing one memory port access per unit from the top, while the bottom control stratum could provide access to a block of memory that could include multiple units.
The 3D memory architectures herein constructed with arrays of memory units each comprising memory strata in which every stratum has at least one select controlled from the overlaying and/or underlying memory control stratum, and the multiple options opened up by such architecture including yield repair, local and global access, is applicable to many memory technologies, including volatile and non-volatile. These architectures benefits are applicable to many of the 3D integration techniques presented herein including epitaxial based with shared lithography and layer stacking with grind and etch-back. A technologist in the art of memory systems could engineer a specific system leveraging the techniques presented herein.
Memory centric applications such as intelligent systems or search applications could be implemented as a memory focused processing system utilizing such 3D systems as is illustrated in
An additional alternative is to replace the per level select transistors such as illustrated in
The memory control circuits 2432 and/or 2428, also often called the memory periphery circuits, could include decoders, sense amplifiers and additional circuits for the specific memory 2430. For the case of per level pillar the circuits driving the word-lines or not-lines pillar (2401-2404) could include first the level selects similar to the one in reference to
The memory control circuits 2432, 2428 could be designed to be transferred on top of the memory multi-level stacks with the control transistors facing down toward the memory stack, or first be transferred onto a carrier wafer and then be transferred on top of the memory stack, resulting in the control transistor facing up away from the memory stack. Similar alternatives are available for the control circuits under the memory stack 2428. While
Another alternative for constructing a 3D memory stacked structure is to reduce changes in the memory wafer processing and compensate by adding process steps to the stacking process.
An additional step could be added which is forming alignment marks for this stacking process. The bonding alignment mark could be included in the metal layer as the bonder could see these alignment marks from the top view of the wafer.
Additional steps that could be taken in the memory fab to help the following stacking process could include using a lithographically defined doping process.
As a general note, the use of top pad and bottom pads herein are exchangeable as with the use of layer transfer techniques. These structures could be flipped for specific applications using the presented technology and structures herein. In some cases there might be a need to flip the layer before bonding it to the target wafer. A carrier wafer, such as presented in at least U.S. Pat. No. 8,273,610, incorporated herein by reference, could be used to support such flipping. The carrier wafer could also leverage techniques presented herein in respect to the term “cut layer”, and could be designed to be grind and etched out, or to be reused having it ‘refurbished’ and used again. Additional techniques for such a carrier wafer could be to form a porous layer at the top of a carrier, such as presented in respect to the ELTRAN process, without the need for the epitaxial step but rather just use it with silicon top or add oxide for the bonding. Another option is to use a wafer with a thick oxide and/or a nitride cover of a few microns and optionally add grooves at the dice lane or between lithographic projection fields. Then detach the carrier wafer by a though-side etch leveraging the very high selectivity of etch rates between silicon and oxide or nitride. An additional alternative is to implant ions such as a combination of helium and hydrogen and then use low temperature (˜400° C.) ion-cut for detach. An example for a need of flipping is in a case when the desired landing pads 2006 are in a range of about 200×200 nm2 or about 400×400 nm2 while the designated location for these pads might be desired for operating silicon. In such case, a via smaller than 100×100 nm2 through the transferred silicon film (strata) could be used and the landing pads could be constructed over the carrier wafer, once the layer was transferred onto the carrier wafer.
An additional enhancement could be by adding to through-strata-via that we could also call a through-layer-via ‘TLV” such as illustrated in
An example for such a feed-through TLV is illustrated in
A standard wafer fabrication technology or baseline technology could be established for the memory per unit pin out position and function. That standard wafer fabrication technology or baseline technology could also be used for the custom logic design so it could integrate the generic memory wafer presented herein, for example, by bonding. Each standard wafer could include alignment marks for the custom logic top layer to help align the generic memory wafer during the bonding process. The standard wafer could include processing cores compatible with the size of the memory unit such as, for example, about 200 μm by 200 μm, a street width between units such as, for example, about 1 μm. The signals to be connected in-between such as: 40 pins for address, 16 pins for data, 10 pins for control (such as read and write) and 4 pins for pass through paths. Some of these pins could be defined in the industry standard as expansion options or to allow more than one memory type or architecture. With about 100 pins per unit, the area for each pin could be about 20 μm by 20 μm, which allows the use of most wafer bonders available currently in the industry. Additionally, the generic memory and control stack could be designed to be about 50 μm thick so it could be shipped, handled, and bonded by industry standard processes and machines. Such could become also a standard for which the memory stack could include a path-through the interface layer with the proper thickness so the total stack would be about 50 μm thick. For example, for a 16 memory layer stack of 1 μm each and control stratum with I/O stratum of 2 μm, the stack thickness could be about 18 μm, and a path-through layer of about 32 μm could be bonded on top to bring the overall stack thickness to about 50 μm thick, compatible with the current industry capability. The pass through paths could be built using technology such as TSV to pass, for example, the approximately 100 signals from the generic memory to the custom 2D processor device, to the processor device such as based on planar, SOI, FinFET, or gate-all-around technology.
The technique of using a precise bonder with staggered pads on word-lines or bit-lines presented in respect to
The stacking techniques presented in respect to
Additional option is to stack different memory type. Clearly stacking could include many type of stratum, yet the unique aspect of the stacking technique herein is to form vertical connection of the word-lines and the bit-lines while having per strata select line such as SLi of
An additional step that could be included in the preparation of 3D memory structures for stacking is adding bonder alignment marks. Precise bonders generally need alignment marks to align wafer to wafer. These alignment marks could be incorporated in the proper location on the top and/or bottom layers of the 3D memory wafer structure using a proper mask of the 3D memory structure such as in a nonfunctioning zone over the wafer such as in-between memory structures.
The technology for precise wafer bonding is being enhanced, recently demonstrating the improvement of wafer to wafer alignment tolerance from 200 nm three sigma to 50 nm. These works have been reported by papers such as by Peng, Lan, et al. “W2 W permanent stacking for 3D system integration.” Electronics Packaging Technology Conference (EPTC), 2014 IEEE 16th. IEEE, 2014; by Sakuma, Katsuyuki, et al. “Bonding technologies for chip level and wafer level 3D integration.” Electronic Components and Technology Conference (ECTC), 2014 IEEE 64th. IEEE, 2014; by Sugaya, Isao, et al. “Precision wafer bonding process for future cost-effective 3DICs.” Advanced Semiconductor Manufacturing Conference (ASMC), 2015 26th Annual SEMI. IEEE, 2015; and by Kurz, Florian, et al. “High Precision Low Temperature Direct Wafer Bonding Technology for Wafer-Level 3D ICs Manufacturing.” ECS Transactions 75.9 (2016): 345-353, all of the forgoing are incorporated herein by reference.
An additional option to accommodate large total stacking misalignment is to build the relatively larger landing pads and pins over the memory unit. This way the space 2311 between the memory units could be kept relatively small while the landing pads could be made large enough to accommodate the total error which could include the bonder alignment error or/and the die placement errors. Such over the array pads construction could add costs associated with the processing of such over the array pads and additional per stacking layer costs in the stacking fabs to build these extra layers of landing pins.
The 3D memory stack herein enables stacking multilayers of memory stratum in which the vertical connectivity is at the word-line and bit-line level. Such 3D stacking enables use of a memory control for multiple memory stratums thus reducing cost in addition to benefits in performance and power reduction. Yet vertical connectivity at the word-line/bit-line level could be a technology challenge as the high pitch of these memory control lines may prevent the use of techniques such as ‘smart-alignment’ as there might not be enough room to run TLVs through. For such cases the Hybrid/Fusion bonding techniques presented herein, at least in respect to
The 3D memory stacking presented herein could be modified to accommodate technology limitations or cost objectives. Such modification could include connecting only the bitlines at the unit level while connecting the wordlines at a far courser granularity or vice versa (connecting the wordlines at the unit level and the bitline at the bank on multiple unit level). Other modifications could include staggering the layer select transistors position of
An additional alternative to a form buried cuttable layer is to replace the buried SiGe with oxide, nitride or other layers. This could be done following a step of isotropic etch as has been described, such as in reference to
An additional alternative for a ‘cut-layer’ is to use a single atom layer of Graphene as presented in a paper by Kim, Jeehwan, et al., “Principle of direct van der Waals epitaxy of single-crystalline films on epitaxial graphene.” Nature communications 5 (2014), and Yunjo Kim, et al., “Remote epitaxy through graphene enables two-dimensional material-based layer transfer” published at NATURE|VOL 544|20 Apr. 2017, incorporated herein by reference. It was discovered that a single atom layer of graphene being placed on a single crystal substrate could allow a single crystal epitaxial growth on top having the base crystal orientation and quality. Yet the layer grown on top of the graphene could be pulled off as the graphene layer has “weak van der Waals interactions, and which also allows facile layer release from 2D surfaces”. Enabling “the grown single-crystalline films are rapidly released from the graphene-coated substrate and perform as well as conventionally prepared films”. Accordingly, such a single atom graphene layer could serve as alternative to the porous layers described herein or combined with such or other forms of ‘cut-layer’ presented herein. The base substrate could be reused after ‘cutting’ off the functional layer. A graphene cut could be used in a similar way to the original concept of porous layer for formation of SOI wafer as was named ELTRAN by Cannon.
Many mix and match of these cutting techniques could be utilized for different product formation and related flows. One such mix could be used for die to wafer 3D integrations as discussed in U.S. patent application Ser. No. 15/095,187 (now U.S. Pat. No. 9,721,927) and Ser. No. 15/173,686 and herein. So, the cut of the 6 microns thick die could use the graphene as the cut layer but then the following a step of thinning the layer after being bonded to the target wafer, and could leverage the SiGe etch selectivity for etch and controlled thinning to below 1 micron to allow a simple process with nano-TSV through (with less than 400 nm via diameter) the thinned die.
An additional technique that could be used for a 2D material such as Graphene as a ‘cut layer’ is an oxide type post that could be etched out prior to the layer transfer step. As the substrate with a cut layer being built in could go through the full front end of the line processing and some back of the line processing before the layer transfer, it could be desired to add in such posts to keep the stability of the structure for the various processing steps prior to the transfer step. Using a modified STI step, holes could be etched all the way through the graphene into the underlaying substrate, and filled with oxide. These holes could be made in the dice lanes. Then as one of the last step before performing the layer transfer operation these oxide posts could be etched away releasing their hold. Additionally, these in the dice lanes could be extended to a full dice lane etch so that in the layer transfer step each die may be peeled off independently from the other dies.
The release process could include a polymer or other material such as nickel to help form a stress which together with temperature, such as liquid nitrogen or less than 400° C. degree spike heating, could help the detach and release of the re-useable substrate from the 3D structure comprising the target wafer and the bonded transferred layer. An alternative technique could include the use of pulling 5-30 micron thin layers off reusable wafers using a technique called controlled spalling such as presented in papers by Shahrjerdi, Davood, and Stephen W. Bedell. “Extremely flexible nanoscale ultrathin body silicon integrated circuits on plastic.” Nano letters 13.1 (2012): 315-320; and by Bedell, Stephen W., et al., “Layer transfer by controlled spalling.” Journal of Physics D: Applied Physics 46.15 (2013): 152002; and U.S. Pat. Nos. 9,698,039, 9,704,736 and 9,713,250, incorporated herein by reference. A reusable “cuttable” substrate could be constructed using the following steps; 1) Form the thin layer with desired silicon thickness on top of a SiGe etch stop layer using an epitaxial process over a donor wafer. 2) Form a reusable carrier by growing 3-10 micron thick oxide (or nitride) over a silicon wafer. 3) By using controlled spalling pull out a 5-10 micron layer off the silicon over SiGe (top Si/buried SiGe/fractured bulk Si stack) from the donor wafer and bond it on top of the reusable carrier, thus forming the reusable “cuttable” substrate. Optionally, the fractured surface portion of bulk Si maybe treated to be planarized for better bonding to the resuable carrier. The reusable “cuttable” substrate could now be processed with building the desired circuits on top of it. Then it could be bonded on top of a target wafer. Then using selective oxide or nitride etch from the side of the wafer, the bulk of the reusable “cuttable” substrate could be detached leaving over the target wafer the circuits and the layers previously bonded to the 3-10 micron thick oxide. Than using SiGe as an etch stop, the 5-10 micron silicon could selectively etched followed by a SiGe etch. In the process the edge of the wafer could include protection of the interconnect layers to protect them from the side oxide detaching etch.
The ‘cut-layer’ technology presented herein could also be used for applications requiring a very thin device. An example of such application is integrating a semiconductor device in a contact lens or in application requiring a very flexible circuit layer. In these applications the ability to use a standard semiconductor fabrication process following by thinning the device thickness to a few microns or hundreds of nano-meters or even less, could be key enabling technology.
An additional inventive embodiment for a 3D memory constructed of arrays of relatively small memory units, with the memory control circuits on top or under of such memory units relate to the ability to perform per unit refresh and other techniques to extend memory effectiveness. This could be applied for DRAM type memory as presented herein before and also for non-volatile memory such as charge trap, floating gate and ferro-electric based memory. These memory units could have an X direction and/or Y direction size of a few tens of microns, or a few hundreds of microns. For example, some of the general concerns with memory structures relate to disturb and other forms of losing memory fidelity. These could impact the level of memory density utilization. With such a 3D memory system as illustrated in
At least one type of control lines from wordlines and bitlines of each memory levels could have its own per level vertical connection to the logic level. In the illustrations of
The memory level of the memory level may be similar to its neighboring memory levels An exemplary section of memory level is shown in
The 3D memory stack device could be coupled with core and peripheral logic and be supplied as known good die, the memory device may be use to configure an SoC, ASSP, FPGA, TPU, or FPGA as shown in
For high precision bonding, the industry is adopting a technique called fusion bonding. In fusion bonding, both wafers are aligned and a pre-bond is initiated. When bringing the device wafers together, wafer stress, local warpage, and/or bow can influence the formation of a bond wave. The bond wave describes the front where hydrogen bridge bonds are formed to pre-bond the wafers. Controlling the continuous wave formation and influencing parameters is the key to achieving the tight alignment specifications and avoiding the void formation noted above. The reason for this is that any wafer strain manifests itself as distortion of the wafer, in part due to lateral and vertical thermal non-uniformity and built-in bowing, which leads to an additional alignment shift. Process and tool optimization can minimize strain and significantly reduce local stress patterns. Typically, distortion values in production are well below 50 nm. Indeed, further optimization of distortion values is a combination of many factors, including not only the bonding process and equipment, but also previous manufacturing steps and the pattern design. Once the initial bonding has been confirmed to meet the alignment requirements, an annealing step would take place to finalize the bonding process. So it desired to have the first bonding step, also called pre-bonding, at a lower temperature or even at room temperature thus reducing stress and expansion associated with an elevated wafer temperature. Only after good alignment has been confirmed will the bonding move to the second step at an elevated temperature to finalize the bonding. The elevated temperature could be higher than 100° C., or even higher than 200° C., and preferably lower than 400° C. There may be a need to control the ramp-up and ramp down rates of this thermal anneal of the final bonding step.
An additional option could be integrated with the proposed flows herein, that the additional bonding step could be used after removing the bonded wafer substrate 2146. Once the ˜700 micron substrate 2146 has been removed the top structure left would be relatively flexible. Than applying pressure or thermo-pressure on it, could help to assure connecting pins to pad if those are not yet connecting 3002 due a thin gap left in-between.
For such pressure a special chuck could be used. The special chuck which we will call bonding-piston 3000 could have a flexible contact surface 3016, a fluid 3014, water or oil or option for such fluid, or sol/gel, or elastomer to distribute the pressure evenly, heating bodies 3012 segmented in multiple patterns and with independently temperature control and main body 3010. Alternatively, a flexible contact surface may be implemented by flexible and thermally conductive materials, such as, for example, doped elastic polymers. Using such bonding-piston 3000 the bonder could form an even pressure on the top surface of the bonded structure 3024, 3022 after the top substrate has been removed as is illustrated in
Additional step that could be used to enhance these pins to pads bonding is a light etch back of the top oxide surface just prior to bonding. A few nanometers of atomic layer oxide etch could make the pins and the pads to connect and bond first while the oxide would be connected and bond slightly later achieving mechanical strength from the oxide to oxide bonding while the metal to metal bonding also provides the electrical connectivity.
Additional findings related to fusion bonding have been detailed in work by Di Cioccio, L., et al., “An overview of patterned metal/dielectric surface bonding: mechanism, alignment and characterization” Journal of The Electrochemical Society 158.6 (2011), incorporated herein by reference. For instance, Cu-Cu bonds can occur at room temperature, without pressure normal to the bonding interface. The mechanism is as follows: below 200° C., Cu surfaces have an unstable copper oxide; when two Cu surfaces are brought into contact, the asperities make contact first; Cu diffuses across the copper oxide interface; the unstable oxide moves laterally; the asperities undergo plastic deformation; the contact area spreads along the oxide interface; eventually, a tough bond occurs (as seen in bond toughness vs multi-day storage time data). This process can be accelerated using a 200° C. anneal. Use of CMP, to reduce asperities and make the surface hydrophilic, could be important. “Dishing” of the Cu surfaces during CMP can either delay bonding, or prevent it altogether, on large-area bonds. Generally this can be mitigated by dividing the large area into a multiplicity of smaller areas. Dishing may therefore be less of a problem for 20 nm+/−bond areas. Especially as metal-metal contact areas shrink well below 1 μm, some copper oxide contact between small bond areas could be important to ensure bonding according to the preceding mechanism proceeds to completion. This realization suggests that some selective augmentation of the height over metal bond pads could succeed in producing a low-resistance, high-quality metal-metal bond. Graphene suffices for this purpose, especially as it deposits preferentially on Ni and Cu surfaces. A simple, slight oxidation of the bond pads could create a slightly raised CuO surface, to ensure mechanical contact prior to wafer- and contact-bonding and annealing.
Selective and/or preferential, maskless deposition of adjuncts onto the metal pads, prior to bonding, could suffice to produce a low-resistance, high-quality bond. Such deposition could be performed using atomic layer deposition (ALD). A list of such adjuncts includes, but is not limited to, the following: aerogels; MoS2; epitaxial perovskites; metals; SiC; porous Si nanowires; transition metal di-chalcogenides (TMDCs), such as WSe2, which additionally may be doped or activated in-situ using, for example, He or H2 plasmas.
Low-resistance, high-quality metal-metal bonds may also be affected using copper nano-pillars, as described in Lee, K. W., et al., “Novel W2 W/C2 W Hybrid Bonding Technology with High Stacking Yield Using Ultra-Fine Size, Ultra-High Density Cu Nano-Pillar (CNP) for Exascale 2.5 D/3D Integration.” Electronic Components and Technology Conference (ECTC), 2016 IEEE 66th. IEEE, 2016, incorporated herein by reference.
The specific memory unit architecture herein could help by having the pins and pads in the periphery of the memory array units. Additionally a patterned oxide etch could be used to further assist the process of bonding these memory strata.
An additional process embodiment that could be applied to this memory stratum is the use of electrical current to harden the word-lines and bit-lines global pillars. Current is used for Bridge-RAM and R-RAM to form conductive filaments to reduce resistivity as a technique to form memory. Similarly, current applied through the pillars could be used to further harden/improve the connection between the pins and pads and may overcome a thin oxide or other barrier. The location with incomplete bonding naturally has high resistance and the flowing current through such results in localized hot spot. Therefore, Joule heating is localized to the weak bonding region and thus selectively improves the bonding due to intermixing of the metal material or partially melting the metal. The design of the top most and the bottom most level could be such that it would enable such a current hardening without damaging the low voltage circuitry and circuit elements. Such techniques are commonly used for metal to metal antifuses as presented in at least U.S. Pat. Nos. 5,126,282, 6,529,038 and 5,986,322; all of the forgoing are incorporated herein by reference. Conventional and other stacking technologies have been presented in: Di Cioccio, L., et al., “An overview of patterned metal/dielectric surface bonding: mechanism, alignment and characterization.” Journal of The Electrochemical Society 158.6 (2011): P81-P86; Di Cioccio, Lea, et al., “An overview of patterned metal/dielectric surface bonding: Mechanism, alignment and characterization.” ECS Transactions 33.4 (2010): 3-16; Kim, Soon-Wook, et al. “Ultra-Fine Pitch 3D Integration Using Face-to-Face Hybrid Wafer Bonding Combined With a Via-Middle Through-Silicon-Via Process.” Electronic Components and Technology Conference (ECTC), 2016 IEEE 66th. IEEE, 2016; Liu, Ziyu, et al. “Room temperature direct Cu-Cu bonding with ultrafine pitch Cu pads.” Electronics Packaging and Technology Conference (EPTC), 2015 IEEE 17th. IEEE, 2015; Teh, W. H., et al. “Recent advances in submicron alignment 300 mm copper-copper thermocompressive face-to-face wafer-to-wafer bonding and integrated infrared, high-speed FIB metrology.” Interconnect Technology Conference (IITC), 2010 International. IEEE, 2010; Lee, Kangwook, et al. “Nano-scale Cu direct bonding using ultra-high density Cu nano-pillar (CNP) for high yield exascale 2.5/3D integration applications.” 3D Systems Integration Conference (3DIC), 2016 IEEE International. IEEE, 2016; and Lee, K. W., et al. “Novel W2 W/C2 W Hybrid Bonding Technology with High Stacking Yield Using Ultra-Fine Size, Ultra-High Density Cu Nano-Pillar (CNP) for Exascale 2.5 D/3D Integration.” Electronic Components and Technology Conference (ECTC), 2016 IEEE 66th. IEEE, 2016, all of the forgoing are incorporated herein by reference.
An additional technology that could be utilized to achieve good metal to metal connection is ultrasound energy. Ultrasonic bonding has been used for years in wire bonding. An advantage of the use of ultrasound is having the energy focused in the bonding area allowing the processing to keep the overall temperature low, both to avoid forming defects in the semiconductor active devices and to reduce stress resulting from thermal expansion. For such processing, the chuck could include, for example, ultrasonic transducers instead of the heating elements 3012, or in addition to them.
An additional embodiment is to tune the ultrasound frequency to match the bonding pins self-resonant (natural) frequencies for even better targeting of the sonic energy to the desired pin-pad locations. Use of ultrasound for bonding has been reported in a paper by Xu, Penghui, et al., “An ambient temperature ultrasonic bonding technology based on Cu micro-cone arrays for 3D packaging.” Materials Letters 176 (2016): 155-158; by Matheny, M. P. and K. F. Graff, “Ultrasonic welding of metals.” Power ultrasonics. 2015. 259-293; by Iwanabe, Keiichiro, et al., “Bonding dynamics of compliant microbump during ultrasonic bonding investigated by using Si strain gauge.” Japanese Journal of Applied Physics 55.6S1 (2016): 06GP22; and by Li, J., et al., “Interface mechanism of ultrasonic flip chip bonding.” Applied Physics Letters 90.24 (2007): 242902; all of the forgoing are incorporated herein by reference.
A potential challenge for such a stacking process is wafer to wafer variations. There are many sources for such variation and some could be managed by sourcing the wafers in the stack from the same process line being produced, preferably from the same lot using the same stepper. Yet some times this might not be possible or there might be variations that are still too high. During wafer processing such variations could be managed by the stepper equipment periodic alignment and optical magnification or reduction to achieve layer to layer alignment with sub nanometer precision. In a similar way such could be done using thermal expansion to compensate for these local variations.
Accordingly the fusion bonding of the wafer described in at least herein could include a thermal chuck with area thermal control. For example, the thermal chuck can be divided into a number of tiles with the unit thermal control size such as at a reticle or sub-reticle level.
The chuck 3120 structure could include thermal isolation structures 3124 so to allow better confinement of the temperature of each zone to better achieve expansion or contraction of different zones to better align to the bonding targets and control the bond wave more precisely. Chuck 3120 structure may include temperature measurement devices in each area zone, for example, with an embedded MEMS device/structure, thermoelectric heaters and/or cooling devices/structures, as well as local feedback/proportional control functions/devices. Chuck 3120 structure may include micro valves and channels for coolant or heating materials, such as liquids or gases.
A 3D system construction could use a mix of the technologies presented herein and the incorporated references. For wafers that been produced having precise wafer, reticle, and die alignment, a simple stacking process flow and tools might be good enough and then other wafers could be stacked on using more advanced techniques such as the Advanced Smart Alignment technique. These could be integrated with other bonding techniques such as using per zone temperature setting and filling/bonding and forming a via for connectivity afterward using techniques such as smart-alignment. Such mix and match techniques could be engineered to achieve the many times dissimilar objectives such as performance and cost.
Some of the stratum within such a 3D strata could include layers designed to function as, for example, an Electro Magnetic Field “EMF” shield, a power plane, a heat spreader, a heat isolation layer, or as some combination of such. For example, properly designed metal layer may provide some of the above functions. At least these functions and how to achieve them may be found in U.S. Pat. No. 9,023,688, incorporated herein by reference.
In reference to
The operation of such a 3D system could reference the memory fabric as a dual port memory fabric in which one side of the stack could be used to input and output data access, while the other side could be used for processing the data in the memory stack. Both operations could utilize the same pillars of memory control, preferably by synchronizing access. Such could include time slot allocation or space slot allocation. For example, for space slot allocation one processor could have two or more units in which processing is done in one unit while data input/output is done with the other unit.
An additional advantage to the memory architecture herein as illustrated by
The recent adoption of neural net and learning algorithms suggests many simple operations, such as multiply and accumulate, to process a massive amount of data. In many of these systems the base elements are called neurons and may need three operand reads (since each neuron MAC operation requires 3 reads, weight, activation and partial sum, and one write-new partial sum). In AlexNet, a well-known reference network in the domain, 3 billion memory accesses are required to complete a recognition. The processor unit could use corresponding memory control circuits to fetch the three operand reads in parallel from its 3D memory unit, and once ready store the result back to its 3D memory unit. The number of bits for many of these processes is less than 16 per operand so more than one such neuron could be processed per one 3D memory unit. For example, with the area marked by 3264 could include a 3D memory unit having 8 levels of memories 3230, memory control circuits 3228 designed to provide three sixteen bit operands for one read, and a multiplier accumulator circuit within its processor fabric level 3224. In some memory structures there is a need for a sense amplifier to convert the signal on the bit-line to a logic signal useable for the multiply accumulation function. Such could require 48 sense amplifier circuits on the memory control level. Alternatively, a lower number of sense amplifiers may be provided and the signals are multiplexed in and buffered afterward.
An additional alternative is to mix processing to unit access with processing to clusters of unit access. Thus, in addition to read and to the same unit, the 3D system could be designed to support access to a group of units as just a bigger array. In such a mode, for example, the units 2231, 2232, 2234, and 2235 could be considered as a larger memory. To access the 2×2 units as a larger memory block the memory control of these units could be designed so the bit-lines and the word-lines are enabled to provide all the selected units, for example, using the vertical pillars 2256 & 2258 as BL access and the 2×2 block and the vertical pillars 2246 & 2257 as the corresponding WL access. Accordingly the exemplary 3D system illustrated in
An alternative fabric could include buses oriented in the X direction and buses oriented in the Y direction. Such buses could include eight to sixteen data lines: about six to eight unit address bits and two to four control signals. These buses could be a single line per bit or a differential line with two lines per bit. These buses could include re-buffering electronic support to reduce the effect of the line's RC. These buses could include mixed length buses such that cover of the full length of the system in the X or Y direction to buses that are shorter, such as a half-length, quarter length and so forth, down to the length of two units.
These across unit array data exchanges buses could be managed by the central system control circuits. These buses could function as a synchronized data exchange and could use differential data communication using centralized clocking to activate the active differential amplifiers to convert the differential signaling to conventional CMOS signaling, similar to what has been presented in U.S. Pat. No. 7,439,773, PCT/US2016/52726, and also U.S. Pat. No. 4,916,910, and U.S. application 2017/0170870, all are incorporated herein by reference.
As a general note we described herein or within incorporated documents a memory structure and variations. There are many ways to form other variations of these structures which an artisan in the semiconductor memory domain may form by the presented elements described herein. These may include exchanging n type with p type and vice versa, increase density by sharing control lines, silicidation of some silicon control lines, improve speed and reduce variation by strengthening bit-lines and word-line with upper layer parallel running and periodically connected metal lines (strapping).
In general, as previously discussed the 3D stacking flow presented here could be used for 3D memory structures just as for 2D structures and could be engineered by an artisan in a memory art for mix and match. For 3D memory the level select could become the structure select. Such as discussed before, adding additional transistors into the word-lines or the bit-lines to select a 3D structure of multilayer as a multi-floors level. It could be desired to have additional set(s) of pads and pins to allow vertical connectivity also for the per layer contacts. Accordingly the memory control accesses the memory stack just like accessing a single memory structure as they are connected in parallel while the selecting of one structure in the stack is achieved by activating its level select (LS). As had been discussed before in such architecture the memory matrix could be structured as a matrix of units each about 200 microns by 200 microns. Current state of the art of 3D memories (3D NAND) are approaching 96 layers yet with a height of about 6 microns. Many such 3D memory structures could be stacked before the unit height approaches its X/Y size.
A modular 3D IC system, as disclosed here utilizing arrays of units each with its unit 3D memory cell block, memory control circuit block, processing logic block, and I/O block, needs good in-plane (X-Y) lateral interconnect such as high throughput and low power consumption for system level functionality. While the out-of-plane (Z) vertical interconnects are formed having vertical vias with diameters of nano-meter sizes (10 nm-200 nm) up to micron sizes (3-20 μm) and relatively short heights of equal or not exceeding the back side to back-side ground die thickness, such as less than 50 μm, the interconnect length of horizontal in-plane direction (X-Y) remains at millimeter sizes, from die level (3-16 mm, for X and Y sides), reticle level (20-30 mm), to multi reticles, and up to wafer sizes (60-300 mm). Clearly the interconnect challenge is now greater for the X-Y interconnect. The propagation delay and power dissipation using low-resistance metals such as copper and low-k dielectric material may have a switching frequency limit in the 10 GHz range, which will end up impeding the 3D system performance improvement. The optical interconnect in X-Y allows an enormous bandwidth increase as well as immunity to electromagnetic noise and chip temperature variation. Furthermore, the optical interconnect decreases power consumption. In reference to
The monolithic 3D technologies presented herein and in the referenced works could be used to simplify the challenge and enable 3D integration of optical on-chip interconnect to further enhance such 3D systems and allow efficient X-Y interconnect across or among 3D SoC (System on Chip) or other 3D devices.
An important aspect of the monolithic 3D technologies is the enabling of heterogeneous integration, in which one level (wafer) is produced using process and material to fabricate logic devices while another level (wafer) is produced using different process and different materials to fabricate on-chip optical interconnect devices. Furthermore, these levels (wafers) would likely be made in different locations and/or wafer fabs. Then using a layer transfer process, one level is transferred over the other enabling fine vertical (3D) integration between the two.
The on-chip optical interconnect level could include more than one sub-level, for example, such as a passive photonic device level(s) for signal routing such as wave guides, photonic crystals, and resonators, and an active device level(s) such as photo-detector and light source (for example, a laser). The photo-detector and light sources can reside in its own different levels or they can be in the same level but with the two made with different substrates knitted tighter side by side. For example, the photo-detector may be based on germanium, the light source maybe based on III-V semiconductor, and the passive devices may be based on silicon (core)-silica (cladding) structures. The logic level itself could include many levels as illustrated in
The optical modulator which is controlled by an electrical driver connected to an electrical logic block may be inserted between a light source and a waveguide. The optical modulator combines an optical structure and an electrical structure. A PIN diode and microresonator make an optical modulator in one embodiment. A MOS capacitor and a Mach-Zehnder interferometer make an optical modulator in another embodiment. Any of those optical modulators may be monolithically integrated as a part of the waveguide.
In one embodiment of the 3D SoC, the on-chip optical interconnect level may use a single wavelength point to point link (1-1 link), single and multiple wavelength point-to-many broadcast (1-n link), or multiple wavelength bus and switching (n-n link). The 1-1 link may be used in data-intensive links such as processor-memory buses. The 1-n link may be used to replace the clock distribution network and eliminates the use of several hundreds of repeaters, which used metallic interconnect. Herein, n represents an integer number larger than 1. Current technologies support optical interconnect such that a wave guide could allow many electrical input ports to add optical coded data to be transferred by the waveguide and many output ports to sense the data in the waveguide and to form electrical data outputs based on the optical data in the waveguide. This could be called an n-n optical link.
In another embodiment of 3D SoC, only the light source may be off-chip whilst the rest of the optical components are integrated on-chip. The light source and on-chip optical interconnected 3D SoC may be implemented using multi-chip module technology.
In one embodiment of optical interconnect 3D SoC, the wavelength of the light source may range from 1.3˜1.55 μm. Alternatively, wavelength division multiplexing (WDM) may be used. Each individual wavelength signal does not interfere with another wavelength while a single wavelength could be used to replace a multiple bit bus. Therefore, WDM provides a very high data rate beyond any single wavelength device bus data rate.
The choice of layer transfer technique could be engineered based on the specific choice of substrates of the various levels, fabrication line and so forth. Techniques such as ion-cut which was detailed in respect to at least FIG. 14 of U.S. Pat. No. 8,273,610, incorporated by reference, and in many of the presented 3D IC flows in it. U.S. Pat. No. 8,273,610 presents multiple techniques to repair the damage formed during the ion-cut process such as in reference to at least its
Optical interconnect could be used to complement the metal interconnect for X-Y connectivity of a 3D IC system. At relatively long in-plane distances such as 5 mm, 10 mm, 20 mm or even longer than 40 mm, optics provide higher speed and lower power dissipation. The capacitive load and on-resistance impede the metal connection performance. Optical wave guides could be used for simultaneous transfer of multiple signals using modulation techniques similar to those used in fiber optic communication systems. But unlike electrical connections, optical wave guides need far larger dimensions, which imply that the optical wave guide profile is sized in microns rather than in nanometers. A layer transfer based optical interconnection could be to leverage a generic optical connectivity fabric. Such could be transferred and reused over different designs, allowing each design to use the generic optical fabric in a different way. Such a generic fabric could include wave guides going though across dice lines and across reticle borders. As discussed in many of the incorporated art herein, 3D devices could include redundancy and repair technology to allow a very high level of integration including a finished device/system size of, for example, a reticle size, a few reticle sizes, or even wafer level, known as wafer scale integration (“WSI”). For some of those techniques, a generic fabric represents a challenge of dicing metal lines which may need an etch step and sealing material deposition to be included. An optical wave guide could be diced without the need for such etch or addition of sealing layers to protect the device as the optical waveguide in most cases is formed by isolation layers which do protect the device from external humidity, etc. This could be part of the engineering & design trades made by an artisan skilled in the art. Such makes the concept of one or more generic optical connectivity layers an attractive option to support different system configurations which could include dicing for different sized base devices customized for the specific target application. Stress relief layers may be added in-between the optical (Ge, SiGe, etc.) and the Si circuitry—so after layer transfer and bonding they are between the optical and other layers. Silicon dioxide is an example of a stress relief material.
The formation of a very long waveguide going across reticles might include a step of isotropic etch and other smoothing techniques to allow better waveguide performance as it crosses reticle boundaries.
The architecture of the generic optical interconnect level 3504 could be designed to support a modular 3D system fabric having a generic array of units underneath. An industry standard could be set so different design teams can use the generic optical interconnect each in a way that supports its target system design and application.
In one embodiment, a vertical cavity surface emitting laser (VCSEL) may be considered as the III-V light source and a PIN germanium diode may be considered as the detector. In another embodiment of the present invention, all silicon based light sources and detectors may be considered. In such case, a Raman-silicon laser and a silicon based PIN photo-detector may be considered.
Prior art work shows alternative options to form an On-Chip Optical Interconnect. Such work has been presented in at least U.S. Pat. Nos. 7,389,029, 8,837,872, 8,428,401, 8,938,139, 9,368,579, 9,423,560, 9,851,506, and application 2015/0049998, all are incorporated herein by reference. These technologies could be engineered to support specific applications. U.S. Pat. No. 8,428,401 does teach use of a metal structure as part of the optical wave guide which could require some attention if it needed to be part of a dicing lane. These could be resolved by either dicing process or etching these regions before dicing, modifying the waveguide in regions that could be part of dicing lanes, such as by replacing the metal on these regions with a dielectric having a lower reflective index.
In an embodiment of the generic optical connectivity fabric, the waveguides are arranged in a Manhattan pattern in X- and Y directions while microdisk-type resonators are formed periodically arranged in a checkerboard pattern. Also, an array of VCSEL and photo detectors may be formed periodically in a checkerboard pattern. Alternatively, 2D photonic crystals where periodically arranged silica cylinders are fully in the XY plane may also form a generic optical connectivity fabric. Then, the layout of photonic crystals may be later tailored on demand.
A common architecture is to have the optical waveguides as part of the ‘backend’ interconnection layer and the photon generator (LED, Laser) and photo detector in the substrate. The waveguide could be a transparent material (silicon oxide, silicon nitride, etc.) surrounded by reflective material such as metal or material with higher reflective index to keep the light beam inside the waveguide. The wave guide could be designed so it could be used by spatially separated multiple inputs and multiple outputs allowing its flexible use. FIG. 4 of U.S. Pat. No. 8,428,401 illustrates a one input with multiple output waveguide structure. Additional work was presented by Shen, Po-Kuan, et al. “Multiple-input multiple-output enabled large bandwidth density on-chip optical interconnect.” Journal of Lightwave Technology 34.12 (2016): 2969-2974; by Heck, Martijn JR, and John E. Bowers. “Energy efficient and energy proportional optical interconnects for multi-core processors: Driving the need for on-chip sources.” IEEE Journal of Selected Topics in Quantum Electronics 20.4 (2014): 332-343; and by Dai, Daoxin, and John E. Bowers. “Silicon-based on-chip multiplexing technologies and devices for Peta-bit optical interconnects.” Nanophotonics 3.4-5 (2014): 283-311, all are incorporated herein by reference.
The optical interconnect could be custom made for the specific 3D system or pre-built being generic and thus servicing multiple 3D systems. It could also be semi-custom, by customizing the generic structure to a specific application. An option for such a semi-custom alternative could be a customization of a generic waveguide by introducing one or more ‘cut’ into it customizing one long waveguide to a two segment waveguide, and/or a three segment waveguide, and so forth.
The layer transfer techniques presented herein enable a thin layer transfer and accordingly allow for a very high density of vertical interconnect between the various levels in the 3D system. This also applies to the layer transfer associated with the optical interconnect. Accordingly the vias such as prepared vias 3718 or the feed through 3712 could have a small circumscribing diameter, for example, such as, about 100 nm, about 200 nm, or even about 400 nm, which is much smaller than the state of the art TSV, which is about 5 microns (R&D) or larger (10+ microns in pilot production).
In some applications is might be useful to have one set of waveguides 3708 traveling in parallel along the Y-axis directions layer 3732, and then transfer over an additional structure of waveguides traveling in parallel along the X-axis directions X direction layer 3734. For example, the pre-prepared connections prepared vias 3718 could be used to connect the control and the electro-optics devices for the transferred waveguides X direction layer 3734. These waveguides could be generic, custom, or customized either before or after being transferred over to the 3D system. In such, a 3D system it might be desired to keep the I/O layer (3236 of
In dissertation works by Donguk Nam titled “STRAINED GERMANIUM TECHNOLOGY FOR ON-CHIP OPTICAL INTERCONNECTS”, December 2013; by Devanand Suresh Sukhdeo, titled “BAND-ENGINEERED GERMANIUM FOR CMOS-COMPATIBLE LIGHT EMISSION”, June 2015; and by Ju Hyung Nam, titled “MONOLITHIC INTEGRATION OF GERMANIUM-ON-INSULATOR PLATFORM ON SILICON SUBSTRATE AND ITS APPLICATIONS TO DEVICES”, March 2016, additional work has been published by Abedin, Ahmad, et al. “GOI fabrication for monolithic 3D integration.” SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2017 IEEE. IEEE, 2017; by Chaisakul, Papichaya, et al. “Integrated germanium optical interconnects on silicon substrates.” Nature Photonics 8.6 (2014): 482; and by Lee, Kwang Hong, et al. “Integration of Si-CMOS and III-V materials through multi-wafer stacking.” SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2017 IEEE. IEEE, 2017, all incorporated herein by reference, layer transfer and strain technology has been utilized to form optical light source (LASER) to support OCOI. Such techniques could be a good fit to the structures presented herein. Use of Germanium for the electro-optic devices could be a good fit with the use of SiGe for a Cut-Layer. These could include use of the buffer layers concept suggested in respect to
In one embodiment for the generic optical connectivity fabric, the n-n link may be desirable for reconfigurable networks, which uses optical switch boxes to dynamically define a communication route between arbitrary two functional blocks. The often called ‘network on chip’ (NoC) has been proposed in Benini, L. and De Micheli, G., Networks on Chip: A New SoC Paradigm, IEEE Computer, 35, 70, 2002; Guerrier, P. and Greiner, A., A generic architecture for on-chip packet-switched interconnections, in Proc. Design, Automation and Test in Europe 2000, 250, 2000; and Dally, W. J. and Towles, B., Route packets, not wires: On-chip interconnection networks, in Proc. 38th Design Automation Conference, 2001; Yang, Peng, et al. “Unified Inter- and Intra-chip Optical Interconnect Networks.” Photonic Interconnects for Computing Systems: Understanding and Pushing Design Challenges (2017): 11. Nikdast, Mahdi, ed. Photonic Interconnects for Computing Systems: Understanding and Pushing Design Challenges. River Publishers, 2017, by Werner, Sebastian, Javier Navaridas, and Mikel Lujin. “A Survey on Optical Network-on-Chip Architectures.” ACM Computing Surveys (CSUR) 50.6 (2017): 89; by Morris, Randy, Avinash Karanth Kodi, and Ahmed Louri. “Dynamic reconfiguration of 3D photonic networks-on-chip for maximizing performance and improving fault tolerance.” Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture. IEEE Computer Society, 2012; by Beg, Christopher. A System Level FMCW RADAR Optimization For Automotive Powertrain Control Application Requirements. MS thesis. University of Waterloo, 2013; by Achballah, Ahmed Ben, Slim Ben Othman, and Slim Ben Saoud. “An Extensive Review of Emerging Technology Networks-On-Chip Proposals.” Global Journal of Research In Engineering (2017); and by Abellán, José L., Chao Chen, and Ajay Joshi. “Electro-photonic noc designs for kilocore systems.” ACM Journal on Emerging Technologies in Computing Systems (JETC) 13.2 (2017): 24, all are incorporated herein by reference. Additionally the following U.S. Pat. Nos. 9,620,489, 9,322,901, and applications 2018/0246286, 2016/0178861, incorporated herein by reference, teach similar concepts of using optical interconnects to support horizontal connectivity for a 3D IC system.
One of the known challenges in reticle size or wafer level integration is yield. In 3D integration, there are multiple redundancy and repair techniques which have been detailed in the incorporated by reference patents herein. These could be used for the optical interconnected 3D system such as is referenced in respect to
Additional aspect of a multi reticle 3D system is added redundancy for the system elements that could be sensitive to yield loss, aspects such as the connections from the optical interconnect to the rest of the system such as the logic level. A simple approach to reduce such yield loss is double modular redundancy or even triple modular redundancy. So these sensitive elements which could include also the electro optics elements such as the laser, and the photo diodes, etc. Having a whole structure being dedicated to the optical interconnect leaves room for doubling or an even higher level of modular redundancy to overcome any reasonable random defect. Additionally, the pre-testing could help reduce any yield losses caused by the optical interconnect structure. Such could allow an efficient multi-reticle 3D system construction. Double redundancy could be designed for parallel connections such as common in double vias for interconnect. Alternatively, it could be designed to be activated by self-testing circuits and support redundancy activation as is well-known in the art and could be engineered by an artisan in the field of fault tolerant systems.
Techniques to use optical lithography to pattern large areas greater than the full reticle field by ‘stitching’ multiple reticle patterns that had been projected independently are known in the art, and are used for Interposer lithography and other applications. Alternatively some lithography tools are designed to support large area projections. Such are presented in a paper by Flack, Warren, et al. “Large area interposer lithography.” Electronic Components and Technology Conference (ECTC), 2014 IEEE 64th. IEEE, 2014; by Lu, Hao, et al. “Demonstration of 3-5 μm RDL line lithography on panel-based glass interposers.” Electronic Components and Technology Conference (ECTC), 2014 IEEE 64th. IEEE, 2014; by Furuya, Ryuta, et al. “Demonstration of 2 μm RDL wiring using dry film photoresists and 5 m RDL via by projection lithography for low-cost 2.5 D panel-based glass and organic interposers.” Electronic Components and Technology Conference (ECTC), 2015 IEEE 65th. IEEE, 2015; by Sundaram, Venky, et al. “Demonstration of Embedded Cu Trench RDL using Panel Scale Lithography and Photosensitive Dry Film Polymer Dielectrics.” International Symposium on Microelectronics. Vol. 2017. No. 1. International Microelectronics Assembly and Packaging Society, 2017; by Zihir, Samet, et al. “60-GHz 64- and 256-elements wafer-scale phased-array transmitters using full-reticle and subreticle stitching techniques.” IEEE Transactions on Microwave Theory and Techniques 64.12 (2016): 4701-4719; and by T Braun, M Topper, R Aschenbrenner, K Lang, White paper on Panel Level Packaging Consortium, all are incorporated herein by reference.
Additionally, some prior works suggest integrating systems using an interposer with optical waveguides such as presented by Arakawa, Yasuhiko, et al. “Silicon photonics for next generation system integration platform.” IEEE Communications Magazine 51.3 (2013): 72-77; by Urino, Yutaka, et al. “High-density and wide-bandwidth optical interconnects with silicon optical interposers.” Photonics Research 2.3 (2014): A1-A7; and by Urino, Yutaka, et al. “Demonstration of 12.5-Gbps optical interconnects integrated with lasers, optical splitters, optical modulators and photo-detectors on a single silicon substrate.” Optics express 20.26 (2012): B256-B263, all are incorporated herein by reference
An additional alternative is to pre-test the optical interconnect components allowing the use of the concept of Known-Good-Die to wafer level die-to-wafer 3D integration by pretesting the optical interconnect fabric before transfer over to the 3D system. These could be easier with the use of a generic optical interconnect which could be produced in volume and pretested before use for the specific application.
Such pretesting could be performed with an external test fixture by measuring light coming at the edge of the wafer. Alternatively, for an optical interconnects structure which includes both the waveguides and the opto-electronics circuit, built-in self-test could be used. Such self-test could be designed in the fabric which could include a photovoltaic region to generate the power for self-test and reduce the need for probing. And reporting the result could also be achieved contactless by use of an optical or wireless signal from the wafer to the test control system.
Such could also be used for the semi-custom optical interconnect fabric as the customization process presented in reference to
The optical inter-die interconnect fabric discussed is one alternative for effective X-Y interconnecting fabric. At least five other alternatives could be used in similar way using electrical signals with metal conducting material: 1) Differential signaling such as was discussed herein in reference to
The RF type interconnects fit well with the presented use (optical interconnect), for 3D system by layer transfer. The common technologies for RF circuits are on RF-SOI substrates supported by multiple vendors these days. Those substrates could be used for layer transfer as discussed herein and in the related application such as by etching the backside handling substrate using the buried oxide as an etch stop. Accordingly
These alternative technologies may challenge the dicing over generic fabric as they do use metal as the interconnecting material. So in such case etch and deposition prior to dicing could be used for proper set up of the dicing lanes as presented in reference to
These technologies could be engineered as an effective alternative to the optical fabric including the use of generic interconnecting fabric with simple customization option by segmentation (cutting) of wave guides. Most fitting alternative to optic could be the TL and SWI. Use of multiple frequencies as a carrier wave could be engineered for n-n connectivity which make the use of a generic interconnection structure easier, as the programming for specific applications could be achieved by control of frequency allocation rather than by switches and conventional programmable interconnects. These techniques are detailed in the papers incorporated herein by reference. Alternatively, multiple-input and multiple-output or MIMO methods may be used for on-chip wireless communication. The layer-to-layer wireless communication within 3D system and intra-layer wireless communication may be enabled via integrated on-chip antennas and can allow arbitrary X-Y-Z interconnect. Techniques for such wireless interconnect has been presented by Russer, Johannes A., et al., “Si and SiGe based monolithic integrated antennas for electromagnetic sensors and for wireless communications.” Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2011 IEEE 11th Topical Meeting on. IEEE, 2011, by Hsu, Heng-Ming, Tai-Hsin Lee, and Chan-Jung Hsu, “Millimeter-wave transmission line in 90-nm cmos technology.” IEEE Journal on Emerging and Selected Topics in Circuits and Systems 2.2 (2012): 194-199, by Abadal Cavallé, Sergi. “Broadcast-oriented wireless network-on-chip: fundamentals and feasibility.” (2016), and by Nossek, Josef A., et al., “Chip-to-chip and on-chip communications.” Ultra-Wideband Radio Technologies for Communications, Localization and Sensor Applications. InTech, 2013, all are incorporated herein by reference.
The details of utilizing such interconnect technologies for Network on Chip (NoC) or other on silicon devices integration is known in the art and presented in publication such as by Karkar, Ammar Jallawi Mahmood, “Interconnects architectures for many-core era using surface-wave communication.” (2016); by Karkar, Ammar, et al, “Surface wave communication system for on-chip and off-chip interconnects.” Proceedings of the Fifth International Workshop on Network on Chip Architectures. ACM, 2012; by Ong, S. N., et al., “A 22 nm FDSOI Technology Optimized for RF/mmWave Applications.” 2018 IEEE Radio Frequency Integrated Circuits Symposium (RFIC). IEEE, 2018; by Liang, Yuan, et al., “On-chip sub-terahertz surface plasmon polariton transmission lines with mode converter in CMOS.” Scientific reports 6 (2016): 30063; by Kazior, Thomas E. “More than Moore: III-V devices and Si CMOS get it together.” Electron Devices Meeting (IEDM), 2013 IEEE International. IEEE, 2013; by Kazior, T. E., et al., “High performance mixed signal and RF circuits enabled by the direct monolithic heterogeneous integration of GaN HEMTs and Si CMOS on a silicon substrate.” Compound Semiconductor Integrated Circuit Symposium (CSICS), 2011 IEEE. IEEE, 2011; by Kazior, Thomas E., et al. “More than Moore-Wafer Scale Integration of Dissimilar Materials on a Si Platform.” Compound Semiconductor Integrated Circuit Symposium (CSICS), 2015 IEEE. IEEE, 2015; by Bertozzi, Davide, et al., “The fast evolving landscape of on-chip communication.” Design Automation for Embedded Systems 19.1-2 (2015): 59-76; by Karkar, Ammar, et al., “Mixed wire and surface-wave communication fabrics for decentralized on-chip multicasting.” Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015. IEEE, 2015; by Karkar, Ammar, et al., “Hybrid wire-surface wave architecture for one-to-many communication in networks-on-chip.” Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014. IEEE, 2014; by Karkar, Ammar, et al., “A survey of emerging interconnects for on-chip efficient multicast and broadcast in many-cores.” IEEE Circuits and Systems Magazine 16.1 (2016): 58-72; by Karkar, Ammar, et al. “Network-on-chip multicast architectures using hybrid wire and surface-wave interconnects.” IEEE Transactions on Emerging Topics in Computing 6.3 (2018): 357-369; by Tiemeijer, Luuk F., et al. “Low-loss patterned ground shield interconnect transmission lines in advanced IC processes.” IEEE transactions on microwave theory and techniques 55.3 (2007): 561-570; by Kim, Jaewon, et al. “Novel CMOS low-loss transmission line structure.” Radio and Wireless Conference, 2004 IEEE. IEEE, 200; by Turner, Walker J., et al., “Ground-referenced signaling for intra-chip and short-reach chip-to-chip interconnects.” Custom Integrated Circuits Conference (CICC), 2018 IEEE. IEEE, 2018; by Hamieh, Mohamad, et al., “Sizing of the physical layer of a rf intra-chip communications.” Electronics, Circuits and Systems (ICECS), 2014 21st IEEE International Conference on. IEEE, 2014; by Agyeman, Michael Opoku, et al. “On the design of reliable hybrid wired-wireless network-on-chip architectures.” Embedded Multicore/Many-core Systems-on-Chip (MCSoC), 2015 IEEE 9th International Symposium on. IEEE, 2015; by Fesharaki, Faezeh, et al. “Guided-wave properties of mode-selective transmission line.” IEEE Access 6 (2018): 5379-5392; and in U.S. Pat. Nos. 8,889,548 and 9,405,064, all of the forgoing are incorporated herein by reference.
Accordingly, the interconnect fabric 3504, 3506 of
The use of RF could include use of differential signaling. Use of differential transmission lines could help reduce the cross talk effect and interference effect, allow lower voltages, and other advantages. The previous concepts for interconnection fabric could be adapted to use differential transmission line using techniques such as has been presented by Sai-Wang, et al. “A simultaneous tri-band on-chip RF-interconnect for future network-on-chip.” VLSI Circuits, 2009 Symposium on. IEEE, 2009, by Sawyer, Brett, et al. “Modeling, design, and demonstration of 2.5 D glass interposers for 16-channel 28 Gbps signaling applications.” Electronic Components and Technology Conference (ECTC), 2015 IEEE 65th. IEEE, 2015, by Sawyer, Brett, et al. “Design and demonstration of 2.5 D glass interposers as a superior alternative to silicon interposers for 28 Gbps signal transmission.” Electronic Components and Technology Conference (ECTC), 2016 IEEE 66th. IEEE, 2016, by Wary, Nijwm, and Pradip Mandal. “Current-Mode Triline Transceiver for Coded Differential Signaling Across On-Chip Global Interconnects.” IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25.9 (2017): 2575-2587, by Holloway, Jack W., et al. “A fully integrated broadband sub-mmwave chip-to-chip interconnect.” IEEE Transactions on Microwave Theory and Techniques 65.7 (2017): 2373-2386, by Alzahmi, Ahmed, et al. “High-performance RF-interconnect for 3D stacked memory.” SoC Design Conference (ISOCC), 2017International. IEEE, 2017, and by Akahoshi, Tomoyuki, et al. “Configuration for High-speed Transmission between Flip-chip Packages Using Low Loss and Flexible Substrate.” Transactions of The Japan Institute of Electronics Packaging 11 (2018): E17-016, all are incorporated herein by reference. And in U.S. Pat. Nos. 9,240,619, 9,071,476, and US patent applications 2016/0197761
Some of the incorporated by reference art, in here suggest the use of interposer, often reference as 2.5D, for chip to chip interconnect. The technology suggested herein is teaching a more effective technique, by adapting these interposer techniques to wafer level for layer transfer over the wafer with the chips to be interconnected. Wafer scale 3D integration of processing chips or cores or units could have as presented a full system 3D structure with good vertical connectivity. Adding the horizontal connectivity (X-Y) by layer transfer of RF circuits fabricated on a wafer such as RF-SOI with a connectivity fabric using layer transfer allows an effective wafer level processing of a fully connected 3D system. Such approaches need to accommodate non-perfect yield, mostly at the processor chip-core-unit level. The presented of techniques herein allow for overcoming such defects by: redundancy, repair, or skipping of such defective elements.
Similar to the concept of pre-testing the optical waveguide structure, so pretesting of the RF transmission line fabric can be engineered. In general these waveguides, whether optical or RF (transmission line), are far larger than advanced semiconductor features. They are hundreds of nanometers wide rather than tens of nanometers wide. The lithography process costs of RF transmission line fabrics can be far lower and the yield could be far higher than optical waveguide structures. Yet defects could still accrue and pretesting could allow avoiding use of defective fabrics. The pretesting could be assisted by dedicated test equipment or by on fabric self-test structures. Those could be engineered by artisans skilled in the art. The test infrastructure could be designed to use contacting probes or be wireless. Combining wireless testing to RF base interconnection fabric could leverage wireless charging, wireless test patterns in and wireless test patterns out using technologies well-known in the art. Pretesting could include special substrates with dedicated test utilities such as transmitters (Laser or RF) at the one end of the waveguides and receivers at the other ends. The connection for providing power and initiating self-test and receiving self-test results could use probes with physical contact to the tested wafer or wireless transmissions. The test elements could be embedded as part of the electromagnetic waves control electronic level, or a dedicated level dedicated for the testing. As a dedicated level it could be part of the substrate on which the wave guides are fabricated on with ‘cut-layer’ in between or brought over such as wafer bonding and de-bonding techniques. These choices could be engineered by artisan skilled in the art.
Wafer level 3D system as presented here could highly benefit with the ability to be configurable. Such flexibility could be used to support the continuous array concept such as has been presented in U.S. Pat. No. 8,395,191, incorporated by reference, in reference to
The 3D system could include in X-Y waveguides or transmission lines a configurable connectivity such as: Single Write Multiple Read (SWMR), Multiple Write Single Read (MWSR), or even Multiple Write Multiple Read (MWMR). Connectivity fabric wherein its waveguide/transmission lines are designed for MWMR, simplify the configuration of its resources by adapting who gets to ‘write’ into a specific waveguide and who gets to read based on considerations such as yield and sizing (customization). Such has been presented by Bribre, Alexandre, et al. “A dynamically reconfigurable rf noc for many-core.” Proceedings of the 25th edition on Great Lakes Symposium on VLSI. ACM, 2015; and by Agyeman, Michael Opoku, et al. “A resilient 2-d waveguide communication fabric for hybrid wired-wireless noc design.” IEEE Transactions on Parallel and Distributed Systems 28.2 (2017): 359-373, which suggest use of both wire and wireless RF base interconnect, Chang, M. Frank, et al. “CMP network-on-chip overlaid with multi-band RF-interconnect.” High Performance Computer Architecture, 2008. HPCA 2008. IEEE 14th International Symposium on. Ieee, 2008; Vivet, Pascal, et al. “Interconnect challenges for 3D multi-cores: From 3D network-on-chip to cache interconnects.” VLSI (ISVLSI), 2015 IEEE Computer Society Annual Symposium on. IEEE, 2015; and in U.S. Pat. Nos. 8,885,689, 9,160,627, and 9,515,367, all are incorporated herein by reference.
As an alternative, the configuring of the interconnect fabric during the setup process as discussed above could allow use of such waveguides resources for X-Y connectivity even in the simple mode of single input single output. These options could be engineered by artisan skilled in the art for the specific application for which the 3D system is being designed for.
The concept of wafer scale integration (“WSI”) has been considered and at times explored over many years. It was never adopted due to the challenge of defects and due to the success of scaling. There is more interest these days as conventional scaling has slowed. And with the growing interest with Artificial Intelligence (AI) and brain inspired architectures. Such concepts have been presented by Kumar, Arvind, et al. “Toward Human-Scale Brain Computing Using 3D Wafer Scale Integration.” ACM Journal on Emerging Technologies in Computing Systems (JETC) 13.3 (2017): 45; by Kumar, Arvind. “Nanotechnology requirements and challenges for large-scale brain computing.” Nanotechnology (IEEE-NANO), 2016 IEEE 16th International Conference on. IEEE, 2016, by Wan, Zhe. Three-Dimensional Wafer Scale Integration for Ultra-Large-Scale Neuromorphic Systems. Diss. UCLA, 2017; by Wan, Zhe, and Subramanian S. Iyer. “Three-dimensional wafer scale integration for ultra-large-scale cognitive systems.” SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2017IEEE. IEEE, 2017; by Uddin, Ashfaque, et al. “Wafer scale integration of CMOS chips for biomedical applications via self-aligned masking.” IEEE Transactions on Components, Packaging and Manufacturing Technology 1.12 (2011): 1996-2004; and by Schmitt, Sebastian, et al. “Neuromorphic hardware in the loop: Training a deep spiking network on the brainscales wafer-scale system.” Neural Networks (IJCNN), 2017 International Joint Conference on. IEEE, 2017; and U.S. Pat. Nos. 8,698,295 and 9,568,960, all are incorporated herein by reference. Herein the reference to wafer scale integration (“WSI”) could be considered as a general term to ultra-scale integration in which more than a reticle size device is constructed. It could be a rectangular device having size of more than 40×40 mm2, 80×80 mm2, 160×160 mm2 or full wafer size. Other shapes of devices are also possible, especially in the 3D context.
Some of the recent work suggests the use of optical waveguides in 3D architecture for WSI such as by Settaluri, Krishna T., et al. “Demonstration of an optical chip-to-chip link in a 3D integrated electronic-photonic platform.” European Solid-State Circuits Conference (ESSCIRC), ESSCIRC 2015-41st. IEEE, 2015; and by Stojanović, V., et al. “High-density 3D electronic-photonic integration.” Energy Efficient Electronic Systems (E3S), 2015 Fourth Berkeley Symposium on. IEEE, 2015, both are incorporated herein by reference. The concepts presented herein are advancing these ideas further supports low cost and effective integration with the current industry infrastructure.
The concepts presented herein in respect to the X-Y connectivity fabric were initially developed and presented with respect to 3D IC through many of the patents assigned to MonolithIC 3D Inc. and incorporated by reference herein. As an example in U.S. Pat. No. 8,395,191, incorporated by reference, the concept of programmable interconnects structure is presented in respect to its
These above concepts could be illustrated in reference to
This concept could be used in a similar way to the concept utilized in the memory business in which some memory cells (rows) are designated as redundancy to repair faulty memory cells, or as in agile design which can adapt to the number of functionally-yielding cores. These concepts could be engineered by an artisan skilled in the art to fit the choice of manufacturing and the required system characteristics.
Herein and in the related patents and applications fabrication process are presented using layer transfer. The electronics elements associated with the layer been transfer could be connected to the underline structure either by using hybrid bonding, having the appropriate connecting pads/pins, or by post process, etching via and forming conductive connection lines. In general hybrid bonding is a shorter and simpler process, while etch and deposition could support higher precision and more connections. The choice between these connecting technologies and the related techniques to overcome bonding misalignments could be engineered by an artisan skilled in the art to fit the specific application.
Herein and in the related patents and applications many 3D semiconductor devices and structures are presented. The reference to a device as 3D device indicates that the transistors included in the device are positioned at least on two overlaying planes (X-Y). In general, these devices are fabricated on round disk wafers in an X-Y plane with a disk diameter of about 100, 150, 200, 300 mm or even larger as future plans are for 400 mm. These wafers are relatively thin at about 0.7-0.9 mm in Z direction. Herein the term horizontal is in X-Y direction while vertical is in Z direction. Accordingly overlay, overlaying, underlying and so forth are in respect to the vertical direction −Z. In 3D devices, the transistors are in most cases being processed first on a wafer substrate that in most cases is a single crystal wafer, usually single crystal silicon. The term layer is used in most cases for such X-Y plane of a material with a functional structure such as isolation, connectivity strips, transistors and so forth. If such layer is combined with additional layers to form a plane of connected transistors it could be still called a layer but often it is called stratum, or tier, or layer, or level. Multiple stratums (strata) could be considered a 3D structure or a multilevel structure. The 3D structure could still be called a wafer but it also could be called a device. The wafer in most cases will be diced to many devices mostly with a rectangular shape which than could be packaged and integrated with other devices to form a system. Yet 3D devices could also be considered in many cases as 3D systems on their own. These terms and names are common in the art and in combination with other terms which could have similar meaning and could have been used herein too. The descriptions herein are to teach technologies and various innovations to an artisan skilled in the art. It is expected to teach the technological concept to engineers, who with the help of the accompanying drawings could make use of them to engineer the improved end products. The 3D system presented herein and the technologies suggested for the processing support the use of single crystal layer(s) and accordingly may include single crystal channel transistors. Such could be applied to the various levels of the 3D IC device starting from the base substrate. The use of single crystal materials are commonly and predominantly silicon; however, the use of single crystal materials described herein is not limited to silicon. As such, the use of poly crystalline or other form of materials, or types of material such as Germanium or alloys, for example, such as SiGe, could be integrated in the 3D system as presented herein or in the incorporated art. The concept of large scale integration such as multi dies, multi reticle, or wafer levels could leverage the presented 3D technologies but could be also implemented in conventional 2D devices.
3D Systems, for example, such as those presented herein commonly generate heat while in operation, which should be managed to protect the system from heating up and affecting the 3D system operation. The incorporated art herein suggests multiple techniques to provide heat removal for such a 3D system. These techniques include use of the through layers vias, the power grid, incorporating a heat spreader, absorbing and reflective layers, and so forth. In some systems additional techniques such as use of liquids combined with micro channel could be required. Such liquid based 3D device cooling are known in the art and have been presented such as in U.S. patent 7, 928,653, and as presented in the paper Bakir, Muhannad S., et al. “3D integrated circuits: liquid cooling and power delivery.” IETE Technical review 26.6 (2009): 407-416, both are incorporated herein by reference. These cooling techniques could be incorporated in the silicon substrate of the 3D IC device or in the interposer used to carry the device or in the package of the device. Recently a DARPA program named ICECool has been established to develop such cooling technologies as been reported in publications such as by Bar-Cohen1, Avram, Joseph J. Maurer, and Jonathan G. Felbinger. “DARPA's Intra/Interchip Embedded Cooling (ICECool) Program.”; and Bar-Cohen, A., J. J. Maurer, and D. H. Altman. “Gen3 embedded cooling for high power RE components.” Microwaves, Antennas, Communications and Electronic Systems (COMCAS), 2017 IEEE International Conference on. IEEE, 2017. Other work was presented by Kandlikar, Satish G. “Review and projections of integrated cooling systems for three-dimensional integrated circuits.” Journal of Electronic Packaging 136.2 (2014): 024001; by Chen, Gengjie, et al. “Minimizing thermal gradient and pumping power in 3D IC liquid cooling network design.” Proceedings of the 54th Annual Design Automation Conference 2017. ACM, 2017; by Serafy, Caleb M. Architectural-physical co-design of 3D CPUs with micro-fluidic cooling. Diss. 2016; by Drummond, Kevin P., et al. “A hierarchical manifold microchannel heat sink array for high-heat-flux two-phase cooling of electronics.” International Journal of Heat and Mass Transfer 117 (2018): 319-330; by Green, Craig, et al. “A review of two-phase forced cooling in three-dimensional stacked electronics: technology integration.” Journal of Electronic Packaging 137.4 (2015): 040802; by Zhang, Xuchen, et al. “3D IC with embedded microfluidic cooling: technology, thermal performance, and electrical implications.” ASME 2015 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems collocated with the ASME 2015 13th International Conference on Nanochannels, Microchannels, and Minichannels. American Society of Mechanical Engineers, 2015; and by Green, Craig, et al. “A review of two-phase forced cooling in three-dimensional stacked electronics: technology integration.” Journal of Electronic Packaging 137.4 (2015): 040802, all of the forgoing in this paragraph are incorporated herein by reference. These fluid cooling technologies could be a good fit to the large scale integration technologies presented herein, for example, with reference to
While
An alternative for the use of waveguides or transmission lines for ultra-scale (wafer scale) integration is to use wireless interconnects at the core to core level. Accordingly each core could have its own RF transmitter receiver and the data between cores could be exchanged using wireless communication without the need for physical connections between dies/reticle-step regions. Such ultra-scale integration could be established without the need for reticle ‘stitching’. Dicing the device edge could be achieved without the need of physical configuration to etch the waveguides or the transmission lines crossing the dicing lanes. The system customization could be performed by software network configuration. The device could be covered with an electromagnetic shield to keep such wireless connectivity confined within the device and protect against interference or ‘tampering’ or ‘spying’. It could be desired that each unit of these multi-core systems is powered independently to further support yield recovery, for example, by disabling faulty units. The use of wireless connectivity for Network on Chip (“NOC”) has been covered in many publications and could be adapted for such an ultra-scale integrated system. Such as in review papers by Xiao, Chunhua, Zhangqin Huang, and Da Li. “A tutorial for key problems in the design of hybrid hierarchical noc architectures with wireless/rf.” SmartCR 3.6 (2013): 425-436; by Deb, Sujay, et al. “Wireless NoC as interconnection backbone for multicore chips: Promises and challenges.” IEEE Journal on Emerging and Selected Topics in Circuits and Systems 2.2 (2012): 228-239; by Opoku Agyeman, Michael, et al. “Towards the practical design of performance-aware resilient wireless NoC architectures.” (2016); by Agyeman, Michael Opoku, Kenneth Tong, and Terrence Mak. “An Improved Wireless Communication Fabric for Performance Aware Network-on-Chip Architectures.” Int. J. Com. Dig. Sys 5.2 (2016); and by Achballah, Ahmed Ben, Slim Ben Othman, and Slim Ben Saoud. “An Extensive Review of Emerging Technology Networks-On-Chip Proposals.” Global Journal of Research In Engineering (2017); all of the forgoing in this paragraph are incorporated herein by reference.
Hybrid systems which combine wired and wireless could be constructed so to achieve a better mix between these technologies. Such a hybrid system has been covered by published work such as by Agyeman, Michael Opoku, et al. “Towards the practical design of performance-aware resilient wireless NoC architectures.” Cloud Computing, Data Science & Engineering-Confluence, 2017 7th International Conference on. IEEE, 2017; by Agyeman, Michael Opoku, et al. “On the design of reliable hybrid wired-wireless network-on-chip architectures.” Embedded Multicore/Many-core Systems-on-Chip (MCSoC), 2015 IEEE 9th International Symposium on. IEEE, 2015; and by Agyeman, Michael Opoku, et al. “A resilient 2-d waveguide communication fabric for hybrid wired-wireless noc design.” IEEE Transactions on Parallel and Distributed Systems 28.2 (2017): 359-373; all of the forgoing in this paragraph are incorporated herein by reference.
In such ultra-scale integration, power needs to be delivered to each unit. Metal interconnection could be used so wide metal lines could be used to form the primary power distribution network, distributing power provided through pads or balls from external sources to all units in the system. Alternatively each unit in the system could have its own pad or ball connected to the external power source.
The presented concept of Ultra Scale Integration herein is not limited to an array of computing cores and is not limited to an array in which all elements are of the same size, those could have been presented to illustrate the concept. Accordingly the elements 3822, 3824, 3826, 3828 of
The ultra-scale integration for wired as well as wireless on-chip interconnects could be extended further by utilizing, for example, a passive panel. The industry has been developing large panel manufacturing technology for applications such as flat panel displays and solar panels. These large panel technologies could be adapted to produce a large panel with waveguides or transmission lines. Array(s) of active device structures could be bonded onto such large panels. Such active device structures could be of a rectangular shape of more than 40×40 mm2, 80×80 mm2, 160×160 mm2 or even larger. The bonding could be hybrid bonding forming the connection from the active device to the waveguides or transmission lines. The alignment of the active device structure to the panel could be provided by the bonding equipment and could be assisted by adapting the electronic alignment techniques presented in PCT/US2018/52332 in reference to at least its
The large panels could be processed to also support liquid cooling. The liquid cooling concept presented herein in reference to
The waveguides/transmission lines interconnect fabric could be arranged so to follow a hierarchy; for example, such as presented in reference to
For electromagnetic waves at frequencies over about 100 GHz, sub-THz and THz region the preferred transmission lines becomes a dielectric interconnect channel. This could resemble the optical wave guides including the option to dice without pre-etching step. These type interconnect channel could be used in any of the techniques presented herein such as part of wafer transfer or device to panel level integration. Such sub-THz interconnection channel has been presented; for example, in papers by Yu, Bo, et al. “Sub-THz interconnect channel for planar chip-to-chip communication.” Electromagnetic Compatibility (EMC), 2016IEEE International Symposium on. IEEE, 2016; and Yu, Bo, et al. “Ortho-Mode Sub-THz Interconnect Channel for Planar Chip-to-Chip Communications.” IEEE Transactions on Microwave Theory and Techniques 66.4 (2018): 1864-1873; and Yu, Bo, et al. “High-efficiency micromachined sub-THz channels for low-cost interconnect for planar integrated circuits.” IEEE Transactions on Microwave Theory and Techniques 64.1 (2016): 96-105; by Myers, Joshua C., et al. “Investigation of modulation-capable silicon waveguides for efficient on-wafer terahertz interconnects.” Electronic Components and Technology Conference (ECTC), 2015 IEEE 65th. IEEE, 2015; by Kaur, Amanpreet, et al. “Affordable terahertz components using 3D printing.” Electronic Components and Technology Conference (ECTC), 2015 IEEE 65th. IEEE, 2015; by Yang, Xianbo, and Premjeet Prem Chahal. “On-wafer terahertz ribbon waveguides using polymer-ceramic nanocomposites.” IEEE Transactions on Components, Packaging and Manufacturing Technology 5.2 (2015): 245-255; by Yeh, Cavour, Fred Shimabukuro, and Peter H. Siegel. “Low-loss terahertz ribbon waveguides.” Applied optics 44.28 (2005): 5937-5946; and by Banan, Behnam. A Novel Electrical-Optical Interconnect. Diss. McGill University, 2016, all of the forgoing in this paragraph are incorporated herein by reference,
The design of the transmission line could take into account the losses of the line structure as the (target) transmission distance changes. It is common in the industry to use special substrates for RF applications, for example, such as RF-SOI. These substrates utilize high resistivity silicon to reduce the substrate related losses for better circuit performance. Recent work suggests further reduction of substrate related losses could be achieved by use of a carrier lifetime modulating process step, for example, such as an anodizing etch forming porous silicon to lower transmission losses, and then oxidizing the porous silicon to gain an even further reduction; such as presented in a paper by Sarafis, Panagiotis, and Androula G. Nassiopoulou. “Porous Si as a substrate for the monolithic integration of RF and millimeter-wave passive devices (transmission lines, inductors, filters, and antennas): Current state-of-art and perspectives.” Applied Physics Reviews 4.3 (2017): 031102; by Issa, Hamza, et al. “On-chip high-performance millimeter-wave transmission lines on locally grown porous silicon areas.” IEEE Transactions on Electron Devices 58.11 (2011): 3720-3724; and by Gautier, G., and P. Leduc. “Porous silicon for electrical isolation in radio frequency devices: A review.” Applied Physics Reviews 1.1 (2014): 011101; all are incorporated herein by reference.
With 3D integration, such as, by using layer transfer, there are additional options to reduce the substrate effects on the transmission lines.
Additional alternative is to add level utilizing die to wafer bonding such as detailed in U.S. Pat. No. 9,721,927 incorporated herein by reference. Such could be utilized for incorporating a mix technology such as transferring a level from a 200 mm wafer on to 300 mm wafer. The transfer device could be a reticle size or other size or shape (5×5 mm2, 10×10 mm2, 20×20 mm2 40×40 mm2 100×100 mm2 or not even rectangular shape, such as hexagon shapes). Additional motivation could be to use ‘Known-Good-Die’ in consideration for yield. The mixed wafer size could be useful for optic based X-Y interconnect as those could utilize non-silicon wafers known to be preferred for optical element such as laser and better available on smaller diameter wafer such as 200 mm (8″) or 150 mm (6″) wafer.
Such mixed 3D integration could be done at the wafer level or even at the panel level wherein on a top section some of the sections transferred could be of different sizes. The process could include a step of filling with smoothing material such as oxide and CMP preparing the upper surface for the following level/layer transfer. Such could include a step to support the connectivity pins for the vertical connectivity.
It will also be appreciated by persons of ordinary skill in the art that the invention is not limited to what has been particularly shown and described hereinabove. For example, the use of SiGe as the designated sacrificial layer or etch stop layer could be replaced by compatible material or combination of other material including additive materials to SiGe like carbon or various doping materials such as boron or other variations. And for example, drawings or illustrations may not show n or p wells for clarity in illustration. Further, any transferred layer or donor substrate or wafer preparation illustrated or discussed herein may include one or more undoped regions or layers of semiconductor material. Further, transferred layer or layers may have regions of STI or other transistor elements within it or on it when transferred. Rather, the scope of the invention includes combinations and sub-combinations of the various features described hereinabove as well as modifications and variations which would occur to such skilled persons upon reading the foregoing description. Thus, the invention is to be limited only by appended claims.
| Number | Date | Country | |
|---|---|---|---|
| 62824288 | Mar 2019 | US | |
| 62770751 | Nov 2018 | US | |
| 62767490 | Nov 2018 | US | |
| 62733005 | Sep 2018 | US | |
| 62726969 | Sep 2018 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 18106484 | Feb 2023 | US |
| Child | 18786372 | US | |
| Parent | 17396646 | Aug 2021 | US |
| Child | 18106484 | US | |
| Parent | 16558304 | Sep 2019 | US |
| Child | 17396646 | US |
