Patent Application
20160133695
The present application claims priority of Chinese Patent Application (No. 201310571563.1) filed on Nov. 13, 2013, which is incorporated herein by reference in its entirety.
The invention belongs to a field of a field effect transistor logic device and the circuit in connection with CMOS ultra large scale integrated circuit (ULSI), and particularly refers to a method of inhibiting tunneling transistor leakage current, and the corresponding device and a preparation method thereof.
Under the drive of Moore's Law, the feature size of the conventional MOSFET continually shrink and now has progressed to the nanometer scale, consequently, the negative effects such as short channel effect of a device and so on have become more serious. The effects such as drain induced barrier lowering, band-to-band tunneling and so on cause a off-state leakage current of a device to increase continually, and at the same time, a sub-threshold slope of the conventional MOSFET can not decrease synchronously with the shrink of the device size due to the limitation by the thermal potential, and thereby the device power consumption increases. Now the power consumption concern has become the most serious problem of limiting the device shrink.
In order to enable the device to be applied in the field of ultra-low voltage and low power consumption, achievement of a device structure with ultra-steep sub-threshold slope based on a new turn-on mechanism and a process and preparation method thereof have become the focus drawing everyone's attentions to small size devices. In recent years, researchers have proposed a possible solution of using tunneling field effect transistor (TFET). Not like the conventional MOSFET, TFET has source and drain with opposite doping types each other, can control the band-to-band tunneling of the reverse biased PIN junction by gate to achieve turn-on, can break through the limitation of the sub-threshold slope 60 mV/dec of the conventional MOSFET, and has a very small leakage current in the cases of long channel. TFET has many advantages such as low leakage current, low sub-threshold slope, low operating voltage and low power consumption, and so on. However, due to the limitation of source junction tunneling probability and tunneling area, TFET is faced with an issue of small on-state current, which greatly limits the applications of TFET devices. In addition, for small size TFET, when the gate length is less than about 20 nm, the direct band-to-band tunneling current from source to drain in bulk region may increase sharply, so that the leakage current and sub-threshold slope of TEFT devices degrade seriously. TFET adopting ultra-thin bulk SOI substrate can inhibit this short channel effect in some extent, but due to the presence of the buried oxide layer under thin silicon film, thermal dissipation problem will become a major issue that the self-heating effect is serious, which affects the device characteristics, and at the same time the requirements of thin silicon film also increase the process complexity of the device.
The purpose of the present invention is to provide a method of inhibiting a leakage current of a tunneling transistor, and the corresponding device and a preparation method thereof. The method may inhibit effectively the leakage current from source-to-drain direct tunneling in the small size TEFT device while improving effectively the sub-threshold slope by interposing an insulating layer between a source region and a bulk region under a tunneling junction and no insulating layer in the tunneling junction between the source region and a channel. The preparation method of the corresponding device is fully compatible with the existing CMOS process.
The technical solutions of the present invention are provided as follows.
A tunneling transistor according to the present invention includes a high resistance semiconductor substrate (1), a highly-doped source region (10), a lowly-doped drain region (11), a gate dielectric layer (3) and a control gate (4). A tunneling junction of the tunneling transistor is formed between the highly-doped source region (10) and channel and has a thickness h of 5-10 nm, and an insulating layer (7) is provided between the highly-doped source region (10) and the high resistance semiconductor substrate (1) under the tunneling junction and has a thickness of 50-500 nm. The doped source region and the doped drain region are disposed on both sides of the control gate, respectively, and have the doping types opposite to each other and different doping concentrations from each other. For the N-type transistor, the source region is a highly-doped P+ source region and has a doping concentration between 5×1019 cm−3 and 1×1021 cm−3, and the drain region is a lowly-doped N drain region and has a doping concentration between 1×1018 cm−3 and 1×1019 cm−3. For a P-type transistor, the source region is a highly-doped N+ source region and has a doping concentration between 5×1019cm−3 and 1×1021cm−3, and the drain region is a lowly-doped P drain region and has a doping concentration between 1×1018cm−3 and 1×1019cm−3. The high resistance semiconductor is lightly doped, with the same doping type as that of the source region, and has a doping concentration less than 1×1017cm−3.
A preparation method of the tunneling transistor described above comprises the steps of:
(1) defining an active region by shallow trench isolation in a high resistance semiconductor substrate;
(2) growing a gate dielectric layer, and depositing a control gate material and a hard mask layer;
(3) performing photolithography and etching to form a pattern for control gate, and using sidewall process to form a layer of thin sidewall protection structure, wherein a thickness of the thin sidewall determines the distance from a source junction to the edge of the control gate depending on the design;
(4) exposing a source region by photolithography, anisotropically etching, with an etching depth as a thickness h of the tunneling junction, the silicon in the source region using a gate sidewall as a protection layer; then depositing an oxidation resistant material, performing photolithography to expose the source region again, anisotropically etching the oxidation resistant material to form a single side oxidation resistant sidewall;
(5) further anisotropically etching the silicon in the source region to form a recessed silicon trench structure using the oxidation resistant sidewall for protection; oxidizing the exposed silicon to form an insulating layer;
(6) removing an oxidation resistant layer, then depositing a source material, and overetching the source material till the surface of a channel;
(7) exposing the source region by photolithography, and forming a highly-doped source region by performing ion implantation using photoresist and the control gate as a mask; then exposing the drain region by photolithography, and forming a lowly-doped drain region with the other doping type by performing ion implantation using photoresist and the control gate as a mask; and then performing rapid high temperature thermal annealing to activate the doped impurities for source/drain;
(8) finally proceeding to a general CMOS Back-End-Of-Line, comprising depositing a passivation layer, opening contact holes and performing metallization, so that the tunneling field effect transistor is prepared, as shown in
In the preparation method described above, a material for the semiconductor substrate in the step (1) is selected from a group consisting of Si, Ge, SiGe, GaAs, and the other binary or ternary compound semiconductor in II-VI, III-V and IV-IV groups, silicon on insulator (SOI) and germanium on insulator (GOI).
In the preparation method described above, a material for the gate dielectric layer in the step (2) is selected from a group consisting of SiO2, Si3N4, and high-K gate dielectric material.
In the preparation method described above, growing of the gate dielectric layer in the step (2) is performed by a process selected from a group consisting of: general thermal oxidation, nitrogen-doped thermal oxidation, chemical vapor deposition and physical vapor deposition.
In the preparation method described above, the control gate material in the step (2) is selected from a group consisting of doped polysilicon, metal cobalt, nickel and the other metal or metal silicide.
In the preparation method described above, a material for the thin sidewall in the step (3) is oxide such as SiO2 and so on.
In the preparation method described above, the oxidation resistant material in the step (4) is a dysoxidizable material such as Si3N4 and so on.
In the preparation method described above, the source/drain material in the step (6) is selected from a group consisting of polysilicon, Ge, SiGe, GaAs, and the other binary or ternary compound semiconductor in II-VI, III-V and IV-IV groups.
The method of inhibiting a leakage current of a tunneling transistor specially comprise the following steps: providing an insulating layer under a tunneling junction of a tunneling transistor, where the insulating layer is disposed between a source region and a bulk region under a channel, so that the leakage current from source-to-drain direct tunneling of the tunneling transistor is inhibited using the insulating layer.
The present invention has the technical effects as follows:
Firstly, the method of the present invention may decrease effectively a small size
TFET device's probability of direct band-to-band tunneling from the source to the drain by introduction of an insulating layer under a tunneling junction, thereby inhibiting a tunneling leakage current of the tunneling transistor and obtaining a lower off-state current. Furthermore, an electric field centralization effect of the insulating layer enables the device to obtain a higher electric field than the traditional TFET when the band-to-band tunneling occurs, thereby improving sub-threshold characteristics of the TFET device.
Secondly, the tunneling transistor prepared by the method of the present invention has a highly-doped source region and a lowly-doped drain region, wherein the source region has a doping concentration between 5×1019cm−3 and 1×1021cm−3, the drain region has a doping concentration between 1×1018cm−3 and 1×1019cm−3, and the doping type of the source region is opposite to that of the drain region, the substrate is lightly doped, with a doping type being same as the doping type of the source region, and has a doping concentration less than 1×1017cm−3. The transistor can turn on using the band-to-band tunneling mechanism in connection with the tunneling junction, and can break through the limitation of the sub-threshold slope of the MOSFET to obtain the steeper sub-threshold characteristics than the conventional TEFT device and MOSFET device. The low concentration doping for drain region can also reduce effectively the probability of band-to-band tunneling in the drain junction so as to inhibit the tunneling current in the drain junction, and thereby can inhibit an ambipolar effect of the device. In addition, because the semiconductor substrate of the tunneling transistor of the present invention is lightly doped and the doping type thereof is the same as the doping type of the source, the tunneling transistor is a three-terminal device where the substrate is biased directly via the source junction, and can obtain a smaller layout area and a higher integration density compared with a MOSFET as a four-terminal device. Moreover, the tunneling transistor of present invention can solve effectively the issue of thermal dissipation of SOI structure to inhibit the self-heating effect compared with the conventional SOI TFET structure.
Thirdly, the preparation method of the corresponding tunneling transistor in connection with the method of the present invention is fully compatible with the conventional CMOS process. The thickness of the tunneling junction is determined by the etching process, and thus the requirement for a thin film process is relieved compared with SOI TFET structure. Furthermore, in the preparation method, lastly depositing of the source material can facilitate to the design for hetero-junction of TFET and can accurately control the location of the hetero-junction of TFET. The hetero-junction TFET has a steeper tunneling junction and a smaller tunneling barrier width compared with homo-junction TFET, so the device can obtain a higher turn-on current and a steeper sub-threshold slope.
In short, the method of the present invention can inhibit effectively the leakage current from source-to-drain direct tunneling of TFET in the small size, and on the other hand can also obtain a larger tunneling electric field, and thereby improve the sub-threshold characteristic of TFET device. The tunneling transistor prepared by using this method may also inhibit the ambipolar effect of the device, has a smaller layout area and a higher integration density, and the preparation process is fully compatible with the existing CMOS process, and thus the device can be expected to be applied in the field of the low power consumption and has a higher practical value.
In the drawings:
Hereinafter, the present invention will be further described with respect to the examples. It is noted that, the embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art, and it will be appreciated to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope defined by the present invention and the accompanying claims. Accordingly, the present invention should not be construed as being limited to the embodiments, and the protected scope of the present invention should be defined by the claims.
A specific example of the preparation method according to the present invention includes the process steps shown in
1. Selecting a bulk silicon wafer with a crystal orientation (100) as a silicon substrate 1, forming an isolation layer 2 for active region on the silicon substrate 1 using a shallow trench isolation technology, wherein the silicon substrate is lightly doped with respect to a doping concentration, as shown in
2. Then thermally growing a gate dielectric layer 3, wherein the gate dielectric layer is SiO2 and has a thickness of 1-5 nm; depositing a gate electrode layer 4 and a gate hard mask layer 5, wherein the gate electrode layer is a doped polysilicon layer and has a thickness of 150-300 nm, and the hard mask layer is SiO2 and has a thickness of 100-200 nm; defining a pattern for control gate by photolithography, and etching the gate hard mask layer 5 and the gate electrode layer 4 till the gate dielectric layer 3; depositing a thin layer of SiO2, with a thickness of 30 nm, using LPCVD process to cover a gate structure, and then forming the gate structure with thin sidewalls for protection using a dry etching, as shown in
3. Exposing a pattern for source region by photolithography, anisotropically etching, with an etching depth of 10 nm, the silicon of source region using the gate sidewall as a protection layer, and removing a photoresist; then depositing Si3N4 with a thickness of 50-100 nm, exposing again the source region by photolithography, anisotropically etching Si3N4 to form a single side oxidation resistant sidewall 6, and removing a photoresist, as shown in
4. Further anisotropically etching, with an etching depth is 20-100 nm, the silicon of the source region to form a recessed silicon trench structure using Si3N4 for protection; then oxidizing the exposed silicon to form a SiO2 layer, that is, a insulating layer 7, wherein the SiO2 layer has a thickness of 50-100 nm, as shown in
5. Depositing a thick layer of polysilicon material 8 by LPCVD, as shown in
6. Exposing the source region by photolithography, and performing P+ ion implantation by using a photoresist 9 and the gate region as a mask to form a highly-doped source region 10, wherein an ion implanting energy is 40 keV, and an implanting impurity is BF2+, as shown in
7. Exposing a drain region by photolithography, and performing N ion implantation by using a photoresist 9 and a gate region as a mask to form a lowly-doped drain region 11, where an ion implanting energy is 50 keV and an implanting impurity is As+, as shown in
8. Finally proceeding to a general CMOS Back-End-Of-Line, comprising depositing a passivation layer, opening contact hole, and performing metallization, so that the tunneling transistor is prepared, as shown in
Although the present invention has been described with respect to the preferred embodiment as above, however, it is not intended to limit the present invention. Without departing from the scope of the present invention technical solution, using the technical method and technical contents disclosed above, Various changes and modifications for the present technical solution may be made or equivalent embodiments may be obtained by those skilled in the art in view of the method and technical contents disclosed above, without departing from the scope of the present invention. Therefore, any simple changes, equivalent changes and modifications made to the above embodiments according to the present invention technical spirit without departing from the spirit of the present invention all falls into the protection scope of the present invention.
| Number | Date | Country | Kind |
|---|---|---|---|
| 201310571563.1 | Nov 2013 | CN | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/CN2014/070364 | 1/9/2014 | WO | 00 |
