Patent Application
20050087517
1. Field of the Invention
This invention relates to layers in microelectronic circuits, and more particularly to adhesion strength between layers of microelectronic circuits.
During fabrication of the package assembly 100, the package 110 and die 102 may be raised to an elevated temperature. Subsequently, as the temperature decreases, the package 110 and die 102 may have different coefficients of thermal expansion and/or may cool at different rates. This may cause stresses to occur between the package 110 and the die 102 and/or within the die 102, such as at the interface 108 between the etch stop layer 104 and the substrate layer 106.
In conventional package assemblies 100, the connectors 112 may be solder balls that comprise a lead-tin alloy. Such connectors 112 are relatively soft. Stresses generated by differing coefficients of thermal expansion and/or cooling rates between the package 110 and the die 102 may cause such soft solder ball connectors 112 to deform. This deformation may act to reduce stresses acting on the interface 108 between layers 104, 106 in the die 102.
The present invention is illustrated by way of example and is not limited in the figures of the accompanying drawings, in which like references indicate similar elements. Features shown in the drawings are not intended to be drawn to scale, nor are they intended to be shown in precise positional relationship.
a through 3d are cross sectional side views that illustrate how a die may be fabricated with a stronger interface between a substrate and etch stop layer.
In the following detailed description of embodiments of the invention, reference is made to the accompanying drawings in which like references indicate similar elements. The illustrative embodiments described herein are disclosed in sufficient detail to enable those skilled in the art to practice the invention. The following detailed description is therefore not to be taken in a limiting sense, and the scope of the invention is defined only by the appended claims.
The die 202 may include a substrate 204. In an embodiment, the substrate 204 may include carbon doped oxide (“CDO”) material at a top surface. This CDO material may act as a dielectric with a low dielectric constant (a low “k”). Above the substrate 204 may be an etch stop layer 206. Alternatively, the etch stop layer 206 may be a diffusion barrier layer 206. The term “etch stop layer” will therefore refer to both an etch stop layer and a diffusion barrier layer. In some embodiments, the etch stop layer 206 may comprise a material such as SiN or SiC. There may be an interface 208 between the etch stop layer 206 and the substrate 204. Stiff connectors 216, such as copper connectors 216, may cause relatively high stresses to act on the interface 208. The interface 208 may be strengthened so that it may withstand increased stress resulting to that the etch stop layer 206 remains adhered to the substrate 204. Such a strengthening may be achieved through modifying a portion of the substrate 204 to increase adhesion between the substrate 204 and the etch stop layer 206.
There may also be an interlayer dielectric (“ILD”) layer 210 above the etch stop layer 206. The ILD layer 210 may comprise a material with a low k, such as SiO2, SiOF, CDO, polymer-containing dielectrics, or other dielectric materials. Extending through the ILD layer 210 and the etch stop layer 206 may be a via or interconnect 216. The via 216 may comprise a conductive material such as aluminum, copper, or other conductive materials. This via 216 may electrically connect a conductor on the top surface of the substrate 204 to a connector 216. This connector 216 may then electrically connect the conductor on the top surface of the substrate to a conductor in the package 214.
a through 3d are cross sectional side views that illustrate how a die 202 may be fabricated with a stronger interface 208 between a substrate 204 and etch stop layer 206, according to one embodiment. This may be done by use of a plasma enhanced chemical vapor deposition (“PECVD”) treatment, where hydrogen plasma is used to modify carbon doped oxide (“CDO”) material in the substrate 204.
a is a cross sectional side view that illustrates the substrate 204 according to one embodiment. The substrate 204 may be any layer generated when making an integrated circuit. The substrate 204 thus may comprise, for example, active and passive devices that are formed on a silicon wafer, such as transistors, capacitors, resistors, diffused junctions, gate electrodes, local interconnects, or other structures. The substrate 204 may also comprise insulating materials (e.g., silicon dioxide, either undoped or doped with phosphorus or boron and phosphorus; silicon nitride; silicon oxynitride; or a polymer), and may comprise other formed materials. The substrate 204 may include CDO material at a top surface, along with patterned conductors.
b is a cross sectional side view that illustrates the substrate 204 after it has been modified to increase the strength of the interface 208 according to one embodiment. The substrate 204 may be modified by a plasma treatment. In an embodiment, the substrate 204 may be modified by a PECVD treatment. The substrate 204 may be placed in a plasma chamber for modification as part of a wafer that comprises a number of substrates 204, prior to singulation of the wafer. In an embodiment, several wafers, each with multiple substrates 204 may be placed in the plasma chamber for modification. In an embodiment, four wafers may be placed in the plasma chamber for modification. In an embodiment, the wafers may have a diameter of 300 millimeters.
The substrate 204 may be brought to a temperature in a range from about 200 degrees Celsius to about 450 degrees Celsius. In an embodiment, the substrate 204 may be brought to a temperature of about 400 degrees Celsius. A flow of hydrogen may be introduced into the plasma chamber. In some embodiments, the flow of hydrogen into the plasma chamber may have a flow rate in a range of about 0.1 liter per minute to about 10 liters per minute. In an embodiment, the flow of hydrogen into the plasma chamber may have a flow rate of about 1 liter per minute. A flow of helium, ammonia, and/or nitrogen or another reducing or inert gas may also be introduced into the plasma chamber. In some embodiments, the chamber may have a pressure in a range from about 1 Torr to about 10 Torr. In some embodiments, the chamber may have a pressure in a range from about 2 Torr to about 5 Torr. In an embodiment, the chamber may have a pressure of about 2.5 Torr. In an embodiment, the plasma chamber may be ramped up to the pressure from a lower starting pressure. A radio frequency (“RF”) power source may apply RF power to the plasma chamber to strike a plasma. In some embodiments with a 300 mm wafer, the radio frequency power source may apply a power in a range from about 200 Watts to about 1000 Watts. In some embodiments, the radio frequency power source may apply a power in a range from about 400 Watts to about 600 Watts. In an embodiment, the radio frequency power source may apply a power of about 500 Watts. In some embodiments, the power may be applied for a time in a range from about 4 seconds to about 30 seconds. In some embodiments, the power may be applied for a time in a range from about 10 seconds to about 15 seconds. In an embodiment, the power may be applied for about 12 seconds.
This may result in a hydrogen plasma flowing over CDO material in the substrate. The hydrogen plasma may remove methyl groups from CDO within the substrate. In an embodiment, the longer the hydrogen plasma treatment, the fewer methyl groups remain.
Returning to
c is a cross sectional side view that illustrates the substrate 204 after an etch stop layer 206 has been deposited on the substrate 204 according to one embodiment. In an embodiment, the etch stop layer 206 may be deposited on the substrate 204 while the substrate 204 is in the same plasma chamber in which the graded modified region 302 was created, and the etch stop layer 206 may be deposited at the same temperature at which the substrate 204 was modified to create the graded modified layer 302. The etch stop layer 206 may comprise a material such as SiN or SiC. There may be an interface 208 between the etch stop layer 206 and the substrate 204. Modifying the substrate 204 to create the graded modified layer 302 may cause the interface between the etch stop layer 206 and the substrate 204 to be stronger than it would be otherwise, so that the etch stop layer 206 may be adhered more strongly to the substrate 204.
d is a cross sectional side view that illustrates the die 202 after an ILD layer 210 and via 212 have been formed, according to one embodiment. The ILD layer 210, the via 212, and/or other structures may be formed using known methods. While an ILD layer 210 and via 212 are shown in
While the foregoing description discusses strengthening an interface 208 between a substrate 204 and an etch stop layer 206, other interfaces may also be strengthened. CDO material in a layer, film, or other form may be treated by hydrogen plasma to remove methyl groups. An etch stop or diffusion barrier layer, such as ones that comprise SiN, SiON or SiC may be deposited on the modified CDO material. The interface between the CDO and etch stop or diffusion barrier layer may be stronger than if the CDO material had not been modified. Alternatively, other ILD's with organic functional groups, such as low k spin on dielectrics or porous CDO films can be modified in this manner to improve adhesion between the etch stop layer and ILD layer. In such embodiments, hydrogen plasma treatment may be used to remove the organic functional groups from a region near the surface of the material, which may result in a graded region with fewer organic functional group near the surface. Finally, this technique could be used to improve the adhesion between ILD layers for integration schemes where an etch stop layer 206 is not needed.
The foregoing description of the embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. This description and the claims following include terms, such as left, right, over, under, upper, lower, first, second, etc. that are used for descriptive purposes only and are not to be construed as limiting. The embodiments of a device or article described herein can be manufactured, used, or shipped in a number of positions and orientations. Persons skilled in the relevant art can appreciate that many modifications and variations are possible in light of the above teaching. Persons skilled in the art will recognize various equivalent combinations and substitutions for various components shown in the Figures. It is therefore intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto.
