Patent Application
20120204941
This application is directed, in general, to photovoltaic cells, and methods of making such cells.
The development of renewable energy sources is expected to become increasingly urgent as fossil energy sources dwindle and concern over CO2 emissions increases. Solar, or photovoltaic cells, have become increasingly efficient as researchers make incremental improvements, and increasingly cost effective as the cost of energy from other sources rises. However, the efficiency of some (e.g. silicon homojunction) solar cells is only in the range of 5%. Heterojunction photovoltaic cells may have a greater efficiency, but may benefit from further improvement of methods of forming these cells before being widely adopted.
One aspect provides a method of forming a photovoltaic cell. The method includes providing a substrate. A crystalline semiconductor layer is formed thereover. The crystalline semiconductor layer is heated above a melting temperature of the semiconductor. A portion of the crystalline semiconductor layer is thereby converted to a quenched amorphous semiconductor layer.
Another embodiment provides a photovoltaic cell. The cell includes a substrate. An amorphous semiconductor layer is located over the substrate. The amorphous semiconductor layer is formed by heating a surface of a crystalline semiconductor layer above a melting point of the semiconductor. The heating converts at least a portion of the crystalline semiconductor layer to an amorphous allotrope of the semiconductor.
Yet another embodiment provides a photovoltaic cell. The photovoltaic cell includes a layer of a crystalline semiconductor material over a substrate. The crystalline semiconductor material has a first conductivity type. A quenched amorphous layer of the semiconductor material is located over the substrate. The quenched amorphous layer has a second different conductivity type. The quenched amorphous layer comprises no more than about 0.1 at. % hydrogen.
Another embodiment provides a semiconductor wafer. The wafer includes a crystalline semiconductor substrate with an amorphous semiconductor layer located thereover. The amorphous semiconductor layer is formed by heating a surface of a crystalline semiconductor layer above a melting point of the semiconductor. The heating converts at least a portion of the crystalline semiconductor layer to an amorphous allotrope of the semiconductor.
Various features of the accompanying drawings may not be drawn to scale. In some cases the dimensions of various features may be arbitrarily increased or reduced for clarity of discussion. No limitation on the thickness of any material layers is implied by relative thicknesses of features as illustrated. Reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
One type of heterojunction photovoltaic (PV) cell that has shown promise for greater efficiency is the “heterojunction with intrinsic thin layer” (HIT) cell. Some such cells currently may have an efficiency of about 20%. However, they are more expensive to produce than simpler PV cell types. Forming HIT cells typically includes multiple passes through an amorphous silicon deposition chamber. These steps add considerable cost to the HIT cell, thus increasing the initial investment required to install a system of such cells, and increasing the payback period of the system. Moreover, amorphous silicon formed by such conventional methods typically includes hydrogen as an impurity. The hydrogen concentration often changes over time, rendering the electrical properties of the cell unstable. This instability may reduce the useful life of a PV cell, thereby increasing the operating cost over the lifetime of the cell.
This disclosure provides improved methods of forming a PV cell, and improved PV cells. The improvements are based on the recognition on the part of the inventors that an amorphous semiconductor layer may be formed on a crystalline semiconductor layer by illuminating the crystalline semiconductor layer with high-intensity light to cause localized melting, and quenching the molten semiconductor. Amorphous semiconductor layers formed using methods of the disclosure in some cases may have greater purity than such layers formed by conventional methods, and in some cases may be formed less expensively than those formed by conventional methods. Thus, electrical stability may be improved and/or the cost of producing the cell may be reduced. Even in embodiments in which the semiconductor layer impurities are not reduced relative to conventional PV cells, PV cells of the disclosure are expected to benefit from improved control of the thickness of amorphous semiconductor layers. Such control is expected to result in superior yield and/or operating characteristics of PV cells formed by the disclosed methods.
The disclosure includes references to various forms of semiconductor materials. While the discussion is not limited to a particular semiconductor material, for convenience the discussion may refer to silicon without limitation. The following convention is followed throughout with respect to various forms of silicon:
a-Si: designates the amorphous morphology allotrope of silicon;
c-Si: designates the single-crystalline morphology allotrope of silicon; and
p-Si: designates the polycrystalline morphology allotrope of silicon.
Herein, allotrope refers to a form of an elemental or compound semiconductor determined by an arrangement of chemical bonds between atoms of the semiconductor. More specifically, crystalline and polycrystalline materials are one allotropic form of silicon while amorphous material is a second different allotropic form. Herein, different allotropes of a semiconductor also have a different morphology. Single crystal silicon and polycrystalline silicon are of the same allotrope, but have differing morphologies.
Herein a conductivity type of a semiconductor material refers to conductivity that predominantly occurs by electron conduction or by hole conduction. Thus, an n-type semiconductor has a first conductivity type, and a p-type semiconductor has a second different conductivity type. For the purposes of the disclosure, an intrinsic semiconductor, e.g. having about a same concentration of holes and electrons, has a third conductivity type that is different from the n-type and p-type semiconductors.
The HIT cell 100 represents a significant advancement in photovoltaic energy production. However, the high cost of production renders the cell 100 uneconomical for many applications. The high cost is due in part to the cost of forming the amorphous layers 120, 130, 140, 150.
Typically, an amorphous semiconductor layer, such as silicon, is deposited in a chemical-vapor-deposition (CVD) process. For example, a-Si may be formed in a conventional process using a silane (SiH4) feedstock. The silane may be doped in situ to result in an n-type or p-type a-Si layer if desired, such as for the amorphous layers 130, 150. However, each amorphous layer 120, 130, 140, 150 typically must be formed in a separate process. Thus, for example, the cell 100 may require four separate processes to produce the amorphous layers 120, 130, 140, 150. Furthermore, because amorphous semiconductor layers are typically formed using a hydrogen-containing compound of the semiconductor element (e.g., silane, germane), the amorphous layers 120, 130, 140, 150 may contain significant amounts of residual hydrogen. In some cases, for instance, a-Si may contain as much as about 30 at. % hydrogen. While hydrogen may be beneficial in some respects, loss of hydrogen over time is generally associated with unstable electrical characteristics.
PCT Application No. PCT/US2008/076976 (the '976 Application), incorporated herein by reference in its entirety, discloses a method of employing a laser to convert a portion of a semiconductor substrate from a crystalline allotrope to an amorphous allotrope.
The underlying crystalline silicon substrate 210 is typically substantially free of hydrogen, e.g. less than about 1 at. %. Because the quenched amorphous silicon layer 220 is formed from the silicon substrate 210, the quenched amorphous silicon layer 220 is also substantially free of hydrogen, e.g. having no greater than about 1 at. %, and in some embodiments has no more than about 0.1 at. % hydrogen. This hydrogen concentration represents a reduction of hydrogen concentration relative to CVD a-Si by a factor of at least 30-300. Thus the electronic properties of the quenched amorphous silicon layer 220 are expected to be more stable than the conventional amorphous layers used in PV cells.
Herein, a quenched amorphous semiconductor layer is a layer characterized by including little or no crystalline ordering. Some semiconductor processes, e.g. implantation, result in some disordering of the semiconductor lattice. Such disordering is typically minor compared to a quenched amorphous semiconductor. For instance, a semiconductor lattice damaged by implantation is expected to display an x-ray or electron diffraction pattern that is dominated by a peak associated with long-range ordering of the underlying lattice. While disorder may result in reduced intensity and broadening of the peak, the peak is expected to remain a dominant feature of the diffraction pattern. In contrast a quenched amorphous semiconductor is expected to be characterized by a diffraction pattern with little or no ordering peak.
The quenched amorphous semiconductor layer may also be distinguished from a damaged semiconductor lattice by transmission electron microscopy (TEM) analysis. High resolution TEM is capable of sufficiently resolving a crystalline semiconductor lattice that the underlying periodicity of the lattice is expected to be evident in a TEM cross section of an implanted semiconductor lattice, even when the implanted dopant concentration is high. On the contrary, a TEM cross section of a quenched amorphous semiconductor layer is expected to show little or no long-range ordering of the layer. While some small and isolated regions of local ordering are possible, such regions while remaining isolated are not inconsistent with characterization of the quenched amorphous layer as amorphous.
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The semiconductor substrate 310 may be any substrate suitable to mechanically support subsequent material layers, as described below, including for example a semiconductor wafer, glass, ceramic or quartz. In some embodiments, such as the illustrated embodiment, the substrate is a semiconductor layer that provides one terminal (e.g. a bottom terminal) of the PV cell 300. In other embodiments the bottom terminal of the PV cell 300 may be, e.g. a transparent conductor such as ITO or other similar material formed on an insulating substrate such as glass. In such embodiments electrical access to the bottom terminal (e.g. ITO) may be made, e.g., by etching an opening through the insulating substrate and electively stopping on the bottom terminal. In another example, an opening may be formed through any layers formed over the bottom terminal, again stopping on the bottom terminal. Those skilled in the pertinent art are familiar with methods of forming such openings. Once exposed, connection to the bottom terminal may be made in any conventional or novel manner.
In some embodiments the semiconductor substrate 310 is a p-type c-Si wafer, and is illustrated as such without limitation in
The doped semiconductor layer 315 may be formed from the semiconductor substrate 310 by doping a surface portion of the semiconductor substrate 310 with an opposite-type dopant. For example, in the illustrated example of a p-type semiconductor substrate 310, the dopant may be n-type. A doping process 320, e.g. a phosphorous implant, may be used. The doping process may result in some disordering of the crystalline lattice within the doped semiconductor layer 315. However, any such disordering is not expected to disrupt the overall long range ordering associated with crystallinity.
The doping process 320 has an associated doping thickness. The doping thickness is the thickness of a surface layer of the semiconductor substrate 310 that includes about 90% of the implanted dopant. In various embodiments the doping process 320 is configured such that the doping thickness is about equal to the thickness of a melted surface layer formed in a subsequent process step, as described below. In various embodiments, the doping thickness is in a range from about 10 nm to about 500 nm, with a thickness of about 100 nm being preferred. A conventional implant process may be easily configured to achieve the desired thickness.
The semiconductor substrate 310 acts as a heat sink into which heat from the melted portion of the doped semiconductor layer 315 may diffuse. Because the semiconductor substrate 310 has a thickness that is typically much greater than the thickness of the doped semiconductor layer 315, e.g. by about 1000 times or more, and the thermal conductivity of the semiconductor substrate 310 is typically good, the heat from the melted portion is expected to rapidly diffuse into the semiconductor substrate 310. The melted portion rapidly cools, thereby quenching the melt, e.g. cooling the melt rapidly such that little or no crystalline material results, to form a doped quenched amorphous layer 335.
Because the quenched amorphous layer 335 is formed from material originally sourced by the semiconductor substrate 310, impurities within the amorphous doped layer 335 should be no greater than the impurities within the semiconductor substrate 310 as long as other sources of impurities are excluded. In particular, when the semiconductor substrate 310 is a conventional semiconductor wafer, the quenched amorphous layer 335 is expected to have a very low concentration of hydrogen, e.g. no greater than about 1 at. %, and in some cases no greater than about 0.1 at. %. This contrasts markedly with conventional methods of forming an amorphous semiconductor layer, e.g. a silane-based CVD process described earlier. The lower concentration of hydrogen in the quenched amorphous layer 335 is expected to significantly increase the operational stability of the PV cell 300 relative to a similar conventionally formed cell, thereby increasing its expected operational lifetime and reducing the cost of ownership of the PV cell 300.
In various embodiments the semiconductor substrate 310 is chilled via a chilling process 325 to increase the rate of heat flow from the melted portion of the doped semiconductor layer 315 to the semiconductor substrate 310. It is expected that the chilling will increasingly favor the production of amorphous silicon, rather than e.g. microcrystalline silicon, in the quenched amorphous layer 335.
Herein “chilled” means heat is removed from the semiconductor substrate 310 via an active means such as a refrigeration cycle or thermoelectric cooler. Chilling the semiconductor substrate 310 does not necessarily mean that the temperature of the semiconductor substrate 310 will not rise during the illumination process 330 above an initial temperature of the semiconductor substrate 310 before illumination. However, if the temperature does rise, the rise should be less than it otherwise would be in the absence of chilling.
The illumination source may be, e.g. a narrow-spectrum source such as a laser or a broad-spectrum source such as a Xe flash lamp. The illumination may include visible and/or invisible wavelengths. The illumination source provides energy to heat the surface of the semiconductor substrate 310 to about the melting point of the semiconductor, e.g. about 1410° C. for Si. The heating preferably takes place over a short period, e.g. one second or less, to minimize heating of the semiconductor substrate 310. In some embodiments, the heating time is preferably about 100 ms or less, while in other embodiments the heating time is preferably about 10 ms or less.
In one embodiment, illumination is provided by a CO2 or excimer laser. The laser beam may be optically focused to a power density ranging from about 1 E 5 W/cm2 to about 1 E 7 W/cm2. Such a beam may be provided, e.g., by a Micropoint Laser system, manufactured by Photonic Industries, St. Charles, Ill. For example a suitably configured laser source is described in the '976 Application.
In summary, a laser with a beam power of, e.g. 1 E-3 W is focused to produce a power density ranging from about 8 E-3 W/μm2 to about 1.4 E-2 W/μm2 at the semiconductor surface. The exposure time may be adjusted, e.g. between about 1 μs and about ms, to result in the formation of a quenched amorphous semiconductor layer at the exposure site. In another example, a dynamic surface annealing (DSA) system, such as the Applied Vantage Astra system available from Applied Materials, Santa Clara, Calif., USA may also provide short-duration narrow-band illumination. In another embodiment the illumination source includes a broad-spectrum source such as a Xe lamp with focusing optics and/or an optical fiber used to produce a desired spot size.
A focused high-intensity light spot may be rastered across a semiconductor surface to convert an exposed portion of the surface to the amorphous allotrope of the semiconductor. The illumination spots may be narrow-band or broad-band. The conversion throughput may be increased by simultaneously rastering multiple spots over the semiconductor surface. For example,
In another embodiment a broad-spectrum source applies a blanket illumination over the surface of the semiconductor. For example, a flash lamp anneal (FLA) system, such as the Millios system manufactured by Mattson Technology, Inc., Fremont, Calif., USA may be used to provide a short-duration, e.g. 10 ms, broad-spectrum illumination sufficient to melt the semiconductor surface.
In contrast to conventional use of DSA or FLA, the semiconductor substrate 310 may be unheated or chilled so that the surface melt is quenched rather than annealed. Such operation is in marked contrast to a conventional DSA or FLA process, in which recrystallization of the semiconductor surface is typically desired.
The conditions that result in the formation of a quenched amorphous layer of a desired depth generally need to be determined for a given set of conditions. Such conditions may include, e.g. material type, the intensity vs. wavelength distribution of the light used, substrate temperature and the desired conversion depth. Process conditions that result in the desired conversion depth may be determined with the aid of design-of-experiment (DOE) techniques known to those skilled in the pertinent art. See, e.g. George E. P. Box, et al., “Statistics for Experimenters,” John Wiley and Sons (1978).
In some embodiments (not shown) an oxide layer may be deposited or thermally grown on the doped semiconductor layer 315 before it is illuminated. Such an oxide layer may protect the doped semiconductor layer 315 from thermal damage and/or reaction to ambient gases such as oxygen or nitrogen. The oxide layer may be selectively removed at a later process step when its protection is no longer needed.
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In the preceding method, the layers 530, 545, 550, 565580 are derived from CVD polysilicon layers. As such, these layers may include a similar hydrogen concentration as a conventionally formed polysilicon layer. However, manufacturing the HIT PV cell 500 is expected to benefit from the relative ease of producing the amorphous layers 530, 545, 565, 580. Furthermore, the performance of the HIT PV cell 500 may benefit from highly uniform thin quenched amorphous semiconductor layers and a high quality interface between adjacent pairs of layers expected to result from the disclosed methods.
Those skilled in the art to which this application relates will appreciate that other and further additions, deletions, substitutions and modifications may be made to the described embodiments.
