Patent Application
20250118592
An Application Data Sheet is filed concurrently with this specification as part of the present application. Each application that the present application claims benefit of or priority to as identified in the concurrently filed Application Data Sheet is incorporated by reference herein in its entirety and for all purposes.
Semiconductor processing tools typically include one or more pedestals that are used to support semiconductor wafers within a semiconductor processing chamber. Such pedestals feature wafer support surfaces that are designed to have wafers placed thereupon and to support those wafers during semiconductor processing operations within the semiconductor processing chamber. Pedestals may be equipped with any of a variety of ancillary systems, including, for example, vacuum chucks and/or electrostatic chucks (which may provide the wafer support surface of the pedestal), heating and/or cooling systems, electrodes used for radio-frequency energy transmission purposes, purge gas systems for protecting the undersides of wafers from process gases that are intended to only be applied to the upward-facing sides of the wafers, lift-pin mechanisms that may be used to raise wafers off of the wafer support surface (or lower wafers onto the wafer support surface), etc. In such tools, the top surface of the wafer is subjected to wafer processing operations while the bottom surface of the wafer rests on the pedestal. The wafer is typically clamped into place on the pedestal using a vacuum or electrostatic forces in order to maximize thermal coupling between the wafer and the pedestal, maintain wafer flatness during processing, and/or reduce the possibility of processing gases reaching the underside of the wafer. In some such semiconductor processing tools, a showerhead (sometimes referred to as a gas distributor) may be positioned above the pedestal. The showerhead may have a plurality of gas distribution ports distributed across a surface thereof that faces towards the pedestal. Such gas distribution ports are fluidically connected with one or more plenums located within the showerhead. The one or more plenums are, in turn, fluidically connected with one or more processing gas sources that may be controlled so as to selectively flow processing gases across the top surface of a wafer supported by the pedestal.
A relatively new type of semiconductor processing tool, described in U.S. Pat. Nos. 9,881,788 and 10,851,457 operates in a fundamentally different manner from the above-described semiconductor processing tools. In such newer semiconductor processing tools, the pedestal on which the wafer normally rests during semiconductor processing operations is replaced with a shower-pedestal, which is a pedestal-like structure that has a large number of gas distribution ports distributed across its upper surface (much like a showerhead has a number of gas distribution ports distributed across its underside). The gas distribution ports are fluidically connected with one or more plenums located within the shower-pedestal. The one or more plenums are, in turn, fluidically connected with one or more processing gas sources that are controllable so as to allow processing gases to be flowed out of the shower-pedestal via those gas distribution ports. Such semiconductor processing tools may also have one or more carrier ring supports that may be configured to support a carrier ring that may, in turn, support a wafer during processing operations. The one or more carrier ring supports are designed to allow the carrier ring and any wafer supported thereby to be held at an elevated location above the shower-pedestal, such that there is a gap in between the shower-pedestal and the wafer to which processing gas is able to be delivered. Such semiconductor processing tools thus allow the underside of the wafer to be subjected to wafer processing operations instead of the top side of the wafer, a complete reversal from the conventional wafer processing approach.
Details of one or more implementations of the subject matter described in this specification are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages will become apparent from the description, the drawings, and the claims.
In some implementations, an apparatus may be provided that includes a shower-pedestal having a plurality of first gas distribution ports distributed across a first surface thereof. The first surface of the shower-pedestal may define a first average midplane. The apparatus may further include a plurality of wafer support structures extending from the shower-pedestal and positioned about a first reference axis that intersects the first surface of the shower-pedestal and is perpendicular to the first average midplane. The plurality of wafer support structures may be further positioned around a region that includes the first surface of the shower-pedestal, each wafer support structure may have a corresponding wafer support surface that is non-parallel with respect to the first average midplane, and each wafer support surface may have a portion that is positioned at least a first distance away from the first average midplane in a direction perpendicular thereto and a second distance from the first reference axis in a direction perpendicular thereto.
In some further implementations, at least a portion of each wafer support surface may form an angle of greater than zero degrees and equal to or less than 15 degrees with respect to the first average midplane.
In some further implementations, each wafer support structure may include a corresponding cantilever beam structure and a corresponding riser structure. For each wafer support structure, the corresponding cantilever beam structure for that wafer support structure may extend radially inward towards the first reference axis from the corresponding riser structure for that wafer support structure, the corresponding cantilever beam structure for that wafer support structure may have a proximal end that is connected with the corresponding riser structure for that wafer support structure, and the corresponding cantilever beam structure for that wafer support structure may have a distal end at which the corresponding wafer support surface for that wafer support structure is located.
In some further implementations, each cantilever beam structure may have a corresponding channel in a side of that cantilever beam structure facing away from the first average midplane, the corresponding channel of each cantilever beam structure may be located between the wafer support surface of that cantilever beam structure and the corresponding riser structure connected with the proximal end of that cantilever beam structure, and the corresponding channel of each cantilever beam structure may extend across that cantilever beam structure in a direction that is transverse to a long axis of the cantilever beam structure.
In some further implementations, each channel may be at least 0.75 mm deep.
In some further implementations, the apparatus may further include a plurality of wafer-centering features, each wafer-centering feature having a corresponding centering surface. At least a portion of the centering surface of each wafer-centering feature may be positioned a third distance from, and face towards, the first reference axis.
In some further implementations, the third distance may be between 150.5 mm and 150 mm.
In some further implementations, each wafer-centering feature may be fixed in space with respect to, and supported by, a corresponding one of the wafer support structures.
In some further implementations, at least a portion of the centering surface of each wafer-centering feature may form an angle of less than 90 degrees with respect to the first reference axis.
In some further implementations, at least a portion of the centering surface of each wafer-centering feature may form an acute angle with respect to the first reference axis that is greater than 0 degrees and less than or equal to 30 degrees.
In some further implementations, the wafer-centering features may be wheels. In some further implementations, the wheels may be made of a ceramic material. In some further implementations, each wheel may be supported by a corresponding one of the wafer support structures relative to the shower-pedestal and may be configured to rotate about an axis that is at a fixed distance relative to the first average midplane.
In some further implementations, the apparatus further includes a showerhead with a plurality of second gas distribution ports distributed across a second surface of the showerhead that faces towards the first surface of the shower-pedestal. In such an implementations, there may be N wheels, the second surface of the showerhead may have N recesses in it, and each recess may be positioned such that a corresponding second reference axis that is perpendicular to the first average midplane and that passes through a center of a corresponding one of the wheels passes through that recess.
In some further implementations, the apparatus may further include a focus ring. The focus ring may have a nominally circular inner edge with a diameter that is smaller than twice the third distance and a nominally circular outer edge that has a diameter that is larger than twice the third distance. The focus ring may also be configured to rest on the wafer support structures and may include N openings proximate the inner edge or N notches along the inner edge that are each positioned such that a portion of a corresponding one of the wheels passes through the opening or notch when the focus ring is supported by the wafer support structures.
In some implementations, the focus ring may have a top surface and a bottom surface and may be associated with a center axis and a reference plane that is perpendicular to the center axis and coincident with the top surface. In such implementations, the bottom surface may have a first circumferential profile at a radial distance X from the center axis that varies such that a normal distance from the reference plane to the bottom surface at the radial distance X periodically varies between at least a first value and a second value. In such implementations, a value twice that of X may be larger than the diameter of the nominally circular inner edge and smaller than the diameter of the nominally circular outer edge.
In some implementations, the focus ring may further include a plurality of protrusions positioned along the bottom surface, each protrusion having a portion lying at the radial distance X from the center axis.
In some implementations, each protrusion may extend along a corresponding axis that is coplanar with a corresponding reference plane that is coplanar with the center axis.
In some implementations, each protrusion may be semi-cylindrical in shape.
In some implementations, the focus ring may have an inner portion and an outer portion, the inner edge may be located on the inner portion, the inner portion may be sized such that it cannot pass through an opening defined by an innermost edge of the outer portion, and the inner portion and the outer portion may not be fixedly connected with one another.
In some further implementations, the apparatus may include one or more wheel vertical lift mechanisms. Each wheel may be supported by a corresponding wheel riser structure, the one or more vertical lift mechanisms, in aggregate, may support the wheel riser structures and may be configured to be movable between at least a first configuration and a second configuration, at least a portion of each wheel may be farther from the first average midplane in a direction parallel to the first reference axis than the wafer support surfaces when the one or more vertical lift mechanisms are in the first configuration, and each wheel may, when the one or more vertical lift mechanisms are in the second configuration, be in between the first average midplane and the location that that wheel was in when the one or more vertical lift mechanisms were in the first configuration.
In some further implementations, the one or more vertical lift mechanisms may be further configured to be movable between at least the first and second configurations and also a third configuration, and the first average midplane may be in between the wafer support surfaces and at least a portion of each wheel when the one or more vertical lift mechanisms are in the third configuration.
In some further implementations, each wheel riser structure may pass through a corresponding notch in an outer edge of the shower-pedestal or through a corresponding hole through the shower-pedestal.
In some further implementations, each wheel riser structure may be located at a different angular position about the first reference axis than the wafer support structures.
In some further implementations, each wheel riser structure may be located at the same angular position about the first reference axis as a corresponding one of the wafer support structures.
In some further implementations, each wafer support structure may have an opening therethrough that is sized such that a portion of a corresponding one of the wheel riser structures passes through the opening when the one or more vertical lift mechanisms is moved between the first configuration to the second configuration.
In some further implementations, the apparatus may further include a chamber and a rotational indexer having a plurality of forks. The rotational indexer may be configured to rotate the plurality of forks about a first rotational axis to at least a first rotational position responsive to one or more inputs, each fork may have a plurality of wafer lift surfaces, and a first fork of the plurality of forks may be positioned such that the wafer lift surfaces thereof are positioned over the shower-pedestal when the plurality of forks are in the first rotational position.
In some further implementations, the first fork may include two arms that, when the plurality of forks are in the first rotational position, lie entirely outside of a circular region centered on the first reference axis and having a diameter of twice the third distance, and each of the arms may have one or more protrusions that, when the plurality of forks are in the first rotational position, extend inward towards the first reference axis such that a portion of each protrusion having one of the wafer lift surfaces lies within the circular region.
In some further implementations, each wafer lift surface may be non-parallel with respect to the first average midplane.
In some further implementations, at least a portion of each wafer lift surface may form an angle of greater than zero degrees and equal to or less than 25 degrees with respect to the first average midplane.
In some further implementations, the forks may each include a first half and a second half, at least one of the wafer lift surfaces of each fork may be provided by the first half of that fork, at least one other of the wafer lift surfaces of each fork may be provided by the second half of that fork, the first halves of the forks may be fixed in space with respect to a first hub, the second halves of the forks may be fixed in space with respect to a second hub, the first hub may be connected with a first rotational drive by a first shaft, the second hub, may be connected with a second rotational drive by a second shaft, and the first rotational drive and the second rotational drive may be configured to be independently actuated for at least a portion of their rotational range of motion.
In some implementations, an apparatus for use with semiconductor wafers of diameter D may be provided. Such an apparatus may include a ring structure having an inner perimeter defining an opening sized smaller than the semiconductor wafers of diameter D and an outer perimeter sized larger than the semiconductor wafers of diameter D. The ring structure may have a top surface and a bottom surface and be associated with a center axis and a reference plane that is perpendicular to the center axis and coincident with the top surface. The bottom surface may have a first circumferential profile at a radial distance X from the center axis that varies such that a normal distance from the reference plane to the bottom surface at the radial distance X varies between at least a first value and a second value. X may be less than 50% of D.
In some implementations, the normal distance from the reference plane to the bottom surface at the radial distance X may vary periodically.
In some such implementations, the normal distance from the reference plane to the bottom surface at the radial distance X may vary periodically with a periodicity of at least three periods about the circumference of the ring structure.
In some implementations, the normal distance from the reference plane to the bottom surface at the radial distance X may vary periodically with a periodicity of three periods about the circumference of the ring structure.
In some implementations, the normal distance from the reference plane to the bottom surface at the radial distance X may vary periodically with a periodicity of four periods about the circumference of the ring structure.
In some such implementations, the normal distance from the reference plane to the bottom surface at the radial distance X may vary periodically with a periodicity of at least four periods and less than or equal to ten periods about the circumference of the ring structure.
In some such implementations, the normal distance from the reference plane to the bottom surface at the radial distance X may vary periodically with a periodicity of more than ten periods and less than or equal to twenty periods about the circumference of the ring structure.
In some such implementations, the normal distance from the reference plane to the bottom surface at the radial distance X may vary periodically with a periodicity of more than twenty periods and less than or equal to thirty periods about the circumference of the ring structure.
In some implementations, there may be N spaced-apart first locations about the ring structure where the normal distance from the reference plane to the bottom surface at the radial distance X is at the first value, there may be N spaced-apart second locations about the ring structure where the normal distance from the reference plane to the bottom surface at the radial distance X is at the second value, each first location may be circumferentially interposed between two of the second locations, each second location may be circumferentially interposed between two of the first locations, and N may be an integer greater than or equal to three.
In some such implementations, N may be three or four. In some other implementations, N may be an integer greater than three and less than or equal to thirty, greater than three and less than or equal to ten, greater than ten and less than or equal to twenty, or greater than twenty and less than or equal to thirty.
In some implementations, the absolute value of the difference between the first value and the second value may be greater than zero microns and less than or equal to 400 microns.
In some implementations, the absolute value of the difference between the first value and the second value may be greater than zero microns and less than or equal to 100 microns, greater than or equal to 50 microns and less than or equal to 150 microns, greater than or equal to 100 microns and less than or equal to 200 microns, greater than or equal to 150 microns and less than or equal to 250 microns, greater than or equal to 200 microns and less than or equal to 300 microns, greater than or equal to 250 microns and less than or equal to 350 microns, or greater than or equal to 300 microns and less than or equal to 400 microns.
In some implementations, the absolute value of the difference between the first value and the second value may be greater by a third value than an expected maximum amount of wafer edge sag in the semiconductor wafers when the semiconductor wafers are supported at a plurality of locations along edges thereof. In some such implementations, the third value may be greater than zero microns and less than or equal to 50 microns. In some other such implementations, the third value may be greater than zero microns and less than or equal to 40 microns. In some other such implementations, the third value may be greater than zero microns and less than or equal to 30 microns. In some other such implementations, the third value may be greater than zero microns and less than or equal to 20 microns.
In some implementations, the top surface may be planar or at least axially symmetric about the center axis. In some other implementations, the top surface may have a second circumferential profile that follows the first circumferential profile.
In some implementations, the bottom surface at the radial distance X from the center axis may be a wavy conical frustum.
In some implementations, the bottom surface at the radial distance X from the center axis may have a radial profile with respect to the center axis that is at an oblique angle with respect to the center axis.
In some implementations, the ring structure may be made of a ceramic material. In some such implementations, the ceramic material may be aluminum oxide.
Reference to the following Figures is made in the discussion below; the Figures are not intended to be limiting in scope and are simply provided to facilitate the discussion below.
The above-described Figures are provided to facilitate understanding of the concepts discussed in this disclosure, and are intended to be illustrative of some implementations that fall within the scope of this disclosure, but are not intended to be limiting—implementations consistent with this disclosure and which are not depicted in the Figures are still considered to be within the scope of this disclosure.
Disclosed herein are systems and apparatuses for use in semiconductor processing tools that perform processing operations on the undersides of substrates (also referred to simply as “wafers” herein). As discussed above, U.S. Pat. Nos. 9,881,788 and 10,851,457 describe examples of semiconductor processing tools that are designed to facilitate the performance of wafer processing operations on the undersides of wafers. Such systems use a carrier ring to support such wafers during such operations; the carrier ring is supported above a shower-pedestal and, in turn, supports the wafer over the shower-pedestal such that there is a gap, e.g., at least several millimeters, between the underside of the wafer and the surface of the shower-pedestal immediately therebeneath. The carrier rings in such systems, however, contact the underside of the wafer, e.g., along an annular region extending radially inward from the wafer edge which rests on a corresponding annular region of the carrier ring, or at multiple smaller regions that rest on tabs that extend radially inward from the inner perimeter of the carrier ring. In either case, the surfaces that the wafer rests on make planar contact with the underside of the wafer. It was determined that such wafer support mechanisms resulted, in some cases, in an undesirable “shadowing” effect in which the surfaces of the wafer that were in contact with the carrier ring, or the regions of the wafer in the immediate vicinity did not experience the same amount of processing as did the remainder of the wafer. For example, such regions may experience a lower level of deposition than other regions of the wafer. Such non-uniformities may cause the usable area of the wafer to be reduced, thereby reducing wafer yield.
The present inventors conceived of apparatuses, systems, and methods that allow such wafer backside processing to be performed while supporting the wafer through edge contact, as opposed to through planar contact as is the case with the carrier ring-based system discussed above. By supporting the wafer through edge contact, the shadowing effect on the wafer may be reduced or eliminated, thereby reducing or eliminating the magnitude of non-uniformities that may arise on the underside of the wafer in the vicinity of locations where the wafer is supported. Moreover, such systems allow the wafer to be supported without the use of a carrier ring, which may decrease cost, tooling inventory, and complexity.
Wafers are typically provided with beveled or rounded top and bottom edges to reduce the likelihood of peeling, arcing, edge chipping, or other issues with the wafers during processing. However, the systems disclosed herein may be used with both beveled or rounded edge wafers or non-beveled or non-rounded edge wafers.
The various concepts relating to the use of edge-supported wafers during backside processing of such wafers are discussed below with respect to the various Figures.
The shower-pedestal 104 may generally include a sidewall that extends around the first plenum 110, a bottom wall (which may extend from the stem 105 to the sidewall, and a top wall (through which the first gas distribution ports 108 extend).
An average midplane of a surface is a plane that intersects with the surface and is positioned such that the maximum distances between the average midplane and the points on that surface that are furthest from the average midplane are at a minimum. For a first surface 106 that is planar, e.g., such as the one shown in
The first reference axis 116 may generally represent the center axis of the shower-pedestal or, perhaps more accurately, be positioned at a location that is intended to cause the first reference axis 116 to pass through the center of the wafer 101 when the wafer 101 is present and properly positioned.
The shower-pedestal 104 may support a plurality of wafer support structures 138 that may be positioned at locations around the first surface 106; in this example, there are three wafer support structures 138, although other implementations may have different numbers of wafer support structures 138. Wafer support structures, as used herein, refer to structures that are configured to have a wafer placed thereupon and to support such a wafer at an elevated location relative to the shower-pedestal, i.e., such that there is a gap between the underside of the wafer and the top of the shower-pedestal. Wafer support structures may be either fixed structures, e.g., static, tower-like structures that protrude from the top surface of the shower-pedestal, static, tower-like structures that extend downward from a showerhead positioned above the shower-pedestal, or static cantilevered structures that extend radially inward from the walls of a semiconductor processing chamber, or dynamic structures, e.g., similar structures that are connected with actuators that allow such structures to be moved between different positions, at least one of which correlates with a position in which a wafer may be supported thereby such that a gap exists between the underside of the wafer and the top side of the shower-pedestal. Various examples of wafer support structures are discussed in more detail later in this disclosure.
A plurality of wafer-centering features 160 may also be provided in association with the shower-pedestal 104. The wafer-centering features 160, like the wafer support structures 138, may be positioned at locations that are generally around the first surface 106, e.g., positioned about the first reference axis 116 and radially offset therefrom. In particular, the wafer-centering features 160 may each have one or more centering surfaces 162, at least portions of which are positioned a third distance 146 away from, and face towards, the first reference axis 116 in a direction perpendicular to the first reference axis 116. The third distance 146 may, for example, be in the range of 150.5 mm and 150 mm for systems that process 300 mm wafers. In some implementations, the wafer-centering surfaces may have portions thereof that form an angle of less than 45° with respect to the first reference axis 116. In some further such implementations, the wafer-centering surfaces may have portions thereof that form an acute angle with respect to the first reference axis 116 that is greater than 0° and less than or equal to 30°.
The wafer-centering features 160 in
The wheel riser structures 182 may be connected with one or more wheel riser support structures 180, e.g., such as an annular ring that extends around the stem 105. The wheel riser support structure(s) 180 may, in turn, be connected with one or more vertical lift mechanisms 178, e.g., one or more linear actuators, that may be controllably actuated so as to cause the one or more vertical lift mechanisms 178 to move between at least a first configuration and a second configuration. The one or more vertical lift mechanisms may, in aggregate, support the wheel riser structures 182 and thus the wheels 164. In the first configuration, at least a portion of each wheel is farther from the first average midplane 114 than the wafer support surfaces 140 (or at least from the portions thereof that are located at the first distance 142 from the first average midplane 114 and the second distance 144 from the first reference axis 116). As shown in
The wafer 101 is shown in
When the one or more vertical lift mechanisms 178 are in the second configuration, each wheel 164 may be in between the first average midplane 114 and where that wheel 164 was when the one or more vertical lift mechanisms were in the first configuration, i.e., closer to the first average midplane 114 than it was when the one or more vertical lift mechanisms were in the first configuration. The dotted outline of the wheel 164, wheel riser structure 182, and guide wheels 165 labeled “A” in
It will also be appreciated that the wafer 101 may first be placed on the wafer support structures 138 with the one or more vertical lift mechanisms 178 in the second configuration and the one or more vertical lift mechanisms 178 may then be caused to transition to the first configuration after the wafer 101 is resting on the wafer support structures 138. In such implementations, the wafer may be nudged radially inward, closer to being centered on the first reference axis 116, by the upward movement of the wheels 164 that arises from such motion.
In some implementations, such as the one depicted in
It will also be understood that fewer than three guide wheels 165 may be provided as well. For example, the two side guide wheels 165 (which rotate about axes perpendicular to the axis of rotation of the wheel 164) may, in some instances, be omitted with little impact on centering performance, leaving only a single guide wheel 165 (or two guide wheels) to guide the wheel riser structure 182 radially towards or away from the first reference axis 116.
It will be further understood that guide wheels 165 may additionally or alternatively be placed lower on the wheel riser structure 182 such that the guide wheels 165 engage with the interior surfaces of the notch or hole 184 in the shower pedestal instead of, or in addition to, the interior surfaces of the opening in the wafer support structure 138. It will also be appreciated that the guide wheels 165 may be placed within the shower-pedestal 104 and/or the wafer support structure 138 (and thus remain fixed in place—although rotatable—as the wheel riser structure 182 moves) and configured to contact the wheel riser structure 182 as it translates.
Furthermore, as discussed earlier, some implementations may not utilize any guide wheels 165, e.g., be unguided (or at least not guided by contact with the wafer support structure 138 and/or the shower-pedestal 104).
In some implementations, the vertical lift mechanism(s) may be further configured to transition between at least the first and second configurations and a third configuration. When the one or more vertical lift mechanisms are in the third configuration, the first average midplane 114 may be located in between the wafer support surfaces 140 and at least a portion of each wheel 164. In other words, the wheels 164 may be at least partially retracted below the level of the first average midplane 114. The dotted outline of the wheel 164, wheel riser structure 182, and guide wheels 165 labeled “B” in
It will be understood that in some implementations, the one or more vertical lift mechanisms 178 may only transition between first and second configurations, with the wheels 164 being located at least partially between the first average midplane 114 and, for example, a plane that is co-planar with the underside of the wafer 101 during wafer processing operations. In other implementations, the one or more vertical lift mechanisms 178 may further transition from the second configuration to the third configuration to completely retract the wheels 164 into the shower-pedestal 104, which may better protect the wheels 164 (e.g., from exposure to potential deposition or etch gases that may cause the diameter of the wheels 164 to change, thereby affecting wafer centering accuracy).
The ability to move the wheels 164 between different elevations with respect to the first average midplane 114 and the first surface 106 allows the wheels 164 to be used to help center the wafer 101 but then be moved out of the way to facilitate wafer processing operations. For example, once the wafer 101 is placed and centered on the wafer support structures 138, the shower-pedestal 104 may be caused to move upward so as to approach a showerhead (not shown) that is located above the shower-pedestal. In some instances, the showerhead may support a ring structure, e.g., a focus ring, that may be configured to rest on, and be supported by, the wafer support structures 138 when the shower-pedestal is brought sufficiently close to the showerhead. Such ring structures may be generally annular in shape and may have an interior edge that has a radius that is less than the diameter of the wafer so as to overlap the outer edge of the wafer. By making the wheel riser structures 182 movable/retractable, the wheels 164 may be caused to move to a lower position relative to the wafer support structures 138 prior to, or in tandem with, the movement of the shower-pedestal 104 so as to cause the ring structure to come into contact with the wafer support structures 138. This avoids potential interference/contact between the wheels 164 and/or wheel riser structures 182 and the ring structure and/or showerhead. It also avoids or reduces the potential for variations in radial flow conductance (in either or both of the space between the wafer and the showerhead or the wafer and the shower-pedestal) that may occur around the perimeter of the wafer due to the presence of the wheel riser structures 182 and/or the wheels 164.
Various types of wafer support structures 138 and wafer-centering features 160 may be used in various implementations.
As can be seen more clearly in
More clearly visible in
Also more clearly visible in
Another feature that is more clearly visible in
The implementation of
As shown in
In the above examples, the wafer-centering features have been provided by wheels that are able to be moved vertically through use of one or more vertical lift mechanisms. However, in some implementations, the wafer-centering features that are used may be supported by, and fixed in space relative to, the wafer support structures (at least with regard to vertical movement).
In
In some implementations, the wafer-centering features may be provided by non-wheel structures. For example, the wafer-centering features may instead be static structures, e.g., protrusions, that have sloped surfaces, e.g., structures having a sloped surface that provides the centering surface.
Many of the structures and features shown in
It will also be appreciated that the static wafer-centering features, e.g., as shown in
In implementations where the wafer-centering features are not able to be moved up and down relative to the wafer support structures, the wafer-centering features may protrude into space that may need to be occupied by other components during some phases of operation. Such other components may include, for example, a focus ring and/or a showerhead.
Many of the structures and features shown in
As can be seen in
The focus ring 870 may be designed to overlap the edge of the wafer (when present) to provide a mechanical barrier to potential diffusion of process gases from the underside of the wafer to the top side of the wafer. The focus ring 870 may have an inner edge 872 and an outer edge 874 that are nominally circular. In some implementations, the inner edge may have a diameter that is less than twice the third distance (between the centering surfaces and the first reference axis, e.g., less than the diameter of the wafer), and the outer diameter may have a diameter that is larger than twice the third distance.
As can be seen in
The focus ring 870 has an opening 876 that is proximate the inner edge 872 and sized large enough that the protruding portions of the wheel 864 and the portion of the wafer support structure 838 are able to pass therethrough without contacting the focus ring 870 when the focus ring 870 is supported by the wafer support structures 838. The openings 876 may also be notches that extend from the inner edge 872 outward (as suggested by the dotted lines visible between the opening 876 and the inner edge 872 in the enlarged detail view shown). The showerhead 828 similarly has a plurality of recesses 868 in it that correspond in number to the number of wafer-centering features 860 that are used, e.g., three. The recesses 868 are positioned such that the portions of the wafer-centering features 860 that may protrude through the focus ring 870 are able to extend into the recesses, thereby preventing the showerhead 828 from bottoming out on, and contacting, the wafer-centering features 860. The recesses 868 and/or the openings 876 may generally be positioned such that second reference axes (not shown) that are parallel to the first reference axis 816 and that pass through a center of, for example, the wheels 864 or other wafer-centering feature, e.g., a protrusion such as shown in
For further clarity, reference is made to
As can be seen in
Also visible in
The shower-pedestal 1004 that is depicted has a first plenum 1010 that may provide one or more processing gases to the underside of a wafer 1001 via a plurality of first gas distribution ports 1008. Such process gases may be provided to the shower-pedestal 1004 via a first gas inlet that is located in shower-pedestal stem 1005. The wafer 1001 may be supported on a plurality of wafer support structures 1038, e.g., wafer support structures that are similar to the wafer support structures 138 discussed earlier. Such wafer support structures 1038 may have openings 1086 that allow a wheel riser structure 1082 and wheel 1064 (shown retracted into a hole 1084 in the shower-pedestal 1004 here) to be extended therethrough so as to cause the wafer 1001 to be centered or more centered on a first reference axis (not shown here, but see earlier discussion thereof for other implementations).
The showerhead 1028 in
Also visible in
As noted earlier, shower-pedestals such as those discussed above may have other numbers of wafer support structures. For example, while
It will be understood that all of the implementations discussed herein and shown in the Figures that exhibit 3-fold radial symmetry (having three wafer support structures, for example) may also be provided in implementations having four-fold radial symmetry, e.g., such as exhibited by the shower-pedestal 1104.
The shower-pedestal and showerhead arrangements discussed above may be implemented in the context of a single-station or multi-station semiconductor processing chamber.
The chamber 1202 may have a plurality of wafer load slots 1203 that may, for example, provide an entryway for wafers to be introduced into, or removed from, the chamber 1202. The rotational indexer 1288 may be used to rotate wafers that have been introduced into the chamber 1202 between different shower-pedestals 1204. In implementations with only a single station, the chamber 1202 may be sized commensurately smaller, and only one shower-pedestal 1204 and showerhead 1228 may be located within the chamber 1202. The rotational indexer 1288 and the forks 1290 may also be omitted.
The arms 1296 may include one or more protrusions 1298 that extend inward towards the first reference axis 1216 and partially into the circular region 1299. The protrusions 1298 may be contiguous with the arms 1296 and may each have a wafer lift surface 1294 that is at a non-parallel angle with respect to the first average midplane. The wafer lift surfaces 1294 may, it will be seen, also extend at least partially into the circular region 1299. The wafer lift surfaces 1294 may, for example, be sloped at an angle with respect to the first average midplane that is greater than 0° and less than or equal to 25°. This allows the fork 1290 to contact the wafer 1201 only along an edge of the wafer 1201, thereby minimizing the amount of contact between the bottom surface of the wafer 1201 and the fork 1290 and reducing the amount of potential particulate generation that may occur.
The various components discussed above may be made from a variety of suitable materials, e.g., materials that are non-reactive or inert with respect to the various processing gases that may be used. For example, one or more of the wheels (if used), static wafer-centering features (if used), wafer support structures, wheel or static structure riser structures (if used), focus ring, shower-pedestal, showerhead, and forks (if used) may be made, in whole or in part, of a ceramic material such as aluminum oxide, silicon nitride, etc.
In
In
In
In
In
In
In
Once processing operations are complete for the wafers 1201 at a given station, the shower-pedestals 1204 may be retracted (and/or the showerheads 1228 raised) so as to return the semiconductor processing tool to a state similar that that shown in
An indexer lift mechanism (not shown) may then be caused to move the forks 1290 vertically upward, as shown in
In
In
As can be seen in
The chamber 2702 also includes a rotational indexer 2788; the rotational indexer 2788 may be supported by a rotational drive 2789 (e.g., an electric motor) that may, in turn, be supported by a vertically oriented linear drive system 2787. The linear drive system 2787 may be configured to translate the rotational drive 2789 up or down, and the rotational drive to rotate clockwise or counterclockwise, responsive to inputs received from a controller 2795. The controller 2795 may also be operatively connected with, e.g., connected directly or indirectly so as to be able to control, vertical lift mechanisms 2778, e.g., linear actuators, screw drives, pneumatic actuators, etc., and lift pin actuators 2720, e.g., linear actuators, screw drives, pneumatic actuators, etc. The vertical lift mechanisms 2778 may be configured to raise or lower, responsive to signals received from controller 2795, a wheel riser support structure 2780 (and wafer-centering features supported thereby), while the lift pin actuators 2720 may be configured to raise or lower lift pin support structure 2722 (and lift pins supported thereby) responsive to signals received from the controller 2795.
Also shown in
The controller 2795 may also be operatively connected with one or more first valves 2711 and one or more second valves 2733. The one or more first valves 2711 may be fluidically connected with one or more first gas sources 2709 and the first plenum of the shower-pedestal 2704. The controller 2795 may be configured to control the one or more first valves 2711, e.g., by providing related control signals thereto, in order to cause one or more first processing gases to be delivered from the one or more first gas sources 2709 to the shower-pedestal 2704.
Similarly, the one or more second valves 2733 may be fluidically connected with one or more second gas sources 2731 and the second plenum of the showerhead 2728. The controller 2795 may be configured to control the one or more second valves 2733, e.g., by providing related control signals thereto, in order to cause one or more second processing gases to be delivered from the one or more second gas sources 2731 to the showerhead 2728.
In some implementations, a rotational indexer may be used in such tools that has forks that may be transitioned between an open state and a closed state.
As can be seen in
The first halves 2890a, the first hub 2893a, and the first shaft 2897a may all be configured to rotate as a unit responsive to rotation of the first shaft 2897a. Similarly, the second halves 2890b, the second hub 2893b, and the second shaft 2897b may all be configured to rotate as a unit responsive to rotation of the second shaft 2897b. When the first shaft 2897a and the second shaft 2897b are both rotated in the same direction and at the same rate, the rotational indexer 2888 will rotate without any change in position between the first halves 2890a and the second halves 2890b. However, if the first shaft 2897a and the second shaft 2897b rotate in opposite directions or potentially in the same direction at different rates, the rotational position of the first hub 2893a relative to the second hub 2893b, and thus the rotational positions of the first halves 2890a relative to the second halves 2890b, may be caused to change. This allows the first halves 2890a and the second halves 2890b to be transitioned between an open state (shown in
The rotational indexer shown in
One issue that may arise in systems that may support a wafer such that the wafer is suspended above a shower-pedestal is that the wafer may, under its own weight, sag slightly.
As discussed earlier, a ring-like structure, such as the focus ring 870, may be centered on, and placed over, the wafer 3201. Such a ring-like structure may, for example, overlap the outer circumference of the wafer 3201 by a small amount. The ring-like structure may act as a diffusion barrier that prevents process gases introduced to the underside of the wafer 3201 from diffusing up past the edge of the wafer 3201 and into the region in between the wafer 3201 and a showerhead (not shown, but see earlier Figures and discussion) into which a purge gas may be flowed. The ring-like structure may either contact the wafer 3201 about its outer edge or be positioned such that a small, e.g., on the order of low tens of microns or less, gap exists between the wafer outer edge and the ring structure outer edge. Such contact or such a small gap may, in combination with the flow of purge gas, prevent diffusion of process gas from the underside of the wafer 3201, through the interface between the wafer 3201 and the ring structure, and to the top surface of the wafer 3201. In effect, the ring structure acts to “extend” the outer edge of the wafer to a larger diameter such that the process gas that does manage to diffuse past the “extended” outer edge contacts the outer edge of the ring structure as opposed to the outer edge of the wafer 3201.
However, when the wafer 3201 exhibits sag, such as shown in
In order to mitigate or eliminate this potential diffusion of process gas through the ring structure/wafer interface, the ring structure may have a design that eschews the traditional design of such ring structures in which the surface of the ring structure that contacts the wafer or is closest to the wafer is made to be axially symmetric, e.g., planar. Instead, such a surface may be made to have a varying circumferential profile that varies in a manner similar to the expected variation in a similar circumferential profile of the wafer (when supported through contact on the wafer edge similar to as shown in
A “circumferential profile” refers to a profile that is taken about the circumference of an object. For example, if one were to take the surface of a ring structure and intersect it with a cylindrical surface (not an actual object, but an abstract surface) that was centered on the center axis of the ring structure, the curve formed by the intersection of the ring structure surface and the cylindrical surface would be the “circumferential profile” of that ring structure surface. Put another way, a circumferential profile is similar to a cross-sectional profile, but evaluated about the circumference of a cylindrical surface instead of across a planar surface (as would be the case in a traditional cross-section view).
Also visible in
In many cases, such variation may be periodic, e.g., recurring in a generally cyclical manner at regular intervals, e.g., every 120°. However, such variations may also repeat but also be non-periodic, e.g., at 0°, 100°, and 240° angular locations about the center axis of the ring structure. In many cases, there will be three repetitions of each such variation, e.g., to match the areas in which a wafer supported at three points will sag. However, it will be understood that while the examples herein focus on variants having three repetitions of such variations to match a wafer that is supported at three points along its edge, other implementations may have a larger number of variations to match circumferential profiles of wafers supported at more than three points along their edges. For example, in some implementations, wafers may be supported at more than three points along their edges. In some such implementations, wafers may be supported at 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, or 30 points along their edges, and the circumferential profiles of ring structures designed to be used with wafers supported in such a manner may correspondingly have between 4 and 30, as appropriate, low points and high points, e.g., similar to the example above.
When the ring structure 3470 is placed on top of the wafer 3401, the two circumferential profiles may generally align and the distance between the ring structure and the wafer along the radius of the circumferential profile may be maintained within a desired threshold, e.g., within a distance small enough to block potential process gas diffusion through that interface.
In some implementations, the circumferential profile of the ring structure 3470 may be defined such that the absolute value of the difference between the first value and the second value is greater than 40 microns and less than or equal to 400 microns, thereby potentially being able to compensate for between approximately 40 microns and 400 microns of wafer edge sag. In some such implementations, the absolute value of the difference between the first value and the second value may be greater than or equal to 50 microns and less than or equal to 150 microns, greater than or equal to 100 microns and less than or equal to 200 microns, greater than or equal to 250 microns and less than or equal to 350 microns, or greater than or equal to 300 microns and less than or equal to 400 microns.
In some instances, the circumferential profile of the ring structure 3470 may be designed such that the absolute value of the difference between the first value and the second value is actually greater, by some small amount (e.g., on the order of low tens of microns) than the maximum expected amount of wafer edge sag in the wafers that the ring structure 3470 is to be used with. For example, the absolute value of the difference between the first value and the second value for the ring structure 3470 may be caused to be larger by a third value than the expected maximum amount of wafer edge sag in the wafers that the ring structure is designed to be used with. The third value may, in some cases, be greater than zero microns and less than or equal to 50 microns, e.g., between zero and 40 microns, between zero and 30 microns, between zero and 20 microns, etc.
In such implementations, the third value may be selected so as to ensure that there is always contact between the wafer 3401 and the bottom surface of the ring structure 3470 even if there is some variation in the maximum amount of edge sag that the wafer 3401 exhibits. For example, the amount of edge sag that wafers exhibit may vary slightly from wafer to wafer depending on, for example, temperature, wafer crystal orientation, potential localized effects due to features patterned onto the wafer, thickness variation in the wafer, etc. The maximum amount of wafer sag may, for example, be an average expected maximum amount of wafer sag, and there may be potential additional wafer sag beyond that in some cases. If the absolute value of the difference between the first value and the second value for the ring structure 3470 is selected to be larger than the expected amount of wafer edge sag by the third value, then this will have the effect of causing the ring structure 3470 to come to rest on the lowest parts of the wafer edge, i.e., the portions of the wafer edge that have sagged the most. At this point, the points of the ring structure that are located over the wafer support structures 3438 may not be in contact with the wafer 3401. However, the weight of the ring structure 3470 may push down on the edge of the wafer 3401, thereby causing the wafer 3401 to sag further until the ring structure is resting directly on top of the portions of the wafer 3401 that are supported by the wafer support structures 3438, thereby causing the wafer edge to come into contact with the ring structure around its full circumference. This is illustrated in
The ring structures discussed herein may be made from a variety of materials, although such materials may be selected to be resistant or non-reactive to the process chemicals that may be provided to the underside of the wafers being processed. For example, such ring structures may be made of a ceramic material, such as alumina (aluminum oxide), and then machined or ground to achieve the desired circumferentially varying profile.
The top surface of such ring structures may, in some cases, be planar or axially symmetric, as shown in
In some implementations, the ring structure may have a plurality of protrusions on its bottom surface, e.g., a circular array of protrusions, that may be positioned so as to lie along a contoured or non-axially symmetric portion of the bottom surface.
In some additional or alternative implementations, ring structures such as the above-discussed ring structures, or the focus rings discussed earlier, may be provided as multi-piece assemblies. For example, a ring structure may have an inner portion and an outer portion that encircles the inner portion. The outer portion may be configured such that the inner portion may rest on, and be supported by, the outer portion but may also be lifted vertically upward off of the inner portion when subjected to a force from below. Such implementations may allow the weight of the ring structure to be split between the inner portion and the outer portion thereof. When the ring structure is then brought into contact with a wafer positioned underneath it, the wafer may lift the inner portion clear of the outer portion and support it. The wafer may thus bear the weight of the inner portion but does not need to bear the weight of the outer portion.
As shown in
In
In
In
Such arrangements allow the size of the focus ring 4870 to be increased beyond the size of the inner portion 4870a without increasing the weight that bears on the wafer 4801 when the focus ring 4870 is placed on the wafer 4801. This allows the focus ring 4870 weight that is placed on the wafer 4801 to be at least somewhat decoupled from the size of the focus ring 4870, as well as the size of the showerhead 4828 that may support the focus ring 4870.
It will be appreciated that the circumferentially varying ring structures discussed herein may be used in any semiconductor processing systems in which a wafer is supported at discrete locations along its edge with the center of the wafer generally unsupported, thereby resulting in wafer edge sag. Such structures are not limited to use with the specific systems shown herein.
The control of a wafer back-side processing system, as well as potentially other equipment discussed above (such as wafer handling robots, indexers, etc.) may be facilitated through the use of a controller that may be included as part of a semiconductor processing tool, including, for example, the above-described example semiconductor processing tools and/or chambers. The systems discussed above may be integrated with electronics for controlling their operation before, during, and after processing of a semiconductor wafer or substrate. The electronics may be referred to as the “controller,” which may control various components or subparts of the system or systems. The controller, depending on the processing requirements and/or the type of system, may be programmed to control any of the processes disclosed herein, including the delivery of processing gases, temperature settings (e.g., heating and/or cooling), valve operation, light source control for radiative heating, pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, positional and operational settings, wafer transfers into and out of a tool or chamber and other transfer tools and/or load locks connected to or interfaced with a specific system. More specifically, such a controller may be configured to control, among other systems, the various actuators and motors of a back-side wafer processing system.
Broadly speaking, the controller may be defined as electronics having various integrated circuits, logic, memory, and/or software that receive instructions, issue instructions, control operation, enable cleaning operations, enable endpoint measurements, and the like. The integrated circuits may include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as application specific integrated circuits (ASICs), and/or one or more microprocessors, or microcontrollers that execute program instructions (e.g., software). Program instructions may be instructions communicated to the controller in the form of various individual settings (or program files), defining operational parameters for carrying out a particular process on or for a semiconductor wafer or to a system. The operational parameters may, in some embodiments, be part of a recipe defined by process engineers to accomplish one or more processing steps during the fabrication of one or more layers, materials, metals, oxides, silicon, silicon oxide, surfaces, circuits, and/or dies of a wafer.
The controller, in some implementations, may be a part of or coupled to a computer that is integrated with, coupled to the system, otherwise networked to the system, or a combination thereof. For example, the controller may be in the “cloud” or all or a part of a fab host computer system, which can allow for remote access of the wafer processing. The computer may enable remote access to the system to monitor current progress of fabrication operations, examine a history of past fabrication operations, examine trends or performance metrics from a plurality of fabrication operations, to change parameters of current processing, to set processing steps to follow a current processing, or to start a new process. In some examples, a remote computer (e.g. a server) can provide process recipes to a system over a network, which may include a local network or the Internet. The remote computer may include a user interface that enables entry or programming of parameters and/or settings, which are then communicated to the system from the remote computer. In some examples, the controller receives instructions in the form of data, which specify parameters for each of the processing steps to be performed during one or more operations. It should be understood that the parameters may be specific to the type of process to be performed and the type of tool that the controller is configured to interface with or control. Thus, as described above, the controller may be distributed, such as by comprising one or more discrete controllers that are networked together and working towards a common purpose, such as the processes and controls described herein. An example of a distributed controller for such purposes would be one or more integrated circuits on a chamber in communication with one or more integrated circuits located remotely (such as at the platform level or as part of a remote computer) that combine to control a process on the chamber.
Without limitation, example systems may include a plasma etch chamber or module, a deposition chamber or module, a spin-rinse chamber or module, a metal plating chamber or module, a clean chamber or module, a bevel edge etch chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, an atomic layer deposition (ALD) chamber or module, an atomic layer etch (ALE) chamber or module, an ion implantation chamber or module, a track chamber or module, and any other semiconductor processing systems that may be associated or used in the fabrication and/or manufacturing of semiconductor wafers.
As noted above, depending on the process step or steps to be performed by the tool, the controller might communicate with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout a factory, a main computer, another controller, or tools used in material transport that bring containers of wafers to and from tool locations and/or load ports in a semiconductor manufacturing factory.
As discussed above, the apparatuses and systems discussed herein may be used to perform processing on at least the underside of a wafer. Such processing may be particularly useful in the context of wafers having large numbers of feature layers, e.g., 3D memory structures or logic devices. Such wafers may, due to the number of feature layers present, warp or bow due to the compressive or tensile forces that may develop within each such feature layer. Systems that are able to perform processing operations on the underside of such wafers, i.e., on a side of the wafer opposite the side on which such feature layers exist, may able to apply material films to such wafers that may generate countervailing tensile or compressive forces that may cancel out or mitigate the stress imbalance through the thickness of the wafer, thereby causing the wafer to bow or warp less.
Traditional dual-electrode radio-frequency plasma-enhanced chemical vapor deposition (PECVD) or etch systems have one gas-flowing electrode that is used for radio-frequency power supply or for ground in the generation of a plasma. Typically, the gas-flowing electrode (also referred to as a showerhead) is on the top side of the reactor, causing the reactants to flow onto the top side of the wafer, thereby causing processing to occur only on the top side of the wafer.
In the systems discussed herein, dual gas-flowing electrodes are provided—one by way of the showerhead and the other by way of the shower-pedestal. Either of the electrodes may serve as an RF electrode to provide AC power for enabling a plasma for use in film deposition or etch processes. This dual gas-flowing electrode system is capable of selectively depositing or etching films on both sides or only one side of the wafer.
In one implementation, the back-side gas flow provided by the shower-pedestal enables the wafer processing operations to be performed on the back-side of the wafer while the front-side gas flow from the showerhead can deposit on the front side of the wafer. In other implementations (on separate tools, or even the same tool or even the same station within the same tool), the system can be set up to selectively process only one side of the wafer by turning on and off the reactants that cause the processing to occur on a particular side of the wafer and replacing them with non-reacting gases (e.g., inert gases).
The shower-pedestals and/or showerheads discussed herein may, in some implementations, include an active heater to get the process gases flowed therethrough to a desired temperature prior to delivery into the chamber housing the shower-pedestals and/or showerheads.
Broadly speaking, when used for deposition-based processing, the use of shower-pedestal may provide several advantages for combating stress and bowing issues by depositing a film on the back side of the wafer. The back-side film may counteract the stress that arises from the front-side deposition, thereby causing a neutral stress condition (or substantially neutral stress, e.g., less than about +/−150 MPa) to develop, thereby resulting in a wafer that shows no bowing (or substantially no bowing, e.g., less than about 150 μm of bow). If the film deposited on the front side is a tensile film, then the back-side film should also be tensile to balance out the overall stress. Likewise, if the front-side film is compressive, then the back-side film should also be compressive. The back-side film may be deposited through various reaction mechanisms (e.g., chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), plasma enhanced atomic layer deposition (PEALD), low pressure chemical vapor deposition (LPCVD), etc)—thus, the equipment discussed herein may be generally usable or adaptable for performing any such types of processing. In some implementations, plasma-enhanced chemical vapor deposition may be used due to the high deposition rate achieved in this type of reaction.
For deposition operations, certain deposition parameters may be tuned to produce a back-side film having a desired stress level. One of these deposition parameters is the thickness of the deposited back-side film. Thicker films may induce more stress in the wafer, while thinner films (of the same composition and deposited under the same conditions) may induce less stress in the wafer. Therefore, in order to minimize the amount of material consumed in forming the back-side layer, the layer may be deposited relatively thinly under conditions that promote formation of a highly stressed film.
As mentioned, stacks of deposited materials on the front-side of the wafer, e.g., to make memory or logic circuits are more likely to result in wafer stress and bowing. One example stack that may cause these problems is a stack having alternating layers of oxide and nitride (e.g., silicon oxide/silicon nitride/silicon oxide/silicon nitride, etc.). Another example stack likely to result in bowing includes alternating layers of oxide and polysilicon (e.g., silicon oxide/polysilicon/silicon oxide/polysilicon, etc.). Other examples of stack materials that may be problematic include, but are not limited to, tungsten and titanium nitride. The materials in the stacks may be deposited through chemical vapor deposition techniques such as plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), plasma-enhanced atomic layer deposition (PEALD), or direct metal deposition (DMD), etc. These examples are not intended to be limiting. Certain disclosed implementations may be useful whenever wafer stress and/or bowing are induced due to material being present on the front side of the wafer.
The front-side stacks may be deposited to any number of layers and thicknesses. In a typical example, such a stack may include between about 32 to 72 layers and may have a total thickness between about 2 μm to 4 μm. The stress induced in the wafer by the stack may be between about−500 MPa to about +500 MPa, resulting in a bow that is frequently between about 200 μm to 400 μm (for a 300 mm wafer), and even greater in some cases.
The material deposited on the back-side of the wafer may be a dielectric material in various implementations. In some cases, an oxide and/or nitride (e.g., silicon oxide/silicon nitride) may be used. Examples of silicon-containing reactants that may be used to produce such a layer include, but are not limited to, silanes, halosilanes, and aminosilanes. A silane contains hydrogen and/or carbon groups but does not contain a halogen. Examples of silanes are silane (SiH4), disilane (Si2H6), and organo-silanes such as methylsilane, ethylsilane, isopropylsilane, t-butylsilane, dimethylsilane, diethylsilane, di-t-butylsilane, allylsilane, sec-butylsilane, thexylsilane, isoamylsilane, t-butyldisilane, di-t-butyldisilane, and the like. A halosilane contains at least one halogen group and may or may not contain hydrogens and/or carbon groups. Examples of halosilanes are iodosilanes, bromosilanes, chlorosilanes and fluorosilanes. Although halosilanes, particularly fluorosilanes, may form reactive halide species that can etch silicon materials, in certain implementations described herein, the silicon-containing reactant is not present when a plasma is struck. Specific chlorosilanes are tetrachlorosilane (SiCl4), trichlorosilane (HSiCl3), dichlorosilane (H2SiCl2), monochlorosilane (ClSiH3), chloroallylsilane, chloromethylsilane, dichloromethylsilane, chlorodimethylsilane, chloroethylsilane, t-butylchlorosilane, di-t-butylchlorosilane, chloroisopropylsilane, chloro-sec-butylsilane, t-butyldimethylchlorosilane, thexyldimethylchlorosilane, and the like. An aminosilane includes at least one nitrogen atom bonded to a silicon atom, but may also contain hydrogens, oxygens, halogens and carbons. Examples of aminosilanes are mono-, di-, tri- and tetra-aminosilane (H3Si(NH2)4, H2Si(NH2)2, HSi(NH2)3 and Si(NH2)4, respectively), as well as substituted mono-, di-, tri- and tetra-aminosilanes, for example, t-butylaminosilane, methylaminosilane, tert-butylsilanamine, bis(tertiarybutylamino) silane (SiH2(NHC(CH3)3)2 (BTBAS), tert-butyl silylcarbamate, SiH(CH3)—(N(CH3)2)2, SiHCl—(N(CH3)2)2, (Si(CH3)2NH)3 and the like. A further example of an aminosilane is trisilylamine (N(SiH3)). Other potential silicon-containing reactants include tetraethyl orthosilicate (TEOS), and cyclic and non-cyclic TEOS variants such as tetramethoxysilane (TMOS), fluorotriethoxysilane (FTES), Trimethylsilane (TMS), octamethyltetracyclosiloxane (OMCTS), tetramethylcyclotetrasiloxane (TMCTSO), dimethyldimethoxysilane (DMDS), hexamethyldisilazane (HMDS), hexamethyldisiloxane (HMDSO), hexamethylcyclotrisiloxane (HMCTSO), dimethyldiethoxysilane (DMDEOS), methyltrimethoxysilane (MTMOS), tetramethyldisiloxane (TMDSO), divinyltetramethyldisiloxane (VSI2), methyltriethoxysilane (MTEOS), dimethyltetramethoxydisiloxane (DMTMODSO), ethyltriethoxysilane (ETEOS), ethyltrimethoxysilane (ETMOS), hexamethoxydisilane (HMODS), bis(triehtoxysilyl) ethane (BTEOSE), bis(trimethoxysilyl) ethane (BTMOSE), dimethylethoxysilane (DMEOS), tetraethoxydimethyldisiloxane (TEODMDSO), tetrakis (trimehtylsiloxy) silane (TTMSOS), tetramethyldiethoxydisiloxane (TMDEODSO), triethoxysilane (TIEOS), trimethoxysilane (TIMEOS), or tetrapropoxysilane (TPOS).
Example nitrogen-containing reactants that may be used to create such a layer include, but are not limited to, ammonia, hydrazine, amines (e.g., amines bearing carbon) such as methylamine, dimethylamine, ethylamine, isopropylamine, t-butylamine, di-t-butylamine, cyclopropylamine, sec-butylamine, cyclobutylamine, isoamylamine, 2-methylbutan-2-amine, trimethylamine, diisopropylamine, diethylisopropylamine, di-t-butylhydrazine, as well as aromatic containing amines such as anilines, pyridines, and benzylamines. Amines may be primary, secondary, tertiary, or quaternary (for example, tetraalkylammonium compounds). A nitrogen-containing reactant can contain heteroatoms other than nitrogen, for example, hydroxylamine, t-butyloxycarbonyl amine and N-t-butyl hydroxylamine are nitrogen-containing reactants.
Examples of oxygen-containing co-reactants that may be used to create such layers may include oxygen, ozone, nitrous oxide, carbon monoxide, nitric oxide, nitrogen dioxide, sulfur oxide, sulfur dioxide, oxygen-containing hydrocarbons (CxHyOz), water, mixtures thereof, etc.
The flow rate of these reactants may depend greatly on the type of reaction through which the back-side layer is deposited. Where CVD/PECVD are used to deposit the back-side layer, the flow rate of the silicon-containing reactant may be between about 0.5 ml/min to 10 mL/min (before atomization), for example between about 0.5 mL/min to 5 mL/min. The flow rate of a nitrogen-containing reactant, oxygen-containing reactant, or other co-reactant may be between about 3 SLM to 25 SLM, for example between about 3 SLM to 10 SLM.
In certain implementations, the back-side layer may be removed after further processing. Where this is the case, the composition of the back-side layer may be chosen such that it can be easily removed from the substrate at an appropriate time. In this regard, there may be a high selectivity between the material of the back-side layer (e.g., the dielectric) and the material of the underlying substrate (e.g., silicon) in the desired removal chemistry.
The optimal thickness of the back-side layer may depend on the amount of stress induced by the deposition on the front side of the wafer, as well as the conditions under which the back-side layer is deposited. The back-side layer may be deposited to a thickness at which the stress in the wafer becomes negligible (e.g., less than about 150 MPa). In these or other implementations, the back-side layer may be deposited to a thickness at which the wafer bow becomes negligible (e.g., less than about 150 μm of bow). In some cases, this corresponds to a back-side layer thickness between about 0.1 μm to 2 μm, for example between about 0.3 μm to 2 μm, or between about 0.1 μm to 1 μm, or between about 0.3 μm to 1 μm. Where silicon nitride is used to form the back-side layer, a film having a thickness of about 0.3 μm may be sufficient to mitigate a bow of about 50 μm to 200 μm. As mentioned above, a higher-stress back-side layer may be used to reduce the required thickness of the back-side layer needed to overcome a thicker, but lower-stress front-side layer. This may help conserve materials and reduce costs, e.g., by requiring less processing time. For more information regarding backside deposition techniques, reference may be made to U.S. Pat. No. 9,881,788, which is owned by the same assignee as the present application and is hereby incorporated herein by reference in its entirety.
The use, if any, of ordinal indicators, e.g., (a), (b), (c) . . . or (1), (2), (3) . . . or the like, in this disclosure and claims is to be understood as not conveying any particular order or sequence, except to the extent that such an order or sequence is explicitly indicated. For example, if there are three steps labeled (i), (ii), and (iii), it is to be understood that these steps may be performed in any order (or even concurrently, if not otherwise contraindicated) unless indicated otherwise. For example, if step (ii) involves the handling of an element that is created in step (i), then step (ii) may be viewed as happening at some point after step (i). Similarly, if step (i) involves the handling of an element that is created in step (ii), the reverse is to be understood. It is also to be understood that use of the ordinal indicator “first” herein, e.g., “a first item,” should not be read as suggesting, implicitly or inherently, that there is necessarily a “second” instance, e.g., “a second item.”
It is to be understood that the phrases “for each <item> of the one or more <items>,” “each <item> of the one or more <items>,” or the like, if used herein, are inclusive of both a single-item group and multiple-item groups, i.e., the phrase “for . . . each” is used in the sense that it is used in programming languages to refer to each item of whatever population of items is referenced. For example, if the population of items referenced is a single item, then “each” would refer to only that single item (despite the fact that dictionary definitions of “each” frequently define the term to refer to “every one of two or more things”) and would not imply that there must be at least two of those items. Similarly, the term “set” or “subset” should not be viewed, in itself, as necessarily encompassing a plurality of items—it will be understood that a set or a subset can encompass only one member or multiple members (unless the context indicates otherwise).
For the purposes of this disclosure, the term “fluidically connected” is used with respect to volumes, plenums, holes, etc., that may be connected with one another, either directly or via one or more intervening components or volumes, in order to form a fluidic connection, similar to how the term “electrically connected” is used with respect to components that are connected together to form an electric connection. The term “fluidically interposed,” if used, may be used to refer to a component, volume, plenum, or hole that is fluidically connected with at least two other components, volumes, plenums, or holes such that fluid flowing from one of those other components, volumes, plenums, or holes to the other or another of those components, volumes, plenums, or holes would first flow through the “fluidically interposed” component before reaching that other or another of those components, volumes, plenums, or holes. For example, if a pump is fluidically interposed between a reservoir and an outlet, fluid that flowed from the reservoir to the outlet would first flow through the pump before reaching the outlet. The term “fluidically adjacent,” if used, refers to placement of a fluidic element relative to another fluidic element such that there are no potential structures fluidically interposed between the two elements that might potentially interrupt fluid flow between the two fluidic elements. For example, in a flow path having a first valve, a second valve, and a third valve placed sequentially therealong, the first valve would be fluidically adjacent to the second valve, the second valve fluidically adjacent to both the first and third valves, and the third valve fluidically adjacent to the second valve.
The term “between,” as used herein and when used with a range of values, is to be understood, unless otherwise indicated, as being inclusive of the start and end values of that range. For example, between 1 and 5 is to be understood to be inclusive of the numbers 1, 2, 3, 4, and 5, not just the numbers 2, 3, and 4.
The term “operatively connected” is to be understood to refer to a state in which two components and/or systems are connected, either directly or indirectly, such that, for example, at least one component or system can control the other. For example, a controller may be described as being operatively connected with a resistive heating unit, which is inclusive of the controller being connected with a sub-controller of the resistive heating unit that is electrically connected with a relay that is configured to controllably connect or disconnect the resistive heating unit with a power source that is capable of providing an amount of power that is able to power the resistive heating unit so as to generate a desired degree of heating. The controller itself likely cannot supply such power directly to the resistive heating unit due to the currents involved, but it will be understood that the controller is nonetheless operatively connected with the resistive heating unit.
It is understood that the examples and implementations described herein are for illustrative purposes only and that various modifications or changes in light thereof will be suggested to persons skilled in the art. Although various details have been omitted for clarity's sake, various design alternatives may be implemented. Therefore, the present examples are to be considered as illustrative and not restrictive, and the disclosure is not to be limited to the details given herein but may be modified within the scope of the disclosure.
It is to be understood that the above disclosure, while focusing on a particular example implementation or implementations, is not limited to only the discussed example, but may also apply to similar variants and mechanisms as well, and such similar variants and mechanisms are also considered to be within the scope of this disclosure. However, the present disclosure is at least directed at, and inclusive of, the following non-exclusive list of numbered implementations:
Implementation 1: An apparatus including:
Implementation 2: The apparatus of implementation 1, where at least a portion of each wafer support surface forms an angle of greater than zero degrees and equal to or less than 15 degrees with respect to the first average midplane.
Implementation 3: The apparatus of either of implementations 1 or 2, where each wafer support structure includes a corresponding cantilever beam structure and a corresponding riser structure, where, for each wafer support structure:
Implementation 4: The apparatus of implementation 3, where:
Implementation 5: The apparatus of implementation 4, where each channel is at least 0.75 mm deep.
Implementation 6: The apparatus of any one of implementations 1 through 5, further including a plurality of wafer-centering features, each wafer-centering feature having a corresponding centering surface, where at least a portion of the centering surface of each wafer-centering feature is positioned a third distance from, and faces towards, the first reference axis.
Implementation 7: The apparatus of implementation 6, where the third distance is between 150.5 mm and 150 mm.
Implementation 8: The apparatus of either implementation 6 or implementation 7, where each wafer-centering feature is fixed in space with respect to, and supported by, a corresponding one of the wafer support structures.
Implementation 9: The apparatus of implementation 8, where at least a portion of the centering surface of each wafer-centering feature forms an angle of less than 90 degrees with respect to the first reference axis.
Implementation 10: The apparatus of implementation 8, where at least a portion of the centering surface of each wafer-centering feature forms an acute angle with respect to the first reference axis that is greater than 0 degrees and less than or equal to 30 degrees.
Implementation 11: The apparatus of implementation 6, where the wafer-centering features are wheels.
Implementation 12: The apparatus of implementation 11, where the wheels are made of a ceramic material.
Implementation 13: The apparatus of either implementation 11 or implementation 12, where each wheel is supported by a corresponding one of the wafer support structures relative to the shower-pedestal and is configured to rotate about an axis that is at a fixed distance relative to the first average midplane.
Implementation 14: The apparatus of implementation 13, further including a showerhead having a plurality of second gas distribution ports distributed across a second surface of the showerhead that faces towards the first surface of the shower-pedestal, where:
Implementation 15: The apparatus of implementation 14, further including a focus ring, where the focus ring:
Implementation 16: The apparatus of implementation 15, where:
Implementation 17: The apparatus of implementation 16, where the focus ring further includes a plurality of protrusions positioned along the bottom surface, each protrusion having a portion lying at the radial distance X from the center axis.
Implementation 18: The apparatus of implementation 17, where each protrusion extends along a corresponding axis that is coplanar with a corresponding reference plane that is coplanar with the center axis.
Implementation 19: The apparatus of implementation 18, where each protrusion is semi-cylindrical in shape.
Implementation 20: The apparatus of implementation 15, where:
Implementation 21: The apparatus of either implementation 11 or implementation 12, further including one or more wheel vertical lift mechanisms, where:
Implementation 22: The apparatus of implementation 21, where:
Implementation 23: The apparatus of either implementation 21 or implementation 22, where each wheel riser structure passes through a corresponding notch in an outer edge of the shower-pedestal or through a corresponding hole through the shower-pedestal.
Implementation 24: The apparatus of any one of implementations 21 through 23, where each wheel riser structure is located at a different angular position about the first reference axis than the wafer support structures.
Implementation 25: The apparatus of any one of implementations 21 through 23, where each wheel riser structure is located at the same angular position about the first reference axis as a corresponding one of the wafer support structures.
Implementation 26: The apparatus of implementation 25, where each wafer support structure has an opening therethrough that is sized such that a portion of a corresponding one of the wheel riser structures passes through the opening when the one or more vertical lift mechanisms is moved between the first configuration to the second configuration.
Implementation 27: The apparatus of any one of implementations 1 through 26, further including:
Implementation 28: The apparatus of implementation 27, where:
Implementation 29: The apparatus of implementation 28, where each wafer lift surface is non-parallel with respect to the first average midplane.
Implementation 30: The apparatus of implementation 28, where at least a portion of each wafer lift surface forms an angle of greater than zero degrees and equal to or less than 25 degrees with respect to the first average midplane.
Implementation 31: The apparatus of any one of implementations 28 through 30, where:
Implementation 32: An apparatus for use with semiconductor wafers of diameter D, the apparatus including a ring structure having an inner perimeter defining an opening sized smaller than the semiconductor wafers of diameter D and an outer perimeter sized larger than the semiconductor wafers of diameter D, where:
Implementation 33: The apparatus of implementation 32, where the normal distance from the reference plane to the bottom surface at the radial distance X varies periodically.
Implementation 34: The apparatus of implementation 33, where the normal distance from the reference plane to the bottom surface at the radial distance X varies periodically with a periodicity of at least three periods about the circumference of the ring structure.
Implementation 35: The apparatus of implementation 33, where the normal distance from the reference plane to the bottom surface at the radial distance X varies periodically with a periodicity of three periods about the circumference of the ring structure.
Implementation 36: The apparatus of implementation 33, where the normal distance from the reference plane to the bottom surface at the radial distance X varies periodically with a periodicity of four periods about the circumference of the ring structure.
Implementation 37: The apparatus of implementation 33, where the normal distance from the reference plane to the bottom surface at the radial distance X varies periodically with a periodicity of at least four periods and less than or equal to ten periods about the circumference of the ring structure.
Implementation 38: The apparatus of implementation 33, where the normal distance from the reference plane to the bottom surface at the radial distance X varies periodically with a periodicity of more than ten periods and less than or equal to twenty periods about the circumference of the ring structure.
Implementation 39: The apparatus of implementation 33, where the normal distance from the reference plane to the bottom surface at the radial distance X varies periodically with a periodicity of more than twenty periods and less than or equal to thirty periods about the circumference of the ring structure.
Implementation 40: The apparatus of any one of implementations 32 through 39, where:
Implementation 41: The apparatus of implementation 40, where N is three.
Implementation 42: The apparatus of implementation 40, where N is four.
Implementation 43: The apparatus of implementation 40, where N is an integer greater than three and less than or equal to thirty.
Implementation 44: The apparatus of implementation 40, where N is an integer greater than three and less than or equal to ten.
Implementation 45: The apparatus of implementation 40, where N is an integer greater than ten and less than or equal to twenty.
Implementation 46: The apparatus of implementation 40, where N is an integer greater than twenty and less than or equal to thirty.
Implementation 47: The apparatus of any one of implementations 32 through 46, where the absolute value of the difference between the first value and the second value is greater than zero microns and less than or equal to 400 microns.
Implementation 48: The apparatus of any one of implementations 32 through 46, where the absolute value of the difference between the first value and the second value is greater than zero microns and less than or equal to 100 microns.
Implementation 49: The apparatus of any one of implementations 32 through 46, where the absolute value of the difference between the first value and the second value is greater than or equal to 50 microns and less than or equal to 150 microns.
Implementation 50: The apparatus of any one of implementations 32 through 46, where the absolute value of the difference between the first value and the second value is greater than or equal to 100 microns and less than or equal to 200 microns.
Implementation 51: The apparatus of any one of implementations 32 through 46, where the absolute value of the difference between the first value and the second value is greater than or equal to 150 microns and less than or equal to 250 microns.
Implementation 52: The apparatus of any one of implementations 32 through 46, where the absolute value of the difference between the first value and the second value is greater than or equal to 200 microns and less than or equal to 300 microns.
Implementation 53: The apparatus of any one of implementations 32 through 46, where the absolute value of the difference between the first value and the second value is greater than or equal to 250 microns and less than or equal to 350 microns.
Implementation 54: The apparatus of any one of implementations 32 through 46, where the absolute value of the difference between the first value and the second value is greater than or equal to 300 microns and less than or equal to 400 microns.
Implementation 55: The apparatus of any one of implementations 32 through 46, where the absolute value of the difference between the first value and the second value is greater by a third value than an expected maximum amount of wafer edge sag in the semiconductor wafers when the semiconductor wafers are supported at a plurality of locations along edges thereof.
Implementation 56: The apparatus of implementation 55, where the third value is greater than zero microns and less than or equal to 50 microns.
Implementation 57: The apparatus of implementation 55, where the third value is greater than zero microns and less than or equal to 40 microns.
Implementation 58: The apparatus of implementation 55, where the third value is greater than zero microns and less than or equal to 30 microns.
Implementation 59: The apparatus of implementation 55, where the third value is greater than zero microns and less than or equal to 20 microns.
Implementation 60: The apparatus of any one of implementations 32 through 59, where the top surface is planar.
Implementation 61: The apparatus of any one of implementations 32 through 59, where the top surface is axially symmetric about the center axis.
Implementation 62: The apparatus of any one of implementations 32 through 61, where the top surface has a second circumferential profile that follows the first circumferential profile.
Implementation 63: The apparatus of any one of implementations 32 through 62, where the bottom surface at the radial distance X from the center axis is a wavy conical frustum.
Implementation 64: The apparatus of any one of implementations 32 through 62, where the bottom surface at the radial distance X from the center axis has a radial profile with respect to the center axis that is at an oblique angle with respect to the center axis.
Implementation 65: The apparatus of any one of implementations 32 through 64, where the ring structure is made of a ceramic material.
Implementation 66: The apparatus of implementation 65, where the ceramic material is aluminum oxide.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/US2023/011056 | 1/18/2023 | WO |
| Number | Date | Country | |
|---|---|---|---|
| 63368974 | Jul 2022 | US | |
| 63301961 | Jan 2022 | US |
