Patent Application
20250015027
This disclosure relates to semiconductor packages and, more particularly, to bonding structures in integrated circuit (IC) die packages.
An IC die package can include two or more IC dies (e.g., system-on-chips (SOCs), logic dies, and/or memory dies) mounted on a package substrate. Power and signal connections between the IC dies can be made through a routing layer. The two or more IC dies can be bonded to the routing layer through hybrid bonding structures. The complexity of manufacturing reliable bonds between the hybrid bonding structures has increased with the scaling down of IC die packages to meet the increased demand for portable electronic devices.
Various embodiments of bonding structures in an IC die package are disclosed. In some embodiments, a structure includes an IC die, an interposer structure electrically connected to the IC die, a first bonding structure, and a second bonding structure. The first bonding structure includes a first dielectric layer disposed on the IC die and also includes a first conductive pad having an embedded portion disposed in the first dielectric layer and an anchor portion extending over a top surface of the first dielectric layer. The second bonding structure includes a second dielectric layer disposed on the interposer structure, a second conductive pad disposed in the second dielectric layer, and an anchor layer surrounding the anchor portion.
In some embodiments, an IC die package includes a routing layer, a die layer, and a bonding layer disposed between the routing layer and the die layer. The routing layer includes conductive lines and vias, and the die layer includes IC dies disposed on the routing layer. The bonding layer includes a bottom dielectric layer disposed on the routing layer, a top dielectric disposed on and bonded to the bottom dielectric layer, a bottom conductive structure disposed in the bottom dielectric layer, and a top conductive structure having a first portion disposed in the top dielectric layer and a second portion disposed in the bottom conductive structure.
In some embodiments, a method for fabricating an IC die package with hybrid bonding structures includes forming a first opening in a first dielectric layer on an integrated circuit (IC) die, depositing a first conductive layer with a first layer portion in the first opening and a second layer portion extending over a top surface of the first dielectric layer, forming a second opening in a second dielectric layer on an interposer structure, depositing a second conductive layer in the second opening, and depositing a third conductive layer on the second conductive layer, such that a top surface of the third conductive layer is below a top surface of the second dielectric layer. The method further includes placing the top surface of the first dielectric layer on the top surface of the second dielectric layer to position the second layer portion in the second opening and on the third conductive layer and performing a bonding process to bond the second layer portion and the third conductive layer.
Aspects of this disclosure are best understood from the following detailed description when read with the accompanying figures.
Illustrative embodiments will now be described with reference to the accompanying drawings. In the drawings, like reference numerals generally indicate identical, functionally similar, and/or structurally similar elements. The discussion of elements with the same annotations applies to each other, unless mentioned otherwise.
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the process for forming a first feature over a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. As used herein, the formation of a first feature on a second feature means the first feature is formed in direct contact with the second feature. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” and the like may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
It is noted that references in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” “exemplary,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Further, when a particular feature, structure or characteristic is described in connection with an embodiment, it would be within the knowledge of one skilled in the art to effect such feature, structure or characteristic in connection with other embodiments whether or not explicitly described.
It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by those skilled in relevant art(s) in light of the teachings herein.
In some embodiments, the terms “about” and “substantially” can indicate a value of a given quantity that varies within 5% of the value (e.g., +1%, +2%, +3%, +4%, +5% of the value). These values are merely examples and are not intended to be limiting. The terms “about” and “substantially” can refer to a percentage of the values as interpreted by those skilled in relevant art(s) in light of the teachings herein.
An IC die (also referred to as an “IC chip”) can include a compilation of layers with different functionality, such as interconnect structures, power distribution network, logic chips, memory chips, and the like. An IC die package (also referred to as “semiconductor package”) can include multiple IC dies disposed on and electrically connected to routing layers having interposer structures, which can be disposed on and electrically connected to a package substrate. The routing layers and package substrate can provide electrical connections (also referred to as “signal transmission paths” or “metal routings”) between IC dies on the same routing layer and/or between IC dies on different routing layers.
The IC die can be bonded to the routing layer through top and bottom hybrid bonding structures in a hybrid bonding process. The top hybrid bonding structure can be disposed on and electrically connected to interconnect structures of the IC die. The bottom hybrid bonding structure can be disposed on and electrically connected to metal lines in the routing layer. Each of the top and bottom hybrid bonding structures can include a dielectric layer and conductive structures disposed in the dielectric layer. The top surfaces (also referred to as “bonding surfaces”) of the top and bottom hybrid bonding structures to be bonded can be brought in contact during the hybrid bonding process to form fusion bonds between the dielectric layers (e.g., oxide-to-oxide bonds) and between the conductive structures (e.g., metal-to-metal bonds).
One of the challenges of manufacturing strong and reliable bonds between the top and bottom hybrid bonding structures is achieving surface planarity of the bonding surfaces of the conductive structures without compromising the cost of fabricating the IC die packages. Inadequate planarization of the bonding surfaces of the conductive structures can result in weak fusion bonds between the conductive structures. The presence of weak fusion bonds can lead to delamination of the top and bottom hybrid bonding structures at the edges or other locations of the IC dies. Another challenge is preserving the reliability and integrity of the fusion bonds between the dielectric layers and of the elements of the IC dies during the high temperature anneal process performed in the hybrid bonding process. The high temperature anneal process can be performed for diffusing the conductive structures into each other at the bonding interfaces to form the metal-to-metal bonds.
To address the abovementioned challenges, the present disclosure provides example top and bottom hybrid bonding structures in IC die packages with stronger bonds, better manufacturing process control, and reduced susceptibility to delamination. The present disclosure also provides methods of forming the top and bottom hybrid bonding structures with shorter planarization process times and lower bonding process temperatures. In some embodiments, the top hybrid bonding structure can include a first dielectric layer and a first conductive structure disposed in the first dielectric layer. The first conductive structure can include a first pad with an anchor portion that protrudes over a top surface of the first dielectric layer. In some embodiments, the bottom hybrid bonding structure can include a second dielectric layer and a second conductive structure disposed in the second dielectric layer. The second conductive structure can include a second pad and an anchor layer disposed on the second pad.
The anchor layer of the second conductive structure can surround and bond with the anchor portion of the first conductive structure. The material of the anchor layer can promote stronger bonds between the first and second conductive structures compared to bonds formed between first and second conductive structures in other hybrid bonding structures without the anchor layers. In addition, the material of the anchor layer can promote the bonding of the first and second conductive structures through the anchor layer at lower bonding process temperatures than that used in direct bonding of first and second conductive structures in other hybrid bonding structures without the anchor layers. In some embodiments, the anchor layer can include a metallic layer with a material having a melting temperature lower than that of the metallic materials of the first and second pads. The anchor layer can further include an intermetallic compound (IMC) layer (also referred to as a “metal alloy layer”) formed between the metallic layer of the anchor layer and the anchor portion of the first pad. The IMC layer can include a combination of the materials of the first pad and the metallic layer and have a melting temperature higher than that of the materials of the first and second pads.
Referring to
In some embodiments, routing layer 104 can include an interposer structure having (i) a semiconductor substrate 104A, (ii) conductive through-vias 104B disposed in semiconductor substrate 104A, (iii) a dielectric layer 104C disposed on semiconductor substrate 104A, (iv) metal lines 104D disposed in dielectric layer 104C, and (v) metal vias 104E disposed in dielectric layer 104C. In some embodiments, semiconductor substrate 104A can include a silicon substrate. In some embodiments, conductive through-vias 104B can include a metal (such as copper and aluminum), a metal alloy (such as copper alloy and aluminum alloy), or a combination thereof. In some embodiments, dielectric layer 104C can include a stack of dielectric layers. In some embodiments, routing layer 104 can be electrically bonded to an underlying package substrate (not shown) through conductive bonding structures 110. In some embodiments, each of conductive bonding structures 110 can include copper (Cu) bumps 110A and solder bumps 110B. The package substrate can be disposed on and electrically connected to a circuit board (not shown) and can electrically connect IC die package 100 to external devices through the circuit board.
Referring to
The following discussion of first conductive structure 122 in region 101 applies to other first conductive structures 122 of
Embedded portion 122e can be disposed in first dielectric layer 120 and in contact with first via 122B. In some embodiments, embedded portion 122e can have a width W1 greater than a width W2 of anchor portion 122p. In some embodiments, embedded portion 122e and first via 122B can be surrounded by first liner 122C and anchor portion 122p can be liner-free. A top surface of first liner 122C can be substantially coplanar with top surface 120t of first dielectric layer 120. In some embodiments, first pad 122A and first via 122B can include the same conductive material, such as copper (Cu), cobalt (Co), aluminum (Al), any other suitable conductive material, and a combination thereof. In some embodiments, first liner 122C can include a conductive material the same as or different from the material of first pad 122A and first via 122B. In some embodiments, first liner 122C can include titanium (Ti), Cu, or other suitable conductive material.
In some embodiments, second hybrid bonding structure 118 can include a second dielectric layer 124 and one or more second conductive structures 126 disposed in second dielectric layer 124. Though six second conductive structures 126 are shown in second hybrid bonding structure 118, any number of second conductive structures 126 can be included in second hybrid bonding structure 116. In some embodiments, second dielectric layer 124 can include a dielectric material the same as or different from first dielectric layer 120. First and second dielectric layers 120 and 124 can be bonded to each other through dielectric-to-dielectric fusion bonds, and first and second conductive structures 122 and 126 can be bonded to each other through metal-to-metal fusion bonds or solder bonds, as described in detail below. In some embodiments, the number of second conductive structures 126 can be equal to the total number of first conductive structures 122. Each second conductive structure 126 can be bonded to a corresponding one of first conductive structures 122.
The following discussion of second conductive structure 126 in region 101 applies to other second conductive structures 126 of
Anchor layer 126D can be disposed between first pad 122A and second pad 126A. A first side of anchor layer 126D can surround anchor portion 122p of first pad 122 and can be fusion or solder bonded to top surface 122pt and side surfaces of anchor portion 122p. A second side of anchor layer 126D can be fusion or solder bonded to top surface 126At of second pad 126A. The material of anchor layer 126D in addition to anchor portion 122p being enclosed by anchor layer 126D can promote stronger bonding and reduced delamination between first and second conductive structures 122 and 126 compared to that between first and second conductive structures in other hybrid bonding structures without anchor layer 126D and/or anchor portions 122p. As electrical connections between the elements of IC dies 112 and routing layer 104 can be made through first and second conductive structures 122 and 126, stronger bonds with reduced susceptibility to delamination between first and second conductive structures 122 and 126 increases reliability of IC die package 100. In addition, the material of anchor layer 126D can promote the bonding of first and second conductive structures 122 and 126 through anchor layer 126D at lower bonding process temperatures than that used in direct bonding of first and second conductive structures in other hybrid bonding structures without anchor layer 126D, as described in detail below.
Referring to
In some embodiments, second IMC layer 126D3 can be formed at an interface between second pad 126A and metal layer 126D1 and can include an IMC having a melting temperature higher than that of the materials of second pad 126A and metal layer 126D1. The IMC of second IMC layer 126D3 can include a combination of the materials of second pad 126A and metal layer 126D1. In some embodiments, second IMC layer 126D3 can include Cu and Sn when second pad 126A includes Cu and metal layer 126D1 includes Sn. In some embodiments, the IMCs of first and second IMC layers 126D2 and 126D3 can be the same as each other when the materials of first and second pads 122A and 126A are the same. In some embodiments, the IMCs of first and second IMC layers 126D2 and 126D3 can be different from each other when the materials of first and second pads 122A and 126A are different from each other. The IMCs of first and second IMC layers 126D2 and 126D3 can provide stronger bonding between first and second pads 122A and 126A compared to first and second conductive structures bonded directly to each other without IMCs.
Referring to
Referring to
Referring to
A bottom surface of each first hybrid bonding structure 216 can be disposed on and electrically connected to interconnect structures 114 of a corresponding IC die 112. A top surface of each first hybrid bonding structure 216 can be disposed on and bonded to second hybrid bonding structure 218 through hybrid bonds. In some embodiments, each first hybrid bonding structure 216 can include a first dielectric layer 120 and one or more first conductive structures 222 disposed in first dielectric layer 120. In some embodiments, each first conductive structure 222 can have the same structure and composition of second conductive structure 126 described above with reference to
In some embodiments, second hybrid bonding structure 218 can include a second dielectric layer 124 and one or more second conductive structures 226 disposed in second dielectric layer 124. In some embodiments, each second conductive structure 226 can have the same structure and composition of first conductive structure 122 described above with reference to
Referring to
Referring to
In some embodiments, the conductive material of second pads 126A can be deposited to fill pad openings 826A up to a distance D4 of about 1 μm to about 2 μm below top surfaces 124t of second dielectric layer 124. In some embodiments, conductive layer 1026 can be deposited with a thickness D5 of about 0.5 μm to about 1.5 μm and to fill pad openings 826A on second pads 126A up to a distance D6 of about 50 nm to about 200 nm below top surfaces 124t of second dielectric layer 124. In some embodiments, operations (iii) and (viii) can be omitted to form second hybrid bonding structure 118 without second liner 126C as shown in
Referring to
In some embodiments, anchor portions 122p may be not be in contact with conductive layers 1026 after the aligning in operation (ii) and there may be air gaps present between anchor portions 122p and conductive layers 1026, as shown in
With the use of anchor layers 126D (or anchor layers 130) to bond first and second pads 122A and 126A, the anneal process can be performed at the melting temperature of the material (e.g., Sn or In) of conductive layer 1026, which is lower than the melting temperature of the material (e.g., Cu) of first and second pads 122A and 126A. In some embodiments, the anneal process can be performed at a temperature below about 200° C. (e.g., at a temperature of about 150° C. to about 180° C.) when conductive layer 1026 includes Sn or In.
Referring to
Referring to
Also, system or device 1600 can be implemented in a wearable device 1660, such as a smartwatch or a health-monitoring device. In some embodiments, the smartwatch can have different functions, such as access to email, cellular service, and calendar functions. Wearable device 1660 can also perform health-monitoring functions, such as monitoring a user's vital signs and performing epidemiological functions (e.g., contact tracing and providing communication to an emergency medical service). Wearable device 1660 can be worn on a user's neck, implantable in user's body, glasses or a helmet designed to provide computer-generated reality experiences (e.g., augmented and/or virtual reality), any other suitable wearable device, and combinations thereof.
Further, system or device 1600 can be implemented in a server computer system, such as a dedicated server or on shared hardware that implements a cloud-based service 1670. System or device 1600 can be implemented in other electronic devices, such as a home electronic device 1680 that includes a refrigerator, a thermostat, a security camera, and other suitable home electronic devices. The interconnection of such devices can be referred to as the “Internet of Things” (IoT). System or device 1600 can also be implemented in various modes of transportation 1690, such as part of a vehicle's control system, guidance system, and/or entertainment system. The systems and devices illustrated in
It is to be appreciated that the Detailed Description section, and not the Abstract of the Disclosure section, is intended to be used to interpret the claims. The Abstract of the Disclosure section may set forth one or more but not all possible embodiments of the present disclosure as contemplated by the inventor(s), and thus, are not intended to limit the subjoined claims in any way.
Unless stated otherwise, the specific embodiments are not intended to limit the scope of claims that are drafted based on this disclosure to the disclosed forms, even where only a single example is described with respect to a particular feature. The disclosed embodiments are thus intended to be illustrative rather than restrictive, absent any statements to the contrary. The application is intended to cover such alternatives, modifications, and equivalents that would be apparent to a person skilled in the art having the benefit of this disclosure.
The foregoing disclosure outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
