The semiconductor industry has grown due to continuous improvements in integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, these improvements in integration density have come from successive reductions in minimum feature size, which allows more components to be integrated into a given area.
In addition to smaller electronic components, improvements to the packaging of components have been developed in an effort to provide smaller packages that occupy less area than previous packages. Example approaches include quad flat pack (QFP), pin grid array (PGA), ball grid array (BGA), flip chips (FC), three-dimensional integrated circuits (3DICs), wafer level packages (WLPs), package on package (POP), System on Chip (SoC) or System on Integrated Circuit (SoIC) devices. Some of these three-dimensional devices (e.g., 3DIC, SoC, SoIC) are prepared by placing chips over chips on a semiconductor wafer level. These three-dimensional devices provide improved integration density and other advantages, such as faster speeds and higher bandwidth, because of the decreased length of interconnects between the stacked chips. However, there are many challenges related to three-dimensional devices.
Aspects of this disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Unless explicitly stated otherwise, each element having the same reference numeral is presumed to have the same material composition and to have a thickness within a same thickness range.
In various embodiments, bonding of an integrated circuit die to a target substrate, such as a semiconductor wafer, may be accomplished using a flip-chip direct bonding process. In a flip-chip direct bonding process, a semiconductor integrated circuit (IC) die (which may also be referred to as a “chip”) may be picked up using a first tool, flipped over, and placed onto the head of a die bonding tool. The die bonding tool may align the semiconductor IC die over a bonding region of the target substrate and may apply a compressive force to the semiconductor IC die to bond the semiconductor IC die to the bonding region of the target substrate.
The head of the die bonding tool may include a vacuum suction port that may be used to temporarily secure the semiconductor IC die to the head of the die bonding tool via application of a suction force while the die bonding tool aligns the semiconductor IC die over the bonding region of the target substrate. When the semiconductor IC die is properly aligned over and brought into contact with the bonding region of the target substrate, the suction force from the vacuum port may be released causing the semiconductor IC die to be released from the head of the die bonding tool. In many cases, the semiconductor IC dies may include a natural warping or deformation, such as a bow- or cup-shaped deformation. When the semiconductor IC die is released from the head of the die bonding tool, the natural warpage of the semiconductor IC die may result in air becoming trapped between the lower surface of the semiconductor IC die and the upper surface of the bonding region of the target substrate. As the die bonding tool applies a compressive force to the semiconductor IC die during the bonding process, the trapped air may be pushed toward the edges of the semiconductor IC die, which may result in poor or defective bonding between the semiconductor IC die and the target substrate, particularly near the peripheral edges and corner regions of the semiconductor IC die. These defective bonds may reduce overall device yields.
In order to improve the bonding between a semiconductor IC die and a target substrate, various embodiments of the present disclosure are directed to a die bonding tool having a tool head including a plurality of openings (e.g., ports) fluidly coupled to a vacuum source and configured to selectively secure a semiconductor IC die onto the tool head via the application of a suction force on the semiconductor IC die. In various embodiments, the plurality of openings may have non-uniform cross-sectional areas. In some embodiments, one or more first openings of the plurality of openings may have a first cross-sectional area and one or more second openings of the plurality of opening may have a second cross-sectional area that is greater than the first cross-sectional area. In some embodiments, a minimum offset distance between each of the first openings and a peripheral edge of the tool head may be less than a minimum offset distance between each of the second openings and a peripheral edge of the tool head.
Accordingly, the second openings which are further from a peripheral edge of the semiconductor IC die than the first openings may have a larger cross-sectional area and thereby apply a greater suction force over a larger area of the semiconductor IC die. This may help to keep the semiconductor IC die relatively flat against a surface of the tool head while the semiconductor IC die is secured to the tool head. In addition, when the semiconductor IC die is released from the tool head, the non-uniform hole sizes enable the semiconductor IC die to be released gradually, with regions of the semiconductor IC die located closer to the center of the die being initially released from the tool head, and regions of the semiconductor IC die located closer to the peripheral edges of the die being subsequently released from the tool head. This may inhibit the formation of air pockets between the lower surface of the semiconductor IC die and the upper surface of the bonding region of the carrier substrate, which may improve the integrity of the bonding between the semiconductor IC die and the carrier substrate and may provide improved device yields.
The semiconductor IC die 102 may include a semiconductor material, such as silicon, having a number of circuit components and elements formed on and/or within the semiconductor material. Semiconductor IC dies 102 are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductive layers of material over a semiconductor substrate, patterning the various material layers using lithography to form integrated circuits, and separating individual dies from the wafer such as by sawing between the integrated circuits along scribe lines. In some embodiments, the semiconductor IC die 102 may be a system-on-chip (SoC) die. An SoC die may include, for example, an application processor die, a central processing unit die, and/or a graphic processing unit die. In some embodiments, the semiconductor IC die 102 may be a memory die. A memory die may include, for example, a dynamic random access memory (DRAM) die, and/or a high bandwidth memory (HBM) die. Other suitable semiconductor IC dies 102, such as an application-specific integrated circuit (ASIC) die, an analog die, a sensor die, a wireless and radio frequency die, a voltage regulator die, and the like, are within the contemplated scope of disclosure.
In various embodiments, the semiconductor IC die 102 may have a thickness of 775 μm or less, although semiconductor IC dies 102 having greater thicknesses are within the contemplated scope of the disclosure. In some embodiments, the semiconductor IC die 102 may be a relatively thin die having a thickness of about 200 μm or less, such as a thickness between about 30 μm and about 200 μm. Thinner IC dies may be susceptible to deformations such as warping. In various embodiments, the suction force on the semiconductor IC die 102 that is provided by the plurality of openings 115a and 115b in the tool head 101 of the die bonding tool 100 may secure the semiconductor IC die 102 against the lower surface 113 of the tool head 101 in a substantially flat (i.e., non-deformed) position.
A die bonding tool 100 according to various embodiments may be used to bond a semiconductor IC die 102 to a target substrate 104.
The die bonding tool 100 may include a system controller 111, which may be central processing unit (CPU), that may be operatively coupled to the vacuum source 110 and to an actuator system (not shown in
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In various embodiments, the semiconductor IC die 102 may be bonded to the target substrate 104 using a direct bonding technique, such as a metal-metal (M-M) and dielectric-dielectric (D-D) bonding technique. In some embodiments, the semiconductor IC die 102 may include a bonding layer BL over the lower surface of the semiconductor IC die 102 including plurality of bonding pads 106 composed of a metallic material (e.g., copper) embedded in a dielectric material matrix 112. The target substrate 104 may similarly include a bonding layer BL over the upper surface of the target substrate 104 including a plurality of bonding pads 108 embedded in a dielectric material matrix 112. In various embodiments, the bonding layer(s) of the semiconductor IC die 102 and/or the target substrate 104 may optionally be pre-treated to promote surface activation (e.g., using a plasma treatment process). The lower surface of the semiconductor IC die 102 and the upper surface of the target substrate 104 may contact each other such that the bonding pads 106 of the bonding layer BL of the semiconductor IC die 102 contact corresponding bonding pads 108 of the bonding layer BL of the target substrate 104. The compressive force applied by the tool head 101 of the die bonding tool 100 may facilitate bonding of the bonding layer BL of the semiconductor IC die 102 and the bonding layer BL of the target substrate 104. In some embodiments, the bonding may be performed at room temperature (e.g., ˜20° C.). The target substrate 104 and the semiconductor IC die 102 bonded thereto may optionally be subjected to a subsequent annealing process at elevated temperature to strengthen the bond between the target substrate 104 and the semiconductor IC die 102.
It will be understood that other bonding processes may be used to bond the semiconductor IC die 102 to the target substrate 104. For example, a thermocompression bonding (TCB) process may be utilized to bond metallic structures (e.g., metal bumps, pillars and/or bonding pads) on the lower surface of the semiconductor IC die 102 to corresponding metallic structures (e.g., metal bumps, pillars and/or bonding pads) on the upper surface of the target substrate 104. The tool head 101 of the die bonding tool 100 may apply a compressive force to the semiconductor IC die 102 while the semiconductor IC die 102 and the target substrate 104 are heated. In some embodiments, the semiconductor IC die 102 and the target substrate 104 may be heated by a heating mechanism (not shown) located on the die bonding tool 100. With the applied pressure and the elevated temperature, surface portions of the metallic structures of the semiconductor IC die 102 and the metallic structures of the target substrate 104 may inter-diffuse, so that bonds may be formed therebetween. In some embodiments, the bonding between the semiconductor IC die 102 and the target substrate 104 may be performed without the use of solder material. In other embodiments, a solder material may be used to bond bonding structures of the semiconductor IC die 102 to corresponding bonding structures of the target substrate 104.
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In various embodiments, the second openings 115b located closer to the center of the lower surface 113 of the tool head 101 may provide a relatively greater suction force near the central region of the semiconductor IC die 102 due to the relatively larger second cross-section area of the second openings 115b as compared to the first cross-section area of the first openings 115a. This may help to maintain the semiconductor IC die 102 in a relatively flat position against the lower surface 113 of the tool head 101 prior to semiconductor IC die 102 being released from the tool head 101. In addition, the arrangement of the openings 115a and 115b in the lower surface 113 of the tool head 101 such that the larger second openings 115b are located closer to the center of the lower surface 113 of the tool head 101 while the smaller first openings 115a are located closer to the peripheral edge(s) 201, 202, 203 and 204 of the lower surface 113 may facilitate a gradual release of the semiconductor IC die 102 from the tool head 101. In particular, regions of the semiconductor IC die 102 underlying the larger second openings 115b and closer to the center of the semiconductor IC die 102 may be released from the tool head 101 prior to the release of peripheral regions of the semiconductor IC die 102 underlying the smaller first openings 115a. This gradual release of the semiconductor IC die 102 from a more central region of the die to the periphery of the semiconductor IC die 102 may prevent air from becoming trapped between the lower surface of the semiconductor IC die 102 and the upper surface of the carrier substrate 104, which may improve the integrity of the bonding between the semiconductor IC die 102 and the carrier substrate 104 and thereby provide improved device yields. Thus, by providing the larger openings 115b interior to the smaller openings 115a, upon release of suction force, interior portions of the semiconductor IC die 102 may contact the upper surface of the carrier substrate 104 prior to or simultaneous with exterior portions of the semiconductor IC die 102 contacting the semiconductor IC die 102, thus enabling air located between the lower surface of the semiconductor IC die 102 and the upper surface of the carrier substrate 104 to escape out along the peripheral edges and corners of the semiconductor IC die 102 without becoming trapped.
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In various embodiments, the lower surface 113 of the tool head 101 may include a plurality of first openings 115a, a plurality of second openings 115b and a plurality of third openings 115c. The plurality of first openings 115a and the plurality of second openings 115b may be arranged such that the minimum first offset distance Off1 of each of the first openings 115a is less than the minimum second offset distances Off2 of each of the second openings 115b. In some embodiments, the plurality of third openings 115c may be arranged such that the minimum third offset distance Off3 of each of the third openings 115c is less than the minimum second offset distances Off2of each of the second openings 115b and greater than the minimum first offset distances Off1 of each of the first openings 115a. In the embodiment shown in
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Referring to all drawings and according to various embodiments of the present disclosure, a die bonding tool 100 includes a tool head 101 having a lower surface 113 having a plurality of openings 115a, 115b therein, and a vacuum source 110 fluidly coupled to the plurality of openings 115a, 115b in the lower surface 113 of the tool head 101 and configured to selectively generate a suction force at each of the plurality of openings 115a, 115b to temporarily secure a semiconductor die 102 against the lower surface 113 of the tool head 101, where the tool head 101 is configured to apply a compressive force on the semiconductor die 102 to bond the semiconductor die 102 to a substrate 104, and the plurality of openings 115a, 115b in the lower surface 113 of the tool head 101 include at least one first opening 115a having a first cross-section area and a first minimum offset distance Off1 between the at least one first opening 115a and any peripheral edge 201, 202, 203, 204 of the lower surface of the tool head 113, at least one second opening 115b having a second cross-section area that is greater than the first cross-section area, and a second minimum offset distance Off2 between the at least one second opening 115b and any peripheral edge 201, 202, 203, 204 of the lower surface 113 of the tool head 101 that is greater than the first minimum offset distance Off1.
In one embodiment, the plurality of openings 115a, 115b in the lower surface 113 of the tool head 101 include a plurality of first openings 115a having the first cross-section area and a plurality of second openings 115b having the second cross-section area, wherein the first minimum offset distance Off1 between one of the plurality of first openings 115a and any peripheral edge 201, 202, 203, 204 of the lower surface 113 of the tool head 101 is less than the second minimum offset distance Off2 between one of the plurality of second openings 115b and any peripheral edge 201, 202, 203, 204 of the lower surface 113 of the tool head 101.
In another embodiment, the plurality of second openings 115b are arranged in a first column of second openings 115b and a second column of second openings 115b located on opposite sides of a center of the lower surface 113 of the tool head 101, and the plurality of first openings 115a are disposed between the first column of second openings 115b and a peripheral edge 201, 202, 203, 204 of the lower surface 113 of the tool head 101 on three sides of the first column of second openings 115b, and wherein the plurality of first openings 115a are disposed between the second column of second openings 115b and a peripheral edge 201, 202, 203, 204 of the lower surface 113 of the tool head 101 on three sides of the second column of second openings 115b.
In another embodiment, the plurality of second openings 115b further include a third column of second openings 115b extending through the center of the lower surface 113 of the tool head 101, and the plurality of first openings 115a extend around the columns of second openings 115b on four sides of the columns of second openings 115b.
In another embodiment, the plurality of second openings 115b extend around a center of the lower surface 113 of the tool head 101 on four sides of the center of the lower surface 113 of the tool head 101, and the plurality of first openings 115a extend around the plurality of second openings 115b on four sides of the plurality of second openings 115b.
In another embodiment, the plurality of openings in the lower surface 113 of the tool head 101 comprise at least one third opening 115c having a third cross-section area that is greater than the first cross-section area and less than the second cross-section area.
In another embodiment, a third minimum offset distance Off3 between the at least one third opening 115c and any peripheral edge 201, 202, 203, 204 of the lower surface 113 of the tool head 101 is greater than the first minimum offset distance Off1 and is less than the second minimum offset distance Off2.
In another embodiment, the second cross-section area of the at least one second opening 115b is at least two times greater than the first cross-section area of the at least one first opening 115a.
In another embodiment, the tool head includes an internal plenum 117 and a plurality of fluid conduits 116 extending between the internal plenum 117 and the plurality of openings 115a, 115b in the lower surface 113 of the tool head 101, and the die bonding tool 100 further includes a fluid conduit 119 that fluidly couples the internal plenum 117 to the vacuum source 110.
In another embodiment, the die bonding tool 100 further includes a system controller 111 coupled to the vacuum source 110 and to an actuator system, where the system controller 111 is configured to control the vacuum source 110 to generate the suction force at each of the plurality of openings 115a, 115b that are configured to temporarily secure the semiconductor die 102 against the lower surface 113 of the tool head 101, control the actuator system to align the semiconductor die 102 over a bonding region 109 of the substrate 104, control the actuator system to bring the semiconductor die 102 into contact with the bonding region 109 of the substrate 104, provide an ambient or positive pressure at the plurality of openings 115a, 115b to release the semiconductor die 102 from the lower surface 113 of the tool head 101, and control the actuator system to apply the compressive force on the semiconductor die 102 to bond the semiconductor die 102 to the substrate 104.
In one embodiment, the actuator system may be configured to move the tool head 101 to align the semiconductor die 102 over a bonding region 109 of the substrate 104, and to bring the semiconductor die 102 into contact with the bonding region 109 of the substrate 104. In another embodiment, the actuator system may be configured to move the substrate 104 to align the semiconductor die 102 over a bonding region 109 of the substrate 104, and to bring the semiconductor die 102 into contact with the bonding region 109 of the substrate 104.
Another embodiment is drawn to a tool head 101 for a die bonding tool 100 that includes a lower surface 113 having a plurality of openings 115a, 115b configured to apply a suction force to secure a semiconductor die 102 against the lower surface 113, where the plurality of openings 115a. 115b have non-uniform sizes, and a ratio of a dimension d2 of the largest opening 115b of the plurality of openings 115a, 115b to a smallest opening 115a of the plurality of openings 115a, 115b is equal to or greater than 1.5 and less than or equal to 3.5.
In one embodiment, each of the openings 115a, 115b has a circular cross-section shape, and the dimension of each of the openings 115a, 115b is a diameter of each of the openings 115a, 115b.
In another embodiment, the diameters of each of the openings 115a, 115b are between 0.1 mm and 1.75.
In another embodiment, the smallest openings 115a are located most proximate to a periphery 201, 202, 203, 204 of the lower surface 113 and a size of the openings 115a, 115b increases towards a center of the lower surface 113.
Another embodiment is drawn to a method of bonding a semiconductor die 102 to a substrate 104 that includes securing a semiconductor die 102 to a tool head 101 for a temporary period using a suction force applied through a plurality of openings 115a, 115b in a lower surface 113 of the tool head 101, the plurality of openings 115a, 115b including at least one first opening 115a having a first cross-section area and at least one second opening 115b having a second cross-section area that is greater than the first cross-section area, and the semiconductor die 102 is secured to the tool head 101 such that a first minimum distance between the at least one first opening 115a and any peripheral edge 201, 202, 203, 204 of the semiconductor die 102 is less than a second minimum distance between the at least one second opening 115b and any peripheral edge 201, 202, 203, 204 of the semiconductor die 102, positioning the semiconductor die 102 over a bonding region 109 of a substrate 104, releasing the application of the suction force on the semiconductor die 102 such that a central region of the semiconductor die 102 contacts the bonding region 109 of the substrate 104 prior to or simultaneous with a peripheral region of the semiconductor die 10 contacting the bonding region 109 of the substrate 104, and applying a compressive force to the semiconductor die 102 to bond the semiconductor die 102 to the bonding region 109 of the substrate 104.
In one embodiment, the semiconductor die 102 is bonded to the substrate 104 using a direct bonding process.
In another embodiment, the direct bonding process is performed at room temperature.
In another embodiment, length and width dimensions L1, L2 of the lower surface 113 of the tool head 101 are ±10% of corresponding length and width dimensions of the semiconductor die 104.
In another embodiment, securing the semiconductor die 102 to the tool head 101 for a temporary period includes providing the semiconductor die 102 having bonding structures 106 located on an upper surface of the semiconductor die 102, securing the semiconductor die 102 to a flip tool 307 using an ejector apparatus 305, inverting the semiconductor die 102 on the flip tool 307 such that the bonding structures 106 are located on a lower surface of the semiconductor die 102, contacting the surface of the semiconductor die 102 opposite to the bonding structures 106 to the lower surface 113 of the tool head 101 to secure the semiconductor die 102 to the tool head 101, and releasing the semiconductor die 102 from the flip tool 307.
In another embodiment, positioning the semiconductor die 102 over a bonding region 109 of a substrate 104 includes moving the tool head 101 in a horizontal direction with respect to the substrate 104 to align the semiconductor die 102 over the bonding region 109 of the substrate 104, moving the tool head 101 in a vertical direction with respect to the substrate 104 to bring the semiconductor die 102 into contact with the bonding region 109 of the substrate 104 such that the bonding structures 106 on the lower surface of the semiconductor die 102 contact corresponding bonding structures 108 on the bonding region 109 of the substrate 104.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of this disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.