Patent Application
20220148969
The present invention relates generally to a semiconductor structure and a method of forming the same. More particularly, the present invention relates to a semiconductor structure that includes a buried power rail for aggressively scaled vertical transport field effect transistor (VTFET).
Fabricating smaller, more densely packed devices having greater computing capability is a continuing objective in building semiconductor devices. In designing semiconductor devices, each cell of the device requires power input (Vdd) and ground (Vss) connections. To power the various components, each cell is also coupled to a power rail which is electrically connected to an active layer of the cell to provide the input power (Vdd). In some instances, a plurality of power rails may be provided for each cell to respectively provide the input power (Vdd) and the ground (Vss).
According to one embodiment of the present invention, a semiconductor structure is provided. The semiconductor structure may include a buried power rail under a bottom source drain of a vertical transistor and a dielectric bi-layer under the bottom source drain. The dielectric bi-layer may be between the buried power rail and the bottom source drain. The semiconductor structure may include a silicon germanium bi-layer under the bottom source drain, the silicon germanium bi-layer may be adjacent to the buried power rail. The buried power rail may be made of tungsten or ruthenium. The semiconductor structure may include a buried power rail contact. The buried power rail contact may connect the bottom source drain to the buried power rail. The dielectric bi-layer may include a first dielectric layer and a dielectric liner. The first dielectric layer may be in direct contact with the bottom source drain. The dielectric liner may surround the buried power rail. The dielectric liner may isolate the buried power rail from the dielectric bi-layer. The silicon germanium bi-layer may include a first semiconductor layer and a second semiconductor layer below the first semiconductor layer. The second semiconductor layer may be in direct contact with the first semiconductor layer. The first semiconductor layer may include 30% germanium and the second semiconductor layer may include 60% germanium. The semiconductor structure may include a third semiconductor layer. The third semiconductor layer may be directly below the bottom source drain. The third semiconductor layer may be made of silicon. The semiconductor structure may also include a top source drain, a fin, and a metal gate. The fin may be between the top source drain and the bottom source drain. The metal gate may be adjacent and in direct contact with the fin.
According to another embodiment of the present invention, a semiconductor structure is provided. The semiconductor structure may include a buried power rail under a bottom source drain of a vertical transistor, a dielectric bi-layer under the bottom source drain, and a buried power rail contact. The dielectric bi-layer may be between the buried power rail and the bottom source drain. The buried power rail contact may connect the bottom source drain to the buried power rail. The buried power rail may be made of tungsten or ruthenium. The dielectric bi-layer may include a first dielectric layer and a dielectric liner. The first dielectric layer may be in direct contact with the bottom source drain. The dielectric liner may surround the buried power rail. The semiconductor structure may include a top source drain, a fin, and a metal gate. The fin may be between the top source drain and the bottom source drain. The metal gate may be adjacent and in direct contact with the fin. The semiconductor structure may include a semiconductor layer. The semiconductor layer may be directly below the bottom source drain. The semiconductor layer may be made of silicon.
According to another embodiment of the present invention, a method is provided. The method may include epitaxially growing a silicon germanium bi-layer on a substrate, epitaxially growing a third semiconductor layer on the silicon germanium bi-layer, forming one or more vertical fins and one or more bottom source drains within the third semiconductor layer. The one or more bottom source drains may be below the one or more vertical fins. The method may include laterally etching portions of the silicon germanium bi-layer and the third semiconductor layer to form one or more first indentations, forming a first dielectric layer within the one or more indentations. The first dielectric layer may be directly below the one or more bottom source drain. The method may include laterally etching portions of the first semiconductor layer to form one or more second indentations, depositing a dielectric liner within the one or more second indentations, and forming one or more buried power rails within the one or more second indentations. The one or more buried power rails may be directly below the one or more bottom source drains. The dielectric liner may separate the one or more buried power rails from the first dielectric layer. The silicon germanium bi-layer may include a first semiconductor layer and a second semiconductor layer. The first semiconductor layer may include 30% germanium and the second semiconductor layer may include 60% germanium. The third semiconductor layer may be made of silicon. The method may include forming a shallow trench isolation between the one or more vertical fins and forming one or more bottom source drain contacts. The one or more bottom source drain contacts may connect the one or more bottom source drains with the one or more buried power rails. The shallow trench isolation may extend through the third semiconductor layer, the silicon germanium bi-layer, and a portion of the substrate. The method may also include forming one or more top source drains on top of the one or more fins, forming a metal gate between the one or more fins, forming one or more top source drain contacts, and forming one or more gate contacts.
The following detailed description, given by way of example and not intend to limit the invention solely thereto, will best be appreciated in conjunction with the accompanying drawings, in which:
The drawings are not necessarily to scale. The drawings are merely schematic representations, not intended to portray specific parameters of the invention. The drawings are intended to depict only typical embodiments of the invention. In the drawings, like numbering represents like elements.
Detailed embodiments of the claimed structures and methods are disclosed herein; however, it can be understood that the disclosed embodiments are merely illustrative of the claimed structures and methods that may be embodied in various forms. This invention may, however, be embodied in many different forms and should not be construed as limited to the exemplary embodiment set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of this invention to those skilled in the art. In the description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments.
For purposes of the description hereinafter, the terms “upper”, “lower”, “right”, “left”, “vertical”, “horizontal”, “top”, “bottom”, and derivatives thereof shall relate to the disclosed structures and methods, as oriented in the drawing figures. The terms “overlying”, “atop”, “on top”, “positioned on” or “positioned atop” mean that a first element, such as a first structure, is present on a second element, such as a second structure, wherein intervening elements, such as an interface structure may be present between the first element and the second element. The term “direct contact” means that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediary conducting, insulating or semiconductor layers at the interface of the two elements.
In the interest of not obscuring the presentation of embodiments of the present invention, in the following detailed description, some processing steps or operations that are known in the art may have been combined together for presentation and for illustration purposes and in some instances may have not been described in detail. In other instances, some processing steps or operations that are known in the art may not be described at all. It should be understood that the following description is rather focused on the distinctive features or elements of various embodiments of the present invention.
Embodiments of the present invention relate generally to a semiconductor structure and a method of forming the same. More particularly, the present invention relates to a semiconductor structure that includes a buried power rail for aggressively scaled vertical transport field effect transistor (VTFET).
Power rails may be used in circuit to supply current to the devices. Conventionally, power rails may be stacked on top of the devices, or buried between the devices. The buried power rails are typically formed in the shallow trench isolation (STI) regions between the transistors. Currently, with aggressive cell scaling, more transistors are fabricated on the same or even smaller footprint. As a result, the space for STI also shrinks. Burying the power rails in the STI regions does not allow buried power to have adequate size to deliver the current. As such, there exists a need for a structure and a method of fabricating a power rail that not only provides current to the increased number of transistors but also fits within the scaled down footprint.
Embodiments of the present invention propose a structure and a method for fabricating a power rail that is buried directly under an active region of a transistor, thus no longer limiting the scaling of the footprint. Further, the location of the resultant buried power rail enables a bottom source drain to have a contact with that buried power rail within the active region, thus saving space within the footprint.
Referring now to
The first semiconductor layer 104 is epitaxially grown on the substrate 102. The second semiconductor layer 106 is then epitaxially grown on a top surface of the first silicon layer 104. The first and the second semiconductor layers 104, 106 are epitaxially grown using epitaxial growth processes, such as, for example molecular beam epitaxy (MBE). Other methods such as rapid thermal chemical vapor deposition (RTCVD), low-energy plasma deposition (LEPD), ultra-high vacuum chemical vapor deposition (UHVCVD), atmospheric pressure chemical vapor deposition (APCVD) may also be used to grow the first and the second semiconductor layers 104, 106. The first semiconductor layer 104 may be grown to a thickness ranging between 30 nm to 200 nm. The second semiconductor layer 106 may be grown to a thickness ranging between 5 nm to 20 nm. The first and the second semiconductor layers 104, 106 may be made of silicon germanium. The germanium percentage in the first semiconductor layer 104 may be around 30%. The germanium percentage in the second semiconductor layer 106 may be around 60%. The first and the second semiconductor layers 104, 106 may collectively be referred to as a silicon germanium bi-layer or a semiconductor bi-layer.
The third semiconductor layer 108 is epitaxially grown on a top surface of the second semiconductor layer 106. The third semiconductor layer 108 may be grown using similar techniques used to grow the first semiconductor layer 104 or the second semiconductor layer 106. The third semiconductor layer 108 may be epitaxially grown to a thickness ranging between 60 nm to 150 nm. The third semiconductor layer 108 may be made of silicon.
The hard mask layer 110 is deposited on a top surface of the third semiconductor layer 108. The hard mask layer 110 may include any dielectric material such as, for example, silicon dioxide, silicon nitride and/or silicon oxynitride. In some embodiments, the hard mask layer 110 can be formed utilizing a conventional deposition process such as, for example, chemical vapor deposition, plasma enhanced chemical vapor deposition, physical vapor deposition, or atomic layer deposition. In other embodiments, the hard mask layer 110 may be formed utilizing a thermal growth process such as, for example, thermal oxidation. In yet other embodiments, the hard mask layer 110 can be formed by a combination of a deposition process and a thermal growth process. The hard mask layer 110 may have a thickness ranging from approximately 10 nm to approximately 150 nm. Other thicknesses for the hard mask layer 110 are possible and can be used in the present application.
Referring now to
Once the fins 112 are patterned, the bottom source drains 116 may be epitaxially grown, using known techniques, such that the bottom source drains 116 form directly below the fins 112. The bottom source drains 116 may be in-situ doped with a p-type dopant or an n-type dopant, forming a p-type or an n-type bottom source drain for a VTFET. For example, the bottom source drains 116 may be made of silicon germanium and in-situ doped with a p-type dopant, such as, for example, boron to form a p-type bottom source drain 116a. The bottom source drains 116 may be made of silicon and in-situ doped with an n-type dopant, such as, for example, phosphorus, to form an n-type bottom source drain 116b.
Referring now to
After the first OPL 118 is deposited, a lithography patterning and dry etch process, such as, for example, a reactive ion etch process may be used to etch the first OPL 118 such that a top portion of the third semiconductor layer 108 is exposed. The top portion of the third semiconductor layer 108 is below the bottom surface of the bottom source drains 116. A spacer layer (now shown) is then conformally deposited onto the top surface of the structure 100. The spacer layer may include an insulating material, such as, for example, silicon dioxide, silicon nitride, SiOCN, or SiBCN. Other non-limiting examples of materials for the spacer layer may include dielectric oxides (e.g., silicon oxide), dielectric nitrides (e.g., silicon nitride), dielectric oxynitrides, or any combination thereof. The spacer layer may be deposited by a deposition process, for example, atomic layer deposition, chemical vapor deposition, or physical vapor deposition. The spacer layer may have a thickness ranging from approximately 3 to approximately 15 nm, or from approximately 5 to approximately 8 nm.
Once conformally deposited, the spacer layer is then etched back to form sidewall spacers 120. To form the sidewall spacers 120, the spacer layer may be etched by a dry etch process, for example, a reactive ion etch process, such that portions of the spacer layer remain on the sidewalls of the bottom source drains 116 and the sidewalls of the first OPL 118. The sidewall spacers 120 protect the sidewalls of the sidewalls of the bottom source drains 116 and the sidewalls of the first OPL 118 from damage during subsequent manufacturing processes.
After the formation of the sidewall spacers 120, another etch process that is selective to (will not substantially remove) the sidewall spacers 120 or the first OPL 118 may be used to further recess the third semiconductor layer 108, the second semiconductor layer 106, and a portion of the first semiconductor layer 104. The etch process may be, for example, a reactive ion etch process. Recessing the third semiconductor layer 108, the second semiconductor layer 106, and a portion of the first semiconductor layer 104 exposes sidewalls of the three layers directly below the sidewall spacers 120.
Referring now to
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The metal layer is then planarized and recessed, using a CMP and an etch process, such as, for example, a reactive ion etch process, to form the buried power rails 130. The buried power rails 130 are formed within the second indentations 126, illustrated in
Referring now to
After the second OPL 132 is deposited, an etch process, such as, for example, a reactive ion etch process, may be used to remove portions of the OPL 132 between the two vertical fins 112. Further, the etch process removes portions of the dielectric liner 128, the bottom source drains 116, the third semiconductor layer 108, the second semiconductor layer 106, and the first semiconductor layer 104 between the two vertical fins 112, thereby forming the trench 134. The trench 134 extends vertically from the top surface of the dielectric liner 128 to the exposed top surface of the substrate 102.
Referring now to
The oxide material is also deposited on the sides of the fins 112, above the buried power rails 130, forming a second dielectric layer 138. After the STI 136 is formed, the second OPL 132 is removed thereby exposing the fins 112 and the hard mask cap 114. Any material removal process, such as, for example, ashing may be used to remove the second OPL 132 from the structure 100.
Referring now to
The metal gate 142 may include a gate dielectric material, a work function metal, and a metal gate. The gate dielectric material may include oxides, nitrides, oxynitrides, silicates (e.g., metal silicates), aluminates, titanates, nitrides, high-k dielectrics like hafnium oxide, or any combination thereof. The work function metal include p-type work function metal materials and n-type work function metal materials. P-type work function materials include compositions such as ruthenium, palladium, platinum, cobalt, nickel, titanium nitride, titanium carbide, titanium aluminum carbide, and conductive metal oxides, or any combination thereof. N-type metal materials include compositions such as hafnium, zirconium, titanium, tantalum, aluminum, metal carbides (e.g., hafnium carbide, zirconium carbide, titanium carbide, and aluminum carbide), aluminides, titanium nitride, titanium carbide, titanium aluminum carbide, or any combination thereof. The metal gate may be made of conductive metal such as, for example, aluminum (Al), platinum (Pt), gold (Au), tungsten (W), titanium (Ti), or any combination thereof. The metal gate 142 may be deposited by a suitable deposition process, for example, atomic layer deposition, chemical vapor deposition, plasma-enhanced chemical vapor deposition, physical vapor deposition, plating, thermal or e-beam evaporation, and sputtering.
After the formation of the metal gate 142, the ILD 148 is deposited on the structure 100. The ILD 148 may be formed from, for example, a low-k dielectric material (with k<4.0), including but not limited to, silicon oxide, spin-on-glass, a flowable oxide, a high density plasma oxide, borophosphosilicate glass (BPSG), or any combination thereof. The ILD 148 is deposited by a deposition process, including, but not limited to chemical vapor deposition, physical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition, evaporation, chemical solution deposition, or like processes. To form the top source drains 146, the hard mask caps 114 are first removed. The hard mask caps 114 may be removed by utilizing any material removal process, such as, for example, chemical mechanical polishing followed by selective SiN removal. Once the hard mask caps 114 are removed, exposing the top surfaces of the third semiconductor layer 108, the top source drains 146 are epitaxially grown from the exposed top surfaces of the third semiconductor layer 108. The top source drains 146 may be doped with the same type of dopants as the bottom source drains 116.
Referring now to
In addition to the bottom source drain contacts 150, the structure 100 undergoes further manufacturing processes to form the top source drain contacts 152 and the gate contact 154. The top source drain contacts 152 and the gate contacts 154 are formed in substantially the same manner as the bottom source drain contacts 150. The top source drain contacts 152 extend through the ILD 148 to the top source drains 146. The gate contacts 154 extend through the ILD 148 to the metal gate 142.
The resultant structure 100, as illustrated in
Another embodiment by which to fabricate a VTFET with a buried power rail directly below it is described in detail below by referring to the accompanying
Referring now to
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After the first and the second semiconductor layers 104, 106 are removed, the resultant opening 158 is then filled with an oxide material, such as, for example, silicon oxide to create the STI 136. The STI 136 separates the two fins 112 and the two bottom source drains 116 such that electrical current applied to one fin has no effect on the second fin. Typically, the STI 136 extends through a portion of the substrate 102 to a depth that allows for the two fins to be electrically separated.
Referring now to
The resultant structure 200, as illustrated in
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As is illustrated in
The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiment, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
