Patent Application
20190341230
This disclosure relates to semiconductor manufacturing. There are many process steps executed to fabricate integrated circuits. Various patterning, deposition, and cleaning steps are executed to fabricate and create packages for integrated circuits. Such steps can include dry cleaning operations in which plasma is used to clean or remove materials from a substrate. One constant challenge with fabrication of semiconductors is preventing contamination of devices and substrates.
Techniques herein provide particle reduction systems and methods. This includes particle reduction in plasma cleaning systems such as an inductively coupled plasma (ICP) sputter clean etch chamber of a physical vapor deposition (PVD) tool. During etch processing, various metal and polymer species are deposited on a ceramic liner. In high volume production, such liners increased in temperature as a result of radio frequency (RF) power coupling and plasma processes. Such heating of the ceramic liner is problematic because particle spallation occurs due to thermal cycling of the liner.
An integrated liner with Faraday shield herein can be held at a constant temperature, thereby preventing such particle spallation. Conventional systems have used Faraday shields and ceramic liners in ICP etch chambers, with the Faraday shields used to modify RF fields in the etch chamber. Also, Faraday shields and ceramic liners are purposefully separated, some with cooling for the Faraday shield.
In contrast, techniques herein include a liner with integrated Faraday shield. The Faraday shield is used to heat the ceramic liner to prevent particle production in a corresponding etch chamber. Such heating can include pre-heating prior to substrate processing.
One embodiment includes a plasma processing system for processing a semiconductor substrate. This system includes a plasma processing chamber having a substrate support member configured for receiving a semiconductor substrate within the plasma processing chamber. A process gas delivery system is configured to deliver process gas to the plasma processing chamber. A power source is configured to energize process gas within the plasma processing chamber to create plasma. A component is positioned between the power source and the substrate support member, the component comprising a ceramic liner and a Faraday shield in contact with a surface of the ceramic liner. The plasma processing gas flow and pumping may be configured to maintain a pressure less than atmospheric pressure.
Of course, the order of discussion of the different steps as described herein has been presented for clarity's sake. In general, these steps can be performed in any suitable order. Additionally, although each of the different features, techniques, configurations, etc. herein may be discussed in different places of this disclosure, it is intended that each of the concepts can be executed independently of each other or in combination with each other. Accordingly, the present invention can be embodied and viewed in many different ways.
Note that this summary section does not specify every embodiment and/or incrementally novel aspect of the present disclosure or claimed invention. Instead, this summary provides preliminary discussion of different embodiments and corresponding points of novelty over conventional techniques. For additional details and/or possible perspectives of the invention and embodiments, the reader is directed to the Detailed Description section and corresponding figures of the present disclosure as further discussed below, and the accompanying claims.
Systems and methods herein include a component comprising an integrated liner with a Faraday shield. With such integration, a ceramic liner can be held at a constant temperature to prevent particle spallation. The Faraday shield is used to heat the ceramic liner to prevent particle production in a corresponding etch chamber. Such heating can include pre-heating prior to substrate processing to avoid thermal cycling of the liner in the presence of a substrate.
The liner with integrated Faraday shield herein can increase liner lifetime before needing to be cleaned because of improved adhesion of sputtered material on the liner. Etch uniformity can be improved by a suitable selection of Faraday shielding pattern.
In one example method, there are various process steps available to be used in various sequences for particle reduction with liners herein. The shield can be cleaned prior to use and/or at intervals as part of routine maintenance. Bead blasting can be used for such cleaning. The liner can be installed or positioned with a Faraday pattern facing a ceramic window of an etch chamber. Thus, a ceramic surface of the liner is positioned to face a substrate when positioned in the etch chamber, while an opposing side having an integrated Faraday shield faces a ceramic window of a corresponding etch chamber. The etch chamber can be pumped to vacuum or to a particular operating pressure.
An ICP or other power source is turned on to a predetermined power level (such as a power level used for wafer processing or higher) to heat the ceramic liner via eddy currents in the Faraday shield. Different shielding patterns can result in different heating. The liner can be heated until reaching an equilibrium temperature or operating temperature during etch operations. The liner or system can include a temperature sensor to measure and indicate when the liner has reached a desired temperature. ICP power can be turned off for a period of time, such as to place a given substrate in the plasma etch chamber. A given etch process can then be executed with the liner already at an equilibrium temperature for that etch process. A temperature of the liner can be measured continuously or periodically, such as with a fiber optic temperature sensor. ICP power can be turned on at various times to maintain the liner at a particular temperature or temperature range.
With such techniques, metal and polymer that is sputtered onto a liner during etch processing can be deposited over a range of liner temperatures. Films from such metal and polymer sputtering typically have a higher coefficient of thermal expansion (CTE) than the liner. For example aluminum has a CTE of 21-24×10{circumflex over ( )}-6 (m/m-K) compared to a quartz liner CTE of 8-14×10{circumflex over ( )}6 (m/m-K). As the liner heats up during processing, the CTE mismatch can contribute to spallation of the film, which causes particles to collect on a wafer. If the liner is already at equilibrium temperature prior to etch, however, then the sputtered film will not experience the thermal ramp, and will remain better adhered to the liner. A wafer can be periodically used to sputter etch onto the liner to increase adhesion through a pasting process.
The invention will be described with reference to the accompanying drawings, in which:
Now referring to the drawings,
Components in accordance with embodiments of the present invention include, for example, a Faraday shield adhered to or integrated with a ceramic liner. This Faraday shield can be patterned from stainless steel or other metal.
Such an integration enables beneficial thermal coupling for faster heating of the liner. By way of a non-limiting example, using 800 W of ICP power applied to the system, approximately 200 W was absorbed in the liner. The liner herein reaches the equilibrium temperature of 80 degrees C. in nine minutes instead of 35 minutes. Thus, by using high power ICP, the integrated liner can quickly reach equilibrium temperature.
Other embodiments include a method of processing a substrate. An inductively-coupled plasma processing system configured to receive a substrate in a plasma processing chamber is provided. Prior to receiving the substrate within the plasma processing chamber, an inductively-coupled power supply is activated that heats a Faraday shield in contact with a ceramic liner which heats the ceramic liner. The ceramic liner is positioned within the plasma processing chamber. Subsequent to the ceramic liner reaching a predetermined temperature the substrate is introduced into the plasma processing chamber. This predetermined temperature can be an equilibrium temperature of corresponding plasma processing treatment for the substrate. The substrate is then processed using plasma energized from the plasma processing system. Methods can include monitoring a temperature of the ceramic liner and heating the ceramic liner via the Faraday shield when the temperature of the ceramic liner is less than a predetermined threshold temperature.
In the preceding description, specific details have been set forth, such as a particular geometry of a processing system and descriptions of various components and processes used therein. It should be understood, however, that techniques herein may be practiced in other embodiments that depart from these specific details, and that such details are for purposes of explanation and not limitation. Embodiments disclosed herein have been described with reference to the accompanying drawings. Similarly, for purposes of explanation, specific numbers, materials, and configurations have been set forth in order to provide a thorough understanding. Nevertheless, embodiments may be practiced without such specific details. Components having substantially the same functional constructions are denoted by like reference characters, and thus any redundant descriptions may be omitted.
Various techniques have been described as multiple discrete operations to assist in understanding the various embodiments. The order of description should not be construed as to imply that these operations are necessarily order dependent. Indeed, these operations need not be performed in the order of presentation. Operations described may be performed in a different order than the described embodiment. Various additional operations may be performed and/or described operations may be omitted in additional embodiments.
“Substrate” or “target substrate” as used herein generically refers to an object being processed in accordance with the invention. The substrate may include any material portion or structure of a device, particularly a semiconductor or other electronics device, and may, for example, be a base substrate structure, such as a semiconductor wafer, reticle, or a layer on or overlying a base substrate structure such as a thin film. Thus, substrate is not limited to any particular base structure, underlying layer or overlying layer, patterned or un-patterned, but rather, is contemplated to include any such layer or base structure, and any combination of layers and/or base structures. The description may reference particular types of substrates, but this is for illustrative purposes only.
Those skilled in the art will also understand that there can be many variations made to the operations of the techniques explained above while still achieving the same objectives of the invention. Such variations are intended to be covered by the scope of this disclosure. As such, the foregoing descriptions of embodiments of the invention are not intended to be limiting. Rather, any limitations to embodiments of the invention are presented in the following claims.
This application claims priority from U.S. Provisional Application Ser. No. 62/666,361, filed May 3, 2018, the entire disclosure of which is hereby incorporated by reference.
| Number | Date | Country | |
|---|---|---|---|
| 62666361 | May 2018 | US |
