Patent Application
20240243067
Embodiments of the present application relate to a technical field of a display panel, and more particularly, to a chip-on-film structure, a display device, and a spliced display device.
Currently, in a display device, a driving chip and a display panel are bonded to a same side of a chip-on-film (COF) structure, and the driving chip is disposed between the display panel and the chip-on-film structure. Due to a higher height of the driving chip, a height of a metal welding layer bonded to the display panel and the chip-on-film structure is high, resulted in that the bonding difficulty is high, the reliability problem easily occurs, and the bonding yield is affected. In addition, the heat is generated during operation of the driving chip, which causes the temperature of an area of the display panel close to the driving chip to rise, and further causes the light-emitting efficiency and the brightness of the light-emitting devices in the display panel to decrease, and causes uneven display of the display panel.
Embodiments of the present application provide a chip-on-film structure including: a base, where the base includes a first surface and a second surface oppositely disposed; a first circuit covering the first surface, where the first circuit includes a driving chip bonding area; a display panel bonding end disposed on the second surface; and a first conductive portion connected to the first circuit and the display panel bonding end respectively.
In some embodiments, the first conductive portion extends through the base.
In some embodiments, the base further includes a third surface and a fourth surface, the third surface is connected to the first surface and the second surface, the fourth surface is connected to the first surface and the second surface; and the first conductive portion covers the third surface.
In some embodiments, the display panel bonding end and the first conductive portion are overlapped in a target direction, and the target direction is parallel to the second surface.
In some embodiments, the display panel bonding end is spaced apart from the first conductive portion in a target direction, and the target direction is parallel to the second surface; where the chip-on-film structure further includes a second circuit, the second circuit at least partially covers the second surface, the display panel bonding end is disposed on a side of the second circuit away from the base, and the first conductive portion is connected to the display panel bonding end through the second circuit.
In some embodiments, the chip-on-film structure further includes a heat insulating layer; and the heat insulating layer is disposed on a side of the second circuit away from the base.
In some embodiments, the chip-on-film structure further includes a first protective layer; and the first protective layer is disposed on a side of the first circuit away from the base.
In some embodiments, the chip-on-film structure further includes a second protective layer; and the second protective layer is positioned between the second circuit and the heat insulating layer.
In some embodiments, the first circuit further includes a circuit board bonding area; and the circuit board bonding area and the display panel bonding end are respectively disposed close to opposite ends of the base.
In some embodiments, the chip-on-film structure further includes a driving chip and a circuit board, the driving chip is disposed in the driving chip bonding area and is connected to the first circuit, and the circuit board is disposed in the circuit board bonding area and is connected to the first circuit.
Embodiment of the present application further provide a display device including the chip-on-film structure described above; and a display panel, where the display panel is connected to the display panel bonding end in the chip-on-film structure.
In some embodiments, the display panel is a top light-emitting display panel, and the display panel includes a second conductive portion; where a top of the light-emitting display panel has a second bonding end, the chip-on-film structure is disposed at bottom of the top light-emitting display panel, and the display panel bonding end faces the display panel and is connected to the second bonding end through the second conductive portion; and where the second conductive portion extends through the display panel or covers a side surface of the display panel.
In some embodiments, the display panel is a bottom light-emitting display panel; where a top of the bottom light-emitting display panel has a first bonding end, the chip-on-film structure is disposed on top of the display panel, and the display panel bonding end faces the display panel and is connected to the first bonding end.
In some embodiments, the display panel includes: a driving backplane, where the driving backplane includes a plurality of bonding electrode pairs, each of the plurality of bonding electrode pairs includes a first bonding electrode and a second bonding electrode insulated from each other; and light-emitting devices, where each of the light-emitting devices is bonded to the driving backplane through a corresponding pair of the plurality of bonding electrode pairs, the light-emitting device includes a first electrode and a second electrode insulated from each other, the first electrode is electrically connected to the first bonding electrode, and the second electrode is electrically connected to the second bonding electrode; where a light-emitting surface of the light-emitting device faces the driving backplane, the light-emitting device further includes an epitaxial plate, and the first electrode and the second electrode are both disposed on a side of the epitaxial plate away from the driving backplane.
In some embodiments, the display panel further includes a first connection line connected between the first electrode and the first bonding electrode, and a second connection line connected between the second electrode and the second bonding electrode.
In some embodiments, the light-emitting device further includes an insulating protective layer covering the epitaxial plate and exposing the first electrode and the second electrode, and the first connection line and the second connection line both are provided on a side of the insulating protective layer away from the epitaxial plate.
In some embodiments, the epitaxial plate includes an N-type semiconductor layer, a P-type semiconductor layer, and a quantum well layer disposed between the N-type semiconductor layer and the P-type semiconductor layer; the P-type semiconductor layer is disposed on a side of the N-type semiconductor layer away from the driving backplane; the first electrode is electrically connected to the N-type semiconductor layer; and the second electrode is electrically connected to the P-type semiconductor layer.
In some embodiments, the N-type semiconductor layer includes a projection beyond a boundary of the quantum well layer, the first electrode is provided on a side of the projection away from the driving backplane, and the second electrode is provided on a side of the P-type semiconductor layer away from the quantum well layer.
In some embodiments, the driving backplane further includes a substrate, and a transistor disposed on the substrate; the first bonding electrode and the bonding second electrode both are disposed on a side of the transistor away from the substrate; and the first bonding electrode is electrically connected to the transistor. Embodiments of the present application further provide a spliced display device including a plurality of the display devices.
The first circuit covers the first surface of the base, the first circuit includes a driving chip bonding area, the display panel bonding end is provided on the second surface of the base, the first surface is provided opposite to the second surface, and the first circuit is connected to the display panel bonding end through the first conductive portion, so as to ensure that the driving chip and the display panel are bonded to both opposite sides of the base respectively, to avoid that the display panel bonding end is too high, and to reduce the bonding difficulty of the display panel, improve the bonding efficiency and reliability, facilitate heat dissipation of the driving chip, and improve the uneven display of the display panel due to the heating from the driving chip.
In addition, in the bottom light-emitting display panel, the light-emitting surface of the light-emitting device faces the driving backplane, and the first electrode and the second electrode of the light-emitting device are both disposed on the side of the epitaxial plate away from the driving backplane. In this way, the first electrode and the second electrode do not block the light emitted from the light-emitting device, so that the light output utilization rate of the bottom light-emitting display panel can be improved, and the situation that the light output utilization rate is low due to the fact that the bottom electrode of the flip chip in the bottom light-emitting display panel blocks out the light from the chip is improved.
In order that the embodiments or the technical solutions in the related art may be described more clearly, reference will now be made to the accompanying drawings which are to be used in the description of the embodiment. It should be understood that the accompanying drawings in the description below are merely some of the embodiments of the present application, and other drawings may be made to those skilled in the art without involving any inventive effort.
The specific structural and functional details disclosed herein are representative only and are for the purpose of describing exemplary embodiments of the present application. The present application may, however, be embodied in many alternative forms and should not be construed as limited only to the embodiments set forth herein.
In the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms “center”, “lateral”, “on”, “below”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, “in”, “out”, and the like, is based on the orientation or positional relationship shown in the drawings, merely to facilitate the description of the present application and to simplify the description, and not to indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore is not to be construed as limiting the present application. Furthermore, the terms “first” and “second” are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying the number of indicated technical features. Thus, the features defined by “first” and “second” are indicated or implied to include one or more. In the description of this application, unless otherwise stated, “a plurality of” means two or more. Additionally, the term “comprise” and any variations thereof is intended to cover a non-exclusive inclusion.
In the description of the present application, it should be noted that, unless expressly stated and defined otherwise, the terms “mount”, “link”, “connect” are to be understood in a broad sense, for example, as a fixed connection, as a detachable connection, or as an integrated connection; as a mechanical connection or an electrical connection; as a directly connection or an indirectly connection by means of an intermediate medium; and as an internal communication of the two elements. The specific meaning of the above terms in the present application can be understood in a specific way to those of ordinary skill in the art.
The terms used herein is for the purpose of describing specific embodiments only and is not intended to limit the exemplary embodiments. As used herein, the singular forms “a”, and “an” are also intended to include the plural unless the context clearly dictates otherwise. It should be understood that the terms used herein “comprise” and/or “include” specifies the presence of stated features, integers, steps, operations, units, and/or components, without the presence or addition of one or more other features, integers, steps, operations, units, components, and/or combinations thereof.
Referring to
As shown in
The first circuit 2 covers the first surface 11 of the base 1, and the first circuit 2 may cover the first surface 11 of the base 1 in whole or in part. The material of the first circuit 2 is a conductive metal such as tungsten, cobalt, copper, aluminum, or the like. The first circuit 2 includes a driving chip bonding area 21 and a circuit board bonding area 22, and the chip-on-film structure may further include a driving chip 8 and a circuit board 9. The driving chip 8 is disposed in the driving chip bonding area 21, and is connected to the first circuit 2 to bond with the first circuit 2. The circuit board 9 is disposed in the circuit board bonding area 22, and is connected to the first circuit 2 to bond with the first circuit 2. As shown in
The display panel bonding end 3 is disposed on the second surface 12 of the base 1 for bonding with the display panel 20 (as will be described below with reference to
The first conductive portion 4 is connected to the first circuit 2 and the display panel bonding end 3, that is, an end of the first conductive portion 4 is connected to the first circuit 2, and another end of the first conductive portion 4 is connected to the display panel bonding end 3. After bonding the driving chip 8 and the display panel 20 (see
In this embodiment, the driving chip bonding area 21 is disposed on the first surface 11 of the base 1, and the display panel bonding end 3 is disposed on the second surface 12 of the base 1, that is, the driving chip bonding area 21 and the display panel bonding end 3 are disposed on opposite sides of the base 1. Thus, after bonding the driving chip and the display panel, the driving chip and the display panel are disposed on opposite sides of the base 1. In this way, the height of the display panel bonding end 3 does not need to set high, for example, it can be less than the height of the driving chip, thereby reducing the bonding difficulty of the display panel and improving the bonding yield and reliability. In addition, the driving chip and the display panel are disposed on opposite sides of the base 1 to facilitate heat dissipation of the driving chip, and the heating from the driving chip does not affect the display panel, thereby improving the display evenness of the display panel.
In addition, as shown in
In an embodiment, as shown in
In another embodiment, as shown in
In another embodiment, as shown in
In another embodiment, as shown in
In another embodiment, as shown in
As shown in
As shown in
According to the chip-on-film structure provided in the embodiments of the present application, the first circuit is covered on the first surface of the base, the first circuit includes a driving chip bonding area, the display panel bonding end is provided on the second surface of the base, the first surface is disposed opposite to the second surface, and the first circuit is connected to the display panel bonding end through the first conductive portion, so that the driving chip and the display panel are bonded to opposite sides of the base, to avoid that the display panel bonding end is too high, to reduce the bonding difficulty of the display panel, improve the bonding efficiency and reliability, facilitate heat dissipation of the driving chip, and improve the display evenness of the display panel.
Referring to
In a case that the display panel 20 is a bottom light-emitting display panel, as shown in
At this time, the display panel 20 includes a driving backplane 27, light-emitting devices 28 disposed on the driving backplane 27, and an encapsulation layer 23 covering the light-emitting devices 28 and the driving backplane 27. The encapsulation layer 23 serves to reflect the lights emitted by the light-emitting devices 28 to the bottom of the display panel 20 (i.e., a side of the driving backplane 27 away from the encapsulation layer 23) in addition to the encapsulation. The first bonding end 24 may be disposed on the driving backplane 27, and the encapsulation layer 23 does not cover the first bonding end 24.
In a case that the display panel 20 is a top light-emitting display panel, as shown in
At this time, the display panel 20 may include a driving backplane 27, light-emitting devices 28 disposed on the driving backplane 27, and an encapsulation layer 23 covering the light-emitting devices 28 and the driving backplane 27. The encapsulation layer 23 is used to encapsulate the light-emitting devices 28.
The second bonding end 25 may be disposed on the driving backplane 27, and the encapsulation layer 23 may not cover the second bonding end 25. In other embodiments, the encapsulation layer 23 may cover the second bonding end 25.
According to the display device provided in the embodiment of the present application, the driving chip and the display panel can be bonded to opposite sides of the base, so that the height of the display panel bonding end is prevented from being too high, the bonding difficulty of the display panel is reduced, the bonding yield and the reliability are improved, the heat dissipation of the driving chip is facilitated, and the uneven display of the display panel caused by the heating of the driving chip is improved.
Embodiments of the present application provides a specific structure of the bottom light-emitting display panel as shown in
Referring to
The light-emitting surface of the light-emitting device 28 faces the driving backplane 27, so that the light emitted from the light-emitting device 28 can directly pass through the driving backplane 27 to realize the bottom light emission of the display panel 20 while improving the utilization rate of the light emitted from the light-emitting device 28. Since the first electrode 221 and the second electrode 222 are provided on the side of the epitaxial plate 223 away from the driving backplane 27, that is, on the non-light-emitting surface of the light-emitting device 28, it is possible to prevent the first electrode 221 and the second electrode 222 from blocking the light emitted from the light-emitting device 28 to improve the utilization rate of the light emitted from the light-emitting device 28.
With continued reference to
The substrate 40 may be a rigid base or a flexible base. In a case that the substrate 40 is a rigid base, the rigid base may be a rigid transparent base such as a glass base, a quartz base, or a silicon wafer. In a case that the substrate 40 is a flexible base, the flexible base may be a flexible transparent base such as a Polyimide (PI) film or an ultra-thin glass film.
The driving backplane 27 further includes a light-shielding layer 60 disposed on the substrate 40 and corresponding to the transistor 50, the light-shielding layer 60 is used for shielding the transistor 50 from the light. The transistor 50 includes an active layer 51, a gate electrode 52, a source electrode 54, and a drain electrode 53, and the first bonding electrode 271 is electrically connected to the drain electrode 53. The material of the light-shielding layer 60 includes a light-shielding material such as metal. The material of the active layer 51 includes a semiconductor material such as polysilicon or metal oxide. The materials of the gate electrode 52, the source electrode 54, and the drain electrode 53 include metals such as copper, aluminum, titanium, and molybdenum.
The driving backplane 27 also includes a plurality of insulating layers, such as a buffer layer 41, a gate insulating layer 42, an interlayer insulating layer 43, a passivation layer 44, and a planarization layer 45. Here, the buffer layer 41 covers the light-shielding layer 60 and the substrate 40, and the buffer layer 41 can prevent undesirable impurities or contaminants (such as moisture, oxygen, and the like) from diffusing from the substrate 40 to devices that may be damaged by these impurities or contaminants, while providing a flat top surface.
The active layer 51 is provided on the buffer layer 41, the gate insulating layer 42 is provided on the active layer 51, and the gate electrode 52 is provided on the gate insulating layer 42. The active layer 51 includes a channel, and source and drain areas disposed on two sides of the channel respectively, and the gate electrode 52 and the gate insulating layer 42 are provided corresponding to the channel. The interlayer insulating layer 43 covers the gate electrode 52 and the buffer layer 41. The source electrode 54 and the drain electrode 53 are disposed on the interlayer insulating layer 43. The source electrode 54 is electrically connected to the source area of the active layer 51, and the drain electrode 53 is electrically connected to the drain area of the active layer 51. The passivation layer 44 covers the source electrode 54, the drain electrode 53, and the interlayer insulating layer 43, and the planarization layer 45 covers the passivation layer 44. The first bonding electrode 271 and the second bonding electrode 272 are provided on the planarization layer 45, and the first bonding electrode 271 is electrically connected to the drain electrode 53 through vias through the planarization layer 45 and the passivation layer 44.
The buffer layer 41, the gate insulating layer 42, the interlayer insulating layer 43, and the passivation layer 44 may be a stack of inorganic materials such as silicon nitride (SiNx), silicon oxide (SiOx), or silicon nitride and silicon oxide. The material of the planarization layer 45 includes an organic material such as a photoresist.
The light-emitting devices 28 are provided on the side of the planarization layer 45 away from the substrate 40. The light-emitting device 28 includes a Micro LED chip, a Mini LED chip, an LED chip, or the like. The transistor 50 is used to control the turn-on and turn-off of a corresponding light-emitting device 28. Specifically, the first electrode 221 of the light-emitting device 28 is bonded to the driving backplane 27 through the first bonding electrode 271, and is electrically connected to the transistor 50 through the first bonding electrode 271; and the second electrode 222 of the light-emitting device 28 is bonded to the driving backplane 27 through the second bonding electrode 272. Alternatively, the first electrode 221 is a cathode, and the second electrode 222 is an anode.
The display panel 20 further includes a first connection line 31 connected between the first electrode 221 and the first bonding electrode 271, and a second connection line 32 connected between the second electrode 222 and the second bonding electrode 272. The material of the first connection line 31, the second connection line 32, the first bonding electrode 271, the second bonding electrode 272, the first electrode 221, and the second electrode 222 may be transparent conductive material such as indium tin oxide (ITO).
Further, the light-emitting device 28 further includes an insulating protective layer 224 covering the epitaxial plate 223 and exposing the first electrode 221 and the second electrode 222. The first connection line 31 and the second connection line 32 are provided on the side of the insulating protective layer 224 away from the epitaxial plate 223. That is, the insulating protective layer 224 covers all areas on the epitaxial plate 223 except the first electrode 221 and the second electrode 222, to avoid short circuits between the first connection line 31 and the epitaxial plate 223, and between the second connection line 32 and the epitaxial plate 223. The insulating protective layer 224 may be a stack of inorganic materials such as silicon nitride (SiNx), silicon oxide (SiOx), or silicon nitride and silicon oxide.
Referring to
To further improve the utilization of the emitted light of the light-emitting device 28, the orthographic projection of the transistor 50 on the substrate 40 is spaced from the orthographic projection of the epitaxial plate 223 on the substrate 40. In the present application, the term “spaced from” defines that the orthographic projections of the two structures on the same surface are not overlapped. For example, in the present embodiment, “the orthographic projection of the transistor 50 on the substrate 40 is spaced from the orthographic projection of the epitaxial plate 223 on the substrate 40” means that the orthographic projection of the transistor 50 on the substrate 40 is not overlapped with the orthographic projection of the epitaxial plate 223 on the substrate 40. As such, the transistor 50 is prevented from blocking the light emitted from the light-emitting device 28.
Further, the display panel 20 further includes an encapsulation layer 23 covering the light-emitting devices 28 and the driving backplane 27. The encapsulation layer 23 serves to protect the light-emitting devices 28, and prevent water and oxygen from intruding into the light-emitting devices 28. Alternatively, the material of the encapsulation layer 23 is selected to have reflective properties to further improve the utilization of the light emitted from the light-emitting devices 28.
The present embodiment adopts the bottom light-emitting display panel, the light-emitting surface of the light-emitting device faces toward the driving backplane, and the first electrode and the second electrode are both disposed on the side of the epitaxial plate away from the driving backplane. Therefore, the first electrode and the second electrode do not block the light emitted from the light-emitting device. In this way, the light output utilization rate of the bottom light-emitting display panel can be improved, and the situation that the light output utilization rate is low due to the fact that the bottom electrode of the flip chip in the bottom light-emitting display panel blocks out the light from the chip is improved.
Embodiments of the present application further provides a spliced display device. As shown in
As above, although the present application has been disclosed as the above-described embodiments, the above-described embodiments are not intended to limit the present application. Those of ordinary skill in the art may make various changes and modifications without departing from the spirit and scope of the present application, and therefore the scope of protection of the present application is as defined in the claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202111484204.3 | Dec 2021 | CN | national |
| 202323389960.5 | Dec 2023 | CN | national |
This application is a continuation-in-part of International Application No. PCT/CN2021/139166, filed on Dec. 17, 2021, which claims priority to Chinese Patent Application No. 202111484204.3, filed on Dec. 7, 2021, and Chinese Patent Application No. 202323389960.5, filed on Dec. 12, 2023. All of the aforementioned patent applications are hereby incorporated by reference in their entireties.
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/CN2021/139166 | Dec 2021 | WO |
| Child | 18429625 | US |
