CHIP STRUCTURE AND CHIP MANUFACTURING PROCESS

Abstract

A chip manufacturing process is disclosed. A wafer having a passivation layer and at least one bonding pad is provided. The surface of the bonding pad is exposed to a first opening of the passivation layer. A first metal layer is formed on the bonding pad exposed by the first opening. A photoresist having a second opening and a photoresist block disposed in the second opening is formed on the first metal layer. The first metal layer corresponding to the second opening has a first surface, and the first metal layer corresponding to the photoresist block has a second surface. A second metal layer is formed on the first surface, and the photoresist block is removed to expose the second surface. A UBM layer is formed on the second metal layer and the second surface of the first metal layer. Finally, a conductive bump is formed on the UBM layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic sectional view of a conventional chip structure.

FIGS. 2A to FIG. 2G are flow charts of the chip manufacturing process according to an embodiment of the present invention.

FIG. 3 is a schematic view of the chip structure according to another embodiment of the present invention.

Claims

1. A chip structure, comprising: a chip, having an active surface;at least one bonding pad, disposed on the active surface;a passivation layer, covering the active surface and having an opening exposing an upper surface of the bonding pad;a metal layer, formed on the bonding pad in the opening;a UBM layer, disposed on the metal layer and not covering the passivation layer; anda conductive bump, formed on the UBM layer.

2. The chip structure as claimed in claim 1, wherein the metal layer comprises a first metal layer and a second metal layer, the first metal layer is disposed on the bonding pad, and the second metal layer is an annular structure and is disposed on a part of the surface of the first metal layer.

3. The chip structure as claimed in claim 2, wherein the first metal layer and the bonding pad are of the same material.

4. The chip structure as claimed in claim 2, wherein a material of the first metal layer and the second metal layer comprises Al or Ti.

5. The chip structure as claimed in claim 1, wherein a material of the UBM layer is one selected from a group consisting of Ni, Cu, Ti, and an alloy thereof.

6. The chip structure as claimed in claim 1, wherein a material of the conductive bump comprises Sn or Au.

7. A chip structure, comprising: a chip, having an active surface;at least one bonding pad, disposed on the active surface;a passivation layer, covering the active surface and having an opening exposing an upper surface of the bonding pad;an annular metal layer, formed on a part of a surface of the bonding pad in the opening;a UBM layer, disposed on the annular metal layer and not covering the passivation layer; anda conductive bump, formed on the UBM layer.

8. The chip structure as claimed in claim 7, wherein a material of the annular metal layer comprises Al or Ti.

9. The chip structure as claimed in claim 7, wherein a material of the UBM layer is one selected from a group consisting of Ni, Cu, Ti, and an alloy thereof.

10. The chip structure as claimed in claim 7, wherein a material of the conductive bump comprises Sn or Au.