Patent Application
20240429175
The disclosure relates to a component carrier and to a method of manufacturing a component carrier.
In the context of growing product functionalities of component carriers equipped with one or more electronic components and increasing miniaturization of such components as well as a rising number of components to be mounted on or embedded in the component carriers such as printed circuit boards, increasingly more powerful array-like components or packages having several components are being employed, which have a plurality of contacts or connections, with ever smaller spacing between these contacts. Removal of heat generated by such components and the component carrier itself during operation becomes an increasing issue. At the same time, component carriers shall be mechanically robust and electrically reliable so as to be operable even under harsh conditions.
Electrically connecting components assigned to a component carrier is however still a challenge.
There may be a need for a component carrier with assigned components being manufacturable simply and with high reliability.
According to an exemplary embodiment of the disclosure, a component carrier is provided, wherein the component carrier comprises a stack comprising at least one electrically insulating layer structure and a plurality of electrically conductive layer structures at least part of which having a first density of trace structures and a second density of connection structures, a further stack comprising at least one further electrically insulating layer structure and a plurality of further electrically conductive layer structures at least part of which having a third density of further trace structures and a fourth density of further connection structures, at least one first component applied to the stack and at least one second component embedded in the further stack wherein the connection structures are respectively connected to the further connection structures, wherein the first density of trace structures is lower than the third density of further trace structures, wherein the stack and the further stack are connected with each other by the connection structures of the stack and by the further connection structures of the further stack, and wherein the at least one first component is connected to the at least one second component.
According to another exemplary embodiment of the disclosure, a component carrier is provided, wherein the component carrier comprises a stack comprising at least one electrically insulating layer structure and a plurality of electrically conductive layer structures at least part of which comprising trace structures and connection structures, a further stack comprising at least one further electrically insulating layer structure and a plurality of further electrically conductive layer structures at least part of which comprising further trace structures and further connection structures, wherein the connection structures are respectively connected to the further connection structures, wherein the stack and the further stack are connected with each other by the connection structures of the stack and by the further connection structures of the further stack, and wherein the stack and/or the further stack comprises a bridge connected to at least two components.
According to another exemplary embodiment of the disclosure, a method of manufacturing a component carrier is provided, wherein the method comprises providing a stack comprising at least one electrically insulating layer structure and a plurality of electrically conductive layer structures at least part of which having a first density of trace structures and a second density of connection structures, providing a further stack comprising at least one further electrically insulating layer structure and a plurality of further electrically conductive layer structures having a third density of further trace structures and a fourth density of further connection structures, applying at least one first component to the stack, and embedding at least one second component in the further stack, providing the stack and the further stack so that the second density of connection structures and the fourth density of further connection structures differ from each other by not more than +/−20%, providing the stack and the further stack so that the first density of trace structures is lower than the third density of further trace structures, connecting the stack and the further stack with each other by the connection structures of the stack and by the further connection structures of the further stack, and connecting the at least one first component to the at least one second component.
According to another exemplary embodiment of the disclosure, a method of manufacturing a component carrier is provided, wherein the method comprises providing a stack comprising at least one electrically insulating layer structure and a plurality of electrically conductive layer structures at least part of which comprising trace structures and connection structures, providing a further stack comprising at least one further electrically insulating layer structure and a plurality of further electrically conductive layer structures at least part of which comprising further trace structures and further connection structures, connecting the connection structures respectively to the further connection structures, connecting the stack and the further stack with each other by the connection structures of the stack and by the further connection structures of the further stack, providing a bridge configured to connect at least two components in the stack and/or the further stack.
According to still another exemplary embodiment of the disclosure, a component carrier is provided which comprises a stack comprising at least one electrically insulating layer structure and a plurality of electrically conductive layer structures at least part of which having a first density of trace structures and a second density of connection structures, a further stack comprising at least one further electrically insulating layer structure and a plurality of further electrically conductive layer structures at least part of which having a third density of further trace structures and a fourth density of further connection structures, and optionally at least one first component applied to the stack, wherein the connection structures are respectively connected to the further connection structures, wherein the first density of trace structures is lower than the third density of further trace structures, wherein the stack and the further stack are connected with each other by the connection structures of the stack and by the further connection structures of the further stack, and wherein the at least one electrically insulating layer structure comprises at least two sub-structures made of different dielectric materials.
In the context of the present application, the term “component carrier” may particularly denote any support structure which can accommodate one or more components thereon and/or therein for providing mechanical support and/or electrical connectivity. In other words, a component carrier may be configured as a mechanical and/or electronic carrier for components. A component carrier may comprise a laminated layer body, such as a laminated layer stack. In particular, a component carrier may be one of a printed circuit board, an organic interposer, and an IC (integrated circuit) substrate. A component carrier may also be a hybrid board combining different ones of the above-mentioned types of component carriers.
In the context of the present application, the term “stack” may particularly denote a flat or planar sheet-like body. For instance, the stack may be a layer stack, in particular a laminated layer stack or a laminate. Such a laminate may be formed by connecting a plurality of layer structures by the application of mechanical pressure and/or heat.
In the context of the present application, the term “layer structure” may particularly denote a continuous layer, a patterned layer or a plurality of non-consecutive islands within a common plane.
In the context of the present application, the term “component” may particularly denote a device, for instance fulfilling an electronic and/or a thermal task. For instance, the component may be an electronic component. Such an electronic component may be an active component such as a semiconductor chip comprising a semiconductor material, in particular as a primary or basic material. Said semiconductor chip may for example be an active semiconductor chip or a passive semiconductor chip (such as a bridge chip). The semiconductor material may for instance be a type IV semiconductor such as silicon or germanium or may be a type III-V semiconductor material such as gallium arsenide. In particular, the semiconductor component may be a semiconductor chip such as a naked die or a molded die.
In the context of the present application, the term “trace structure” may particularly denote an elongate element of an electrically conductive layer structure. For instance, such an elongate element may be straight, curved and/or angled. A trace structure may extend within a horizontal plane. Different horizontal trace structures may be connected with each other by perpendicular or vertical connection structures. An example of a trace structure is a wiring. For instance, a trace structure may interconnect connection structures, components, vertical through connections and/or other trace structures. For example, a trace structure may extend within a horizontal plane.
In the context of the present application, the term “connection structure” may particularly denote a laminar element of an electrically conductive layer structure. For instance, such a laminar element may be flat or two-dimensional, such as a pad. However, a connection structure may also be three-dimensional and/or may extend vertically, such as a pillar or cylinder. Based on the formation of trenches, it is also possible to provide a vertical connection with a rectangular (in particular square) footprint. For instance, a connection structure may contribute to a connection between different stacks, in particular by forming part of one stack and being connected with another connection structure of another stack. For example, a connection structure may also be connected to other connection structures, components, vertical through connections and/or trace structures. Apart from connection structures (see reference signs 130, 138) which form part of a respective stack, connection elements (see reference sign 168) may be provided for interconnecting stacks, a stack with a component, or a component with another component.
In the context of the present application, the term “density of structures” may particularly denote a number of structures per area. For example, a density of connection structures 130 of stack 102 according to
In the context of the present application, the term “the second density and the fourth density differ from each other by not more than +/−20%” may particularly denote that a ratio of, on the one hand, the difference between the second density and the fourth density of connection structures, divided by, on the other hand, the larger of the second density and the fourth density of connection structures, has an absolute value of not more than 0.2. In the context of the present application, corresponding percentages shall be calculated according to the aforementioned rule.
In the context of the present application, the term “component applied to a stack” may particularly denote a component being surface mounted to the stack or being embedded in the stack.
In the context of the present application, the term “bridge” may particularly denote a conductive bridge, for instance making a connection inside or across the stack(s) by bridging (at least) two contact areas. Generally, the bridge may comprise a bridge device, for example a bridge die. Preferably, the bridge may comprise a metallic wire or foil or the like in various shapes. For instance, the bridge may comprise a wiring structure configured to allow (at least) two connection areas to be electrically contacted, particularly configured to electrically connect (at least) two components one to another. The bridge may also be configured to electrically connect the trace structures or the connection structures or both thereof. Alternatively or additionally, the bridge may be arranged on an outer surface of the stack and configured to electrically connect (at least) two contact areas deliberately. In an embodiment, the bridge may be at least partially embedded (encapsulated) in the stack and/or the further stack. In a further embodiment, the bridge may comprise a further wiring structure electrically connecting one side of the further stack with the opposed side of said further stack (the two opposed main surfaces).
According to exemplary embodiments of the disclosure, a component carrier is provided which comprises (at least) two stacks which may be arranged on top of each other. At least two components (for example semiconductor chips) of such a component carrier shall be electrically connected with each other, so that they can cooperate functionally. The components may be assigned to the different stacks. In order to properly couple the components in a compact way, at least one of said components may be embedded in the respective stack. Furthermore, the components may be connected with each other by electrically conductive trace structures and electrically conductive connection structures. Although being connected with each other, the stacks may have even significantly different densities of trace structures, which increases the freedom of design. However, for properly connecting the stacks with each other without the need of providing a redistribution structure in between, the density of connection structures of the stacks may be very similar, to thereby ensure a matching connection geometry of both stacks. As a result, a compact design and a reliable electric coupling of the components may be ensured. The division of the electrical structures into the trace structures and further trace structures according to embodiments of the disclosure may allow the complexity to be unbundled. Moreover, this may enable a uniform structuring of the layers in the further layer structure and may thus simplify the design of the package.
In the following, further exemplary embodiments of the manufacturing method, and the component carrier will be explained.
In an embodiment, the at least one first component and the at least one second component may be connected directly or indirectly with each other. For example, said connection may be internally or externally of the stacks. For instance, said connection may be through said trace structures and said connection structures.
In an embodiment, the at least one first component comprises at least one component being embedded in the stack and/or at least one component being surface mounted on the stack. In the context of the present application, the term “embedded component” may particularly denote a component being arranged partially or entirely inside the stack. This may be accomplished by fully circumferentially surrounding the component with stack material. However, this may also be done by inserting the component in a recess or cavity of the stack while an upper main surface and/or side wall portions of the component may extend partly or entirely out of the stack. Component embedding may lead to a compact design. In contrast to this, a surface mounted component may be attached on an exterior main surface of the stack and may be connected here electrically and mechanically. Surface mounting of a component may simplify the manufacture of the component and removal of heat of the surface mounted components during operation of the component carrier.
The stacks may have a sheet (or plate) like design comprising two opposing main surfaces. The main surfaces may form the two largest surface areas of the stack. The main surfaces are connected by circumferential side walls. The thickness of a stack is defined by the distance between the two opposing main surfaces. The main surfaces may comprise functional sections, such as conductive traces or conductive interconnections with further elements, such as one or more integrated circuits (ICs).
In an embodiment, the at least one second component is encapsulated by an electrically insulating encapsulant. Such an encapsulant may be embodied, for example, as a mold structure (like an epoxy mold compound). In another example, also a dielectric layer (for example a build-up film or a solder resist, for example comprising an epoxy material) or a coating may act as an encapsulant. By encapsulation, the second component may be protected mechanically and may be isolated electrically with regard to an environment to thereby improve the electrical and mechanical reliability of the component carrier.
In an embodiment, the electrically conductive layer structures of the stack comprise a lower density stack coupling region and a higher density stack coupling region, wherein the higher density stack coupling region has the first density of trace structures and has the second density of connection structures. In particular, said density may denote an integration density. The term “density”, in particular “integration density”, may denote a number of electrically conductive structures (in particular trace structures, connection structures and/or vertical through connections, such as metallic vias) per area or volume of the respective stack coupling region. Hence, the amount of electrically conductive structures in the higher density stack coupling region may be higher than the amount of electrically conductive structures in the lower density stack coupling region. Thus, integration density may mean a quantity of electrically conductive structures per area or volume. The integration density in the lower density stack coupling region can be less than in the higher density stack coupling region, and correspondingly the line space ratio may be different. Since manufacture of a stack coupling region with high integration density may involve a larger effort than manufacture of a stack coupling region with low integration density, a high integration density needs only be manufactured in the stack where needed from a functional point of view. In other portions of the stack in which a low integration density is sufficient for fulfilling a desired function, a simplified manufacturing process can be carried out.
Advantageously, the lower density stack coupling region and the higher density stack coupling region may form integral parts of the same common stack. Thus, the lower density stack coupling region and the higher density stack coupling region do not have to be manufactured separately to be subsequently connected to each other by surface mounting or embedding. In contrast to this, the lower density stack coupling region and the higher density stack coupling region may form part of the same build-up or layer stack. For example, it may be possible that the lower density stack coupling region forms a central portion or a base portion of the layer stack, and that the higher density stack coupling region is formed on said lower density stack coupling region. In one embodiment, the higher density stack coupling region may be formed on only one main surface of the lower density stack coupling region. In another embodiment, two separate higher density stack coupling regions may be formed on both opposing main surfaces of the lower density stack coupling region. Both the lower density stack coupling region and the higher density stack coupling region may extend over the entire width of the component carrier.
In an embodiment, a line pitch of the lower density stack coupling region is in a range from 30 μm to 120 μm. In contrast to this, a line pitch of the higher density stack coupling region may be in a range from 2 μm to below 30 μm (in particular from 2 μm to 25 μm). Furthermore, wherein a line pitch of the further electrically conductive layer structures may be in a range from 0.4 μm to 10 μm. The term “line pitch” may denote a sum of a broadness of a metal trace and a broadness of dielectric material. With the described design rule in terms of line pitch, the lower density stack coupling region may be manufactured in a very simple way. In order to match with the demanding line pitch properties of the further stack, the higher density stack coupling region may have an intermediate value of the line pitch, i.e., larger than of the further stack but smaller than that of the lower density stack coupling region. This combines a reasonable manufacturing effort with a reliable electric coupling between stack and further stack, including its respective component(s).
In an embodiment, at least one of the at least one first component and the at least one second component comprises at least one of the group comprising a processor chip, a memory chip, a wafer level package, a bridge die (which may be used for interconnecting two other dies), stacked dies (i.e., a plurality of dies mounted on top of each other), and an interposer (which may be an inlay or board being vertically sandwiched between two layer structures or other components to be interconnected by the interposer). The aforementioned interposer may for example be an active interposer. For example, one component may be a processor chip and the further component may be a memory chip or a sensor chip interconnected with the processor chip, in particular by the trace structures and connection structures.
In an embodiment, at least part of the further connection structures is located at a bottom main surface of the further stack. In the context of the present application, the term “main surface of the further stack” may particularly denote one or more largest planar surface area(s) of the further stack. Usually, a for instance substantially cuboid or plate-shaped further stack may have two opposing main surfaces in the form of two horizontal surface areas on top and on bottom of the further stack. Thus, the main surface may be different from the sidewalls of the further stack. The further stack may preferably comprise two main surfaces parallel and opposite to each other, preferably spaced with respect to each other by the thickness of the further stack. In an embodiment, the further stack only has one side (which may be the bottom side) with electrical connections, so that a planar arrangement of further connection structures will then be present only on the bottom side of the further stack.
In an embodiment, at least part of the further connection structures is located at a top main surface of the further stack. In an embodiment, in which further connection structures are also provided on a top main surface of the further stack facing away from the other stack, the vertical stacking may be continued, for instance by placing yet another stack or yet another component on a top main surface of the further stack. In a corresponding embodiment, at least one further connection structure of the bottom main surface may be connected to at least one further connection structure of the top main surface through electrically conductive structures or elements inside the further stack. This may include the use of a redistribution and/or fan out structure.
In an embodiment, the second density of connection structures and the fourth density of further connection structures differ from each other by not more than +/−5%, in particular are substantially the same. In order to accomplish a proper electric connection between the top side of the stack and the bottom side of the further stack, completely matching arrangements of connection structures and further connection structures may be advantageous. By dividing the complexity into the different layer structures it may be possible to achieve a homogenous density in each of the stacks.
For instance, the arrangement of connection structures and the arrangement of further connection structures may be fully aligned, as shown for instance in
In an embodiment, the further connection structures are arranged at a main surface of the further stack facing the stack. All further connection structures may be coplanar at a bottom main surface of the further stack. This may lead to a very short electric connection path between the connection structures and the further connection structures, when the latter are arranged on a top main surface of the stack. This may have the advantage of a faster and more reliable transfer of data and/or current through the short electric connections. Hence, all connection structures may be coplanar or almost coplanar at a top main surface of the stack.
In another embodiment, some or all of the further connection structures are arranged at a main surface of the further stack facing away from the stack. By providing a further electric interface at a top main surface of the further stack, three-dimensional integration may be enhanced. For instance, still another stack (which may also have at least one assigned component) may then be mounted on top of the further stack.
In an embodiment, the component carrier comprises yet another stack comprising a plurality of other electrically conductive layer structures having a fifth density of other trace structures and a sixth density of other connection structures. Furthermore, at least one third component may be embedded in (or surface mounted on) the other stack. The second density of connection structures of the stack and the sixth density of other connection structures may differ from each other by not more than +/−20%. The first density of trace structures of the stack may be lower than the fifth density of other trace structures. The stack and the other stack may be connected with each other by the connection structures of the stack and by the other connection structures of the other stack. The at least one first component and/or the at least one second component may be connected to the at least one third component. To describe it briefly, yet another stack may be mounted on the stack, in particular side-by-side with the further stack. The electric connection between stack and other stack may correspond to the electric connection between stack and further stack. In particular, the above-mentioned higher density stack coupling region used for coupling the stack with the further stack may extend up to a region below the other stack, so that a common high density stack coupling region of the stack may be used for electrically coupling at least one component assigned to the further stack with at least one component assigned to the other stack. This may simplify the manufacture of the stack and may ensure simultaneously a proper electric coupling between the stack and multiple additional stacks (and optionally corresponding components) mounted thereon. By taking this measure, also the third component may be involved in the coupling architecture with the first and second components.
In an embodiment, the component carrier comprises at least one other component being mounted on a main surface of the further stack which main surface faces away from the stack. Apart from the surface mounted at least one further stack, one or more other components may be surface mounted on the main stack as well.
In an embodiment, the stack has an asymmetric build-up. The component carrier may be provided with a central core having a respective build-up on each of the opposing main surfaces thereof. For instance, only one main surface may be equipped with at least one further stack, and optionally with at least one surface mounted component. By properly designing the constituents of the component carrier, excessive warpage can be avoided despite of the asymmetrical build up on both sides of the core.
Exemplary embodiments may involve a configuration of the component carrier with coreless build-up and/or with a multilayer core. For example, a core provided in the stack in some embodiments (see reference sign 164 in
In an embodiment, the further stack is mounted at least partially in a recess of the stack. Additionally or alternatively, at least one component may be mounted in the recess. Such a recess may be formed in a main surface of the stack. By assembling the further stack in such a recess, a complex design in vertical direction may be obtained. This may allow to achieve a further miniaturization.
In an embodiment, the further stack is configured as a chiplet. Such a chiplet may be an integrated circuit block that has been specifically designed to work with other similar chiplets to form larger more complex component carrier-type modules. In such modules, a system may be subdivided into functional circuit blocks, i.e., said chiplets, that may be made of reusable blocks. However, it is also possible that the further stack is configured as a package accommodated at least partially in a cavity (which may be denoted as 2.5D package), as package comprising vertically stacked semiconductor chips (which may be denoted as 3D package). Furthermore, it is possible that the component carrier comprises a chiplet mounted on the further stack. It is possible that one or more chiplets are mounted on the further stack. It may also be that the stack itself carries one or more chiplets. In a 3D-package, chips may be stacked on each other.
In another embodiment, the stack and/or the further stack comprises a bridge configured to being embedded in the stack and/or the further stack. A high freedom of design may be achieved by the provision of such bridge inside the stack and/or the further stack, for example like a component-to-component coupling, an electrically conductive layer structures coupling or both thereof. In an embodiment, the bridge may electrically connect the further electrically conductive layer structures, in particular to the further trace structures or the further connection structures, in more particular to both thereof. Alternatively or additionally, the bridge may electrically connect at least two components with each other, said components being provided/assembled inside the further stack or outside of the further stack (through a respective wiring structure). In a preferable embodiment, the bridge may electrically connect the further trace structures or the further connection structures to the components surface mounted on the further stack (through connection, e.g. realized by a further wiring structure of the bridge). Advantageously, this may facilitate an efficient communication between the components either inside the further stack or outside of the further stack. In addition, this may also facilitate a simple manufacture process with a saving manufacturing source, for example a complicated interconnection through a plurality of electrically conductive layer structures may be avoided.
In a further embodiment, the bridge is (arranged) above the trace structures and/or the further trace structures and the connection structures and/or the further connection structures (in other words closer to the components than to the stack). For instance, the bridge may be configured as an interface bridge for efficient communication between the further trace structures or the further connection structures and the components (or other electrically conductive layer structures) on the top main surface of the further stack. In other words, the bridge may electronically connect one side of the further stack with an opposed side of the further stack. In another embodiment, the bridge may be configured as an interconnect bridge for electrically connecting the (at least) two components on the top main surface of the further stack. This may provide an advantage that a component carrier may be provided with a high product functionality (for example more components, being embedded and/or surface mounted, may be assembled) and an increased miniaturization (for example a more compact in a vertical direction may be obtained) in an efficient manner.
In an embodiment, the bridge comprises a further wiring structure electrically connecting one side of the stack and/or the further stack with the opposed side of the stack and/or said further stack. In an embodiment, the further wiring structure connects at least one of the (at least) two components connected to the bridge with the stack (through the further stack). In an embodiment, the bridge is exposed on (at least) one side of the (further) stack. In an embodiment, the bridge is connected to the components through connecting structures.
In an embodiment, the stack comprises at least one electrically insulating layer structure and at least one electrically conductive layer structure. For example, the component carrier may be a laminate of the mentioned electrically insulating layer structure(s) and electrically conductive layer structure(s), in particular formed by applying mechanical pressure and/or thermal energy. The mentioned stack may provide a plate-shaped component carrier capable of providing a large mounting surface for further components and being nevertheless very thin and compact.
In an embodiment, the component carrier is shaped as a plate. This contributes to the compact design, wherein the component carrier nevertheless provides a large basis for mounting components thereon. Furthermore, in particular a naked die as example for an embedded electronic component, can be conveniently embedded, thanks to its small thickness, into a thin plate such as a printed circuit board.
In an embodiment, the component carrier is configured as one of the group consisting of a printed circuit board, a substrate (in particular an IC substrate), and an interposer.
In the context of the present application, the term “printed circuit board” (PCB) may particularly denote a plate-shaped component carrier which is formed by laminating several electrically conductive layer structures with several electrically insulating layer structures, for instance by applying pressure and/or by the supply of thermal energy. As preferred materials for PCB technology, the electrically conductive layer structures are made of copper, whereas the electrically insulating layer structures may comprise resin and/or glass fibers, so-called prepreg or FR4 material. The various electrically conductive layer structures may be connected to one another in a desired way by forming holes through the laminate, for instance by laser drilling or mechanical drilling, and by partially or fully filling them with electrically conductive material (in particular copper), thereby forming vias or any other through-hole connections. The filled hole either connects the whole stack, (through-hole connections extending through several layers or the entire stack), or the filled hole connects at least two electrically conductive layers, called via. Similarly, optical interconnections can be formed through individual layers of the stack in order to receive an electro-optical circuit board (EOCB). Apart from one or more components which may be embedded in a printed circuit board, a printed circuit board is usually configured for accommodating one or more components on one or both opposing surfaces of the plate-shaped printed circuit board. They may be connected to the respective main surface by soldering. A dielectric part of a PCB may be composed of resin with reinforcing fibers (such as glass fibers).
In the context of the present application, the term “substrate” may particularly denote a small component carrier. A substrate may be a, in relation to a PCB, comparably small component carrier onto which one or more components may be mounted and that may act as a connection medium between one or more chip(s) and a further PCB. For instance, a substrate may be substantially the same size as a component (in particular an electronic component) to be mounted thereon (for instance in case of a Chip Scale Package (CSP)). In another embodiment, the substrate may be substantially larger than the assigned component (for instance in a flip chip ball grid array, FCBGA, configuration). More specifically, a substrate can be understood as a carrier for electrical connections or electrical networks as well as component carrier comparable to a printed circuit board (PCB), however with a considerably higher density of laterally and/or vertically arranged connections. Lateral connections are for example conductive paths, whereas vertical connections may be for example drill holes. These lateral and/or vertical connections are arranged within the substrate and can be used to provide electrical, thermal and/or mechanical connections of housed components or unhoused components (such as bare dies), particularly of IC chips, with a printed circuit board or intermediate printed circuit board. Thus, the term “substrate” also includes “IC substrates”. A dielectric part of a substrate may be composed of resin with reinforcing particles (such as reinforcing spheres, in particular glass spheres).
The substrate or interposer may comprise or consist of at least a layer of glass, silicon (Si) and/or a photoimageable or dry-etchable organic material like epoxy-based build-up material (such as epoxy-based build-up film) or polymer compounds (which may or may not include photo- and/or thermosensitive molecules) like polyimide or polybenzoxazole.
In an embodiment, the at least one electrically insulating layer structure comprises at least one of the group consisting of a resin or a polymer, such as epoxy resin, cyanate ester resin, benzocyclobutene resin, bismaleimide-triazine resin, polyphenylene derivate (e.g., based on polyphenylenether, PPE), polyimide (PI), polyamide (PA), liquid crystal polymer (LCP), polytetrafluoroethylene (PTFE) and/or a combination thereof. Reinforcing structures such as webs, fibers, spheres or other kinds of filler particles, for example made of glass (multilayer glass) in order to form a composite, could be used as well. A semi-cured resin in combination with a reinforcing agent, e.g., fibers impregnated with the above-mentioned resins is called prepreg. These prepregs are often named after their properties e.g., FR4 or FR5, which describe their flame-retardant properties. Although prepreg particularly FR4 are usually preferred for rigid PCBs, other materials, in particular epoxy-based build-up materials (such as build-up films) or photoimageable dielectric materials, may be used as well. For high frequency applications, high-frequency materials such as polytetrafluoroethylene, liquid crystal polymer and/or cyanate ester resins, may be preferred. Besides these polymers, low temperature cofired ceramics (LTCC) or other low, very low or ultra-low DK materials may be applied in the component carrier as electrically insulating structures.
In an embodiment, the at least one electrically conductive layer structure comprises at least one of the group consisting of copper, aluminum, nickel, silver, gold, palladium, tungsten, magnesium, carbon, (in particular doped) silicon, titanium, and platinum. Although copper is usually preferred, other materials or coated versions thereof are possible as well, in particular coated with supra-conductive material or conductive polymers, such as graphene or poly(3,4-ethylenedioxythiophene) (PEDOT), respectively.
At least one further component may be embedded in and/or surface mounted on the stack. The component and/or the at least one further component can be selected from a group consisting of an electrically non-conductive inlay, an electrically conductive inlay (such as a metal inlay, preferably comprising copper or aluminum), a heat transfer unit (for example a heat pipe), a light guiding element (for example an optical waveguide or a light conductor connection), an electronic component, or combinations thereof. An inlay can be for instance a metal block, with or without an insulating material coating (IMS-inlay), which could be either embedded or surface mounted for the purpose of facilitating heat dissipation. Suitable materials are defined according to their thermal conductivity, which should be at least 2 W/mK. Such materials are often based, but not limited to metals, metal-oxides and/or ceramics as for instance copper, aluminum oxide (Al2O3) or aluminum nitride (AlN). In order to increase the heat exchange capacity, other geometries with increased surface area are frequently used as well. Furthermore, a component can be an active electronic component (having at least one p-n-junction implemented), a passive electronic component such as a resistor, an inductance, or capacitor, an electronic chip, a storage device (for instance a DRAM or another data memory), a filter, an integrated circuit (such as field-programmable gate array (FPGA), programmable array logic (PAL), generic array logic (GAL) and complex programmable logic devices (CPLDs)), a signal processing component, a power management component (such as a field-effect transistor (FET), metal-oxide-semiconductor field-effect transistor (MOSFET), complementary metal-oxide-semiconductor (CMOS), junction field-effect transistor (JFET), or insulated-gate field-effect transistor (IGFET), all based on semiconductor materials such as silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), gallium oxide (Ga2O3), indium gallium arsenide (InGaAs), indium phosphide (InP) and/or any other suitable inorganic compound), an optoelectronic interface element, a light emitting diode, a photocoupler, a voltage converter (for example a DC/DC converter or an AC/DC converter), a cryptographic component, a transmitter and/or receiver, an electromechanical transducer, a sensor, an actuator, a microelectromechanical system (MEMS), a microprocessor, a capacitor, a resistor, an inductance, a battery, a switch, a camera, an antenna, a logic chip, and an energy harvesting unit. However, other components may be embedded in the component carrier. For example, a magnetic element can be used as a component. Such a magnetic element may be a permanent magnetic element (such as a ferromagnetic element, an antiferromagnetic element, a multiferroic element or a ferrimagnetic element, for instance a ferrite core) or may be a paramagnetic element. However, the component may also be an IC substrate, an interposer or a further component carrier, for example in a board-in-board configuration. The component may be surface mounted on the component carrier and/or may be embedded in an interior thereof. Moreover, other components, in particular those which generate and emit electromagnetic radiation and/or are sensitive with regard to electromagnetic radiation propagating from an environment, may be used as a component.
In an embodiment, the component carrier is a laminate-type component carrier. In such an embodiment, the component carrier is a compound of multiple layer structures which are stacked and connected by applying a pressing force and/or heat.
After processing interior layer structures of the component carrier, it is possible to cover (in particular by lamination) one or both opposing main surfaces of the processed layer structures symmetrically or asymmetrically with one or more further electrically insulating layer structures and/or electrically conductive layer structures. In other words, a build-up may be continued until a desired number of layers is obtained.
After having completed formation of a stack of electrically insulating layer structures and electrically conductive layer structures, it is possible to proceed with a surface treatment of the obtained layers structures or component carrier.
In particular, an electrically insulating solder resist may be applied to one or both opposing main surfaces of the layer stack or component carrier in terms of surface treatment. For instance, it is possible to form such a solder resist on an entire main surface and to subsequently pattern the layer of solder resist to expose one or more electrically conductive surface portions which shall be used for electrically coupling the component carrier to an electronic periphery. The surface portions of the component carrier remaining covered with solder resist may be efficiently protected against oxidation or corrosion, in particular surface portions containing copper.
It is also possible to apply a surface finish selectively to exposed electrically conductive surface portions of the component carrier in terms of surface treatment. Such a surface finish may be an electrically conductive cover material on exposed electrically conductive layer structures (such as pads, conductive tracks, etc., in particular comprising or consisting of copper) on a surface of a component carrier. If such exposed electrically conductive layer structures are left unprotected, then the exposed electrically conductive component carrier material (in particular copper) might oxidize, making the component carrier less reliable. A surface finish may then be formed for instance as an interface between a surface mounted component and the component carrier. The surface finish has the function to protect the exposed electrically conductive layer structures (in particular copper circuitry) and enable a joining process with one or more components, for instance by soldering. Examples for appropriate materials for a surface finish are Organic Solderability Preservative (OSP), Electroless Nickel Immersion Gold (ENIG), Electroless Nickel Immersion Palladium Immersion Gold (ENIPIG), Electroless Nickel Electroless Palladium Immersion Gold (ENEPIG), gold (in particular hard gold), chemical tin (chemical and electroplated), nickel-gold, nickel-palladium, etc. Also nickel-free materials for a surface finish may be used, in particular for high-speed applications. Examples are ISIG (Immersion Silver Immersion Gold), and EPAG (Electroless Palladium Autocatalytic Gold).
The aspects defined above, and further aspects of the disclosure are apparent from the examples of embodiment to be described hereinafter and are explained with reference to these examples of embodiment.
The illustrations in the drawings are schematically presented. In different drawings, similar or identical elements are provided with the same reference signs.
Before, referring to the drawings, exemplary embodiments will be described in further detail, some basic considerations will be summarized based on which exemplary embodiments of the disclosure have been developed.
According to an exemplary embodiment of the disclosure, a component carrier, such as an integrated circuit (IC) substrate or a printed circuit board (PCB), comprises a laminated layer stack (which also may be denoted as a main stack) with trace structures (in particular embodied as a wiring) of a first integration density and connection structures (such as pads and/or pillars) of a second integration density. For instance, the connection structures may be coplanar in a connection plane, such as a horizontal plane, of the stack. Beyond this, the component carrier may comprise a further layer stack (which may also be denoted as additional stack) with further trace structures (in particular, trace structure having a third density). To describe it briefly, the integration density of trace structures may be higher in the further stack compared with the stack. In other words, a wiring structure of the further stack may be denser than a wiring structure of the stack. Hence, only the connection structures may be provided matching for the stacks, whereas there may be a high freedom of design in terms of setting the density of the trace structures in accordance with the needs of a specific application. For example, the first density may be more than 20% larger than the third density (in particular, the difference between the third density and the first density divided by the third density may be at least 0.2). For assembling the component carrier, the stack and the further stack may be connected with each other by connecting the connection structures of the stack with the further connection structures of the further stack. For instance, said connection may be accomplished by soldering, sintering, an electrically conductive glue, or thermocompression bonding. By the described connection scheme, it may also be possible to electrically connect one or more first components applied to (for instance embedded in and/or surface mounted on) the stack to one or more second components being embedded in the further stack. By taking this measure, a functional connection between different components (preferably semiconductor chips) assigned to different stacks of a common PCB-type component carrier may be accomplished along a short connection path, which is advantageous in terms of signal integrity. In particular, signal losses may be reduced, and signal quality may be improved. These advantageous effects can be combined with a simple manufacturability of the component carrier, since demanding high integration densities need only be provided specifically in a respective one of the stacks where functionally needed. In particular, an exemplary embodiment of the disclosure may provide an ultrahigh density fan-out architecture on a substrate.
Advantageously, the stack may have a bigger surface area than the further stack (and the optional other stack). That said, the further (and the optional other) stack may be totally surface mounted on stack main surface without overhang (see figures described below).
According to a preferred embodiment, the main stack may comprise a first portion embodied as a higher density stack coupling region and a second portion embodied as a lower density stack coupling region. The higher density stack coupling region may have a higher integration density than the lower density stack coupling region. The higher density stack coupling region may be connected to the further stack, whereas the lower density stack coupling region may be spaced with respect to the further stack by the higher density stack coupling region. Both the first portion and the second portion may form integral parts of the common main stack. Advantageously, the higher density stack coupling region can be used for connecting the additional or further stack. Only here a locally increased integration density is needed in order to enable a matching connection with the further stack with its higher integration density. In order to save manufacturing resources, a remaining other portion of the stack apart from a connection to the further stack may be realized as simple lower density stack coupling region. Such a manufacturing architecture may combine an excellent reliability and a high performance with a reasonable manufacturing effort.
Conventionally, a high-density layer has been manufactured separately and has then been embedded in or assembled to a layer stack. This is cumbersome. In other embodiments, an entire component carrier has been manufactured as high density stack. This involves an excessive manufacturing effort.
To overcome the above-mentioned and/or other shortcomings at least partially, an exemplary embodiment of the disclosure provides a component carrier configured as fan-out package with a split high-density connection on substrate layers.
According to an exemplary embodiment, a component carrier is provided which comprises a stack comprising a plurality of electrically conductive layer structures and at least one electrically insulating layer structure, wherein the electrically conductive layer structures comprise a lower density stack connection region and a higher density stack connection region, and a first component and a second component both being surface-mounted on the stack, wherein the first component has a component connection region having a connection density differing not more than +/−20% from a connection density of the higher density stack connection region, wherein the first component and the second component are electrically coupled with each other by the higher density stack connection region and by the component connection region. Preferably, also the second component has a component connection region having a connection density differing not more than +/−20% from a connection density of the higher density stack connection region. By connecting two surface mount device-type components with each other on a stack in the described way, it may be possible to separate routing complexity in two parts. A first part of routing complexity may be provided by the higher density stack connection region of the stack. A second part of the routing complexity may be provided by the component connection region of the respective surface mounted component. Advantageously, this may make it dispensable to provide the highest-level routing performance on each of the components and on the substrate. In contrast to this, different technologies may be matched to distribute connection resources between components and stack. As a result, a component carrier with high reliability may be obtained.
According to such an embodiment, it may be possible to mount at least one fan-out package (in particular containing one or more components) with one or more high density routing layers on an IC (integrated circuit) substrate with one or more high density routing layers to split a requested routing density between stack and components. Moreover, at least part of the involved components may be embedded to support an improved power delivery. To put it shortly, exemplary embodiment may split a high-density connection partially in a fan-out package and partially on substrate layers.
Exemplary embodiments may have advantages. In particular, it may be possible to improve or even optimize routing layers by splitting density layers. Furthermore, high density routing layers in a fan-out package may lower the demand of routing density on a substrate. Beyond this, high density routing on a fan-out region can be achieved easier and with higher yield. Advantageously, routing between components within a fan-out package can be outsourced to a mainboard. Moreover, a known good fan-out package may be provided on a known good substrate, which may further increase the yield. Furthermore, the manufacturing architecture according to exemplary embodiments of the disclosure may lead to a height reduction of the obtained component carrier. A high freedom of design may be achieved by the opportunity of integrating active and/or passive components, in embedding technology and/or by surface mounting. By accomplishing component-to-component coupling by matching connection structures of stack and a further stack, substrate embedded bridge dies as well as patch redistribution layers may be dispensable.
Exemplary applications of exemplary embodiments of the disclosure are high performance computing applications, server/cloud applications, chiplets, advanced driver assistance systems, and modules or packages involving artificial intelligence (AI).
The component carrier 100 according to
Now referring to
As can be taken from
As also shown in
Further stack 132 may comprise one or more further electrically insulating layer structures shown schematically with reference sign 107 and a plurality of further electrically conductive layer structures 134. The further electrically insulating layer structures 107 can be embodied as described above for electrically insulating layer structures 106 of stack 102. Furthermore, the further electrically conductive layer structures 134 are only shown schematically in
Again referring to
In view of the foregoing, the second density of connection structures 130 and the fourth density of further connection structures 138 differ from each other only slightly, for instance by about 10% (please note that the drawing of
Hence, the density of the connection structures 130, 138 may be substantially the same in both stacks 102, 132. Consequently, the connection pattern of the connection structures 130 and of the further connection structures 138 may match at least approximately. In other words, the connection structures 130 and the further connection structures 138 may be in alignment, as shown in
In contrast to this, there is no need to have similar densities of tracing structures 128, 136. Hence, tracing structures 128, 136 may be freely designed for stack 102 and further stack 132 separately, which increases the freedom of design.
Again referring to
The embedded components 124 are embedded in stack 102, more specifically in a core 164 thereof. However, in other embodiments core 164 may be substituted by a dielectric multilayer. In a coreless embodiment (which may be implemented with or without embedding of components), the manufacturing process may omit a core and may start with any sacrificial carrier, for example a glass plate.
The surface mounted components 140 are surface mounted on an upper main surface of the stack 102 on which also the further stack 132 is surface mounted. For example, the embedded components 124 may be passive components, such as capacitors, integrated passive devices (IPDs), power management integrated circuits (PMICs), etc. For instance, the surface mounted components 140 may be high bandwidth memories (HBMs). Also, one or more embedded inductors are possible in an embodiment.
Moreover, a plurality of second components 142 are embedded in the further stack 132. Said second components 142 may be for example central processing units (CPUs), controller chips, etc.
Referring again to
As shown in
Now referring specifically to stack 102, the electrically conductive layer structures 104 comprise higher density stack coupling regions 108 and a lower density stack coupling region 110 in between. The upper higher density stack coupling region 108 has the first density of trace structures 128 and has the second density of connection structures 130. According to
In an embodiment, the two opposed higher density stack coupling regions 108 may be electrically connected by vertical connection elements or structures, preferably by plated through holes (PTH) which penetrate trough the stack thickness of stack 164.
By the electrically conductive layer structures 104, 134 and 148, the first components 124, 140, the second components 142 and the third component 154 may be electrically connected with each other. In a nutshell, the construction and the stack coupling of the other stack 146 may be corresponding to the construction and the stack coupling of the further stack 132, as described above in detail. For instance, the other stack 146 with the encapsulated third component 154 may be a wafer level package. Stack 146 (and its component 154) and stack 132 (and its components 142) may be electrically connected with each other by the upper higher density stack coupling region 108. At the bottom side of each of stack 146 and stack 132, a routing structure may be formed which contributes to said connection. Said routing structure may comprise, for example, one, two or three layers.
Furthermore, the upper higher density stack coupling region 108 of
As can be taken from the dimensions of the elements of the electrically conductive layer structure 104 in
A line pitch of the further electrically conductive layer structures 134 (for example 2 μm), being directly electrically coupled with the embedded second components 142, may be even less than the line pitch in the higher density stack coupling region 108. Hence, the upper higher density stack coupling region 108 may function as an interface between the typically higher line pitch of component carrier technology (as present in core 164) and the typically lower line pitch of semiconductor technology (as present in components 142, 154 being directly coupled with the further electrically conductive layer structures 134 of the further stack 132). Moreover, high density resources may be split between the further stack 132 and the upper higher density stack coupling region 108.
According to
Again referring to
In summary, the embodiment of
Preferably, there may be higher density copper portions in the first density of trace structures 128 in the area below first components 140 and/or the further stack 132 and/or the area between first components 140 and/or the further stack 132 to connect said two elements. However, there may be some portions in the first density of trace structures 128 where there is less copper loading in the stack 102 (preferably not under the components and between them). In other words, not all layers need to be made of copper, for instance none or one as indicated with an arrow 199 in
For manufacturing a component carrier 100 such as the one shown in
A main difference between the embodiment of
As core 164, any multilayer or any other layer boards may be used.
A main difference between the embodiment of
A main difference between the embodiment of
Although the other stack 146 is omitted in the embodiment of
A main difference between the embodiment of
Descriptively speaking,
Next, a further embodiment will be explained referring in particular to the embodiments of
Advantageously, the at least one electrically insulating layer structure 106 of stack 102 comprises at least two sub-structures made of different dielectric materials. In particular, the electrically insulating material of one or more of the electrically insulating layer structures 106 of one or more higher density stack coupling regions 108 (i.e., dielectric material surrounding trace structures 128 and connection structures 130) may be different from the electrically insulating material of one or more electrically insulating layer structures 106 of the one or more lower density stack coupling region 110 (such as material of core 164 according to
Next, a further embodiment will be explained in particular referring to the embodiment of
In other words, the bridge 250 is electrically connected to the further electrically conductive layer structures 134, in particular to the further trace structures 136. Further, the bridge 250 preferably comprises a wiring structure 251 configured to connect (at least) two components 126 one to each other and/or a further wiring structure 252 connected to the further trace structures 136. The wiring structure 251 can be seen as an (embedded in the further stack) interconnection between surface-mounted components, while the further wiring structure 252 can be seen as a through-connection (through the further stack).
It should be noted that the term “comprising” does not exclude other elements or steps and the article “a” or “an” does not exclude a plurality. Also, elements described in association with different embodiments may be combined.
Implementation of the disclosure is not limited to the preferred embodiments shown in the figures as described above. Instead, a multiplicity of variants is possible which use the solutions shown and the principle according to the disclosure even in the case of fundamentally different embodiments.
This application is a continuation-in-part of and claims benefit to the earlier filing date of U.S. patent application Ser. No. 17/655,162, filed Mar. 16, 2022, the entire contents of which are herein incorporated by reference.
| Number | Date | Country | |
|---|---|---|---|
| Parent | 17655162 | Mar 2022 | US |
| Child | 18825196 | US |
