Patent Application
20250220819
As advanced packaging is enabling more aggressive computation capability, high power and high quality power delivery is needed to support all of the overlying chiplets. Accordingly, the ability to embed passive components (e.g., capacitors, inductors, resistors, etc.) into the package substrate will enable improved performance compared to placing the passive components on the land side of the package. Embedding components in the core is beneficial because there is less routing in the core compared to overlying and underlying buildup layers. As such, space within the package substrate is more fully utilized.
However, substrate core thickness is defined by the total package thermomechanical stress level. This required thickness can be significantly different than the thickness of the passive component. For example, in the case of a deep trench capacitor (DTC), the DTC is fabricated on a silicon wafer. The wafer will have a thickness that is potentially hundreds of microns different than the thickness of the core, which can be approximately 1.0 mm or greater. Placing such passive components in deep cavities through the core can be problematic. For example, the passive components may shift or rotate during embedding.
Described herein are electronic systems, and more particularly, devices with a substrate embedded in a mold layer and placed in a cavity through a core of a package substrate, in accordance with various embodiments. In the following description, various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. However, it will be apparent to those skilled in the art that the present disclosure may be practiced with only some of the described aspects. For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the illustrative implementations. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without the specific details. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative implementations.
Various operations will be described as multiple discrete operations, in turn, in a manner that is most helpful in understanding the present disclosure, however, the order of description should not be construed to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation.
Various embodiments or aspects of the disclosure are described herein. In some implementations, the different embodiments are practiced separately. However, embodiments are not limited to embodiments being practiced in isolation. For example, two or more different embodiments can be combined together in order to be practiced as a single device, process, structure, or the like. The entirety of various embodiments can be combined together in some instances. In other instances, portions of a first embodiment can be combined with portions of one or more different embodiments. For example, a portion of a first embodiment can be combined with a portion of a second embodiment, or a portion of a first embodiment can be combined with a portion of a second embodiment and a portion of a third embodiment.
As noted above, introducing passive components (e.g., inductors, capacitors, resistors, etc.) into the package substrate is desirable to improve power delivery and performance for the overlying chiplets compared to placing the passive components on the land side of the package substrate. This is due, at least in part, to the passive components being physically closer to the chiplets when they are integrated into the package substrate. One suitable location in the package substrate for the passive components is the core. The core has underutilized space that can be leveraged to house the passive components. However, the thickness of the passive components is usually smaller than a thickness of the core. This can lead to integration and manufacturing issues. Examples of these drawbacks can be seen in
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In an embodiment, a component 120 is provided in the cavity 107. The component 120 may have a thickness that is smaller than a thickness of the core 105. For example, the component 120 may have a thickness that is hundreds of microns thinner than the core 105. The component 120 is secured within the cavity 107 through the use of a fill layer 125. The fill layer 125 may be a dielectric material, such as a mold layer, an epoxy, an adhesive, or the like. However, during the filling process, the component 120 may shift and/or rotate. The movement of the component 120 may be due, at least in part, to the introduction of pressure to the component 120 during the filling process. As shown, the component 120 has tilted so that one side is raised up from the bottom of the core 105. This may make it difficult to make electrical contact to the pads 122 that are at the bottom of the component 120 in subsequent processing operations.
Accordingly, embodiments disclosed herein reduce movement of the electrically passive component by providing a device that comprises a component that is at least partially embedded in a mold layer. The mold layer provides additional thickness to the device in order to substantially match the thickness of the core. The mold layer may be provided on multiple surfaces of the electrically passive component. For example, the mold layer may be provided over a bottom surface of the electrically passive component and along sidewalls of the electrically passive component. In an embodiment, a top surface of the electrically passive component is substantially coplanar with a top surface of the mold layer. That is, the top surface of the electrically passive component remains exposed in order to allow for electrical connection to the electrically passive component.
In an embodiment, the device may be formed through multiple different process flows. In one embodiment, each electrically passive component is overmolded with a molding material. In other embodiments, a plurality of electrically passive components can be overmolded together to form a reconstituted substrate. The electrically passive components can then be singulated into individual devices.
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In an embodiment, the substrate 221 may include any suitable material that provides a solid base on which (or into which) passive structures can be fabricated. In some embodiments, the substrate 221 may comprise a semiconductor material, such as silicon. For example, a silicon wafer may be processed to produce a plurality of passive devices. After processing, the silicon wafer is singulated in order to provide individual substrates 221. While silicon can be used in some embodiments, other embodiments may include a substrate 221 that comprises a ceramic, a glass, an insulator, or the like.
In an embodiment, the routing layer 223 may be a different material than the substrate 221. For example, the routing layer 223 may include a dielectric material, such as one comprising silicon and oxygen (e.g., SiO2) or silicon and nitrogen (e.g., Si3N4). Organic dielectrics may also be used in some embodiments. The routing layer 223 may include electrical routing (not shown), such as pads, traces, and/or the like. In some embodiments, the routing layer 223 is omitted, or the electrical routing is otherwise provided in and/or on the substrate 221.
In an embodiment, a layer 224 is provided around the substrate 221 and/or the routing layer 223. The layer 224 may be a molding material, such as, but not limited to, an epoxy, an organic dielectric material, or the like. In some embodiments, filler particles (not shown) may be dispersed within the layer 224. Filler particles may be used in order to modify a coefficient of thermal expansion (CTE) of the layer 224 in order to more closely match the CTE of the substrate 221 and/or the routing layer 223. Matching CTEs may reduce stress and provide enhanced reliability.
In an embodiment, the layer 224 may contact a first surface 244 of the substrate 221 and sidewall surfaces 245 of the substrate 221. The layer 224 may also contact a sidewall 247 of the routing layer 223. In an embodiment, a top surface 241 of the layer 224 may be substantially coplanar with a surface 242 of the routing layer 223 (or with a surface 243 of the substrate 221 when the routing layer 223 is omitted). As used herein, “substantially coplanar” may refer to two surfaces that are within 10 μm of being coplanar with each other.
In an embodiment, the layer 224 may have a first thickness T1 between sidewall 245 of the substrate 221 and sidewall 249 of the layer 224. The layer 224 may have a second thickness T2 between the bottom surface 244 of the substrate 221 and the bottom surface 248 of the layer 224. In an embodiment, the second thickness T2 may be greater than the first thickness T1. A total thickness of the device 220 between the bottom surface 248 of the layer 224 and the top surface 241 of the layer 224 may be approximately 500 μm or greater, approximately 1.0 mm or greater, or approximately 1.5 mm or greater. Though, thinner thicknesses for the device 220 may also be used in some embodiments. In an embodiment a combined thickness of the substrate 221 and the routing layer 223 may be a third thickness T3. When the routing layer 223 is omitted, the third thickness T3 may simply be the thickness of the substrate 221. In an embodiment, the third thickness T3 may be approximately 1.5 mm or smaller, approximately 1.0 mm or smaller, approximately 700 μm or smaller, approximately 500 μm or smaller, or approximately 200 μm or smaller. Though, larger third thicknesses T3 may also be used in some embodiments. As used herein, “approximately” may refer to a range of values within ten percent of the stated value. For example, approximately 500 μm may refer to a range between 450 μm and 550 μm. In an embodiment, a width of the layer 224 is greater than a width of the substrate 221.
In an embodiment, the device 220 may further comprise pads 222. The pads 222 may be electrically conductive material (e.g., comprising copper). The pads 222 may provide electrical coupling to the one or more electrically passive components on and/or in the substrate 221 and/or the routing layer 223. In the illustrated embodiment, the pads 222 extend up from the surface 242 of the routing layer 223. In other embodiments, the pads 222 may be embedded within the routing layer 223 or the substrate 221 (when the routing layer 223 is omitted).
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In an embodiment, the substrate 321 and the routing layer 323 may be similar to substrates and routing layers described in greater detail herein. For example, the substrate 321 or the substrate 321 and the routing layer 323 may house one or more electrically passive devices, such as an inductor, a capacitor, or a resistor. The carrier 350 may be a temporary support surface. The carrier 350 may comprise glass, ceramic, silicon, metal, or any other rigid material.
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In an embodiment, the substrates 421 and the routing layers 423 may be similar to substrates and routing layers described in greater detail herein. For example, the substrates 421 or the substrates 421 and the routing layers 423 may house one or more electrically passive devices, such as an inductor, a capacitor, or a resistor. The carrier 450 may be a temporary support surface. The carrier 450 may comprise glass, ceramic, silicon, metal, or any other rigid material.
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In an embodiment, the process 470 may continue with operation 472, which comprises forming a layer around the devices to form a reconstituted substrate, in accordance with an embodiment. In an embodiment, operation 472 may include structures and processes similar to those described herein with respect to
In an embodiment, the process 470 may continue with operation 473, which comprises singulating the reconstituted substrate to from a plurality of devices embedded in the layer. In an embodiment, operation 473 may include structures and processes similar to those described herein with respect to
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The glass core 505 may have any suitable dimensions. In a particular embodiment, the glass core 505 may have a thickness that is approximately 50 μm or greater. For example, the thickness of the glass core 505 may be between approximately 50 μm and approximately 1.4 mm. Though, smaller or larger thicknesses may also be used. The glass core 505 may have edge dimensions (e.g., length, width, etc.) that are approximately 10 mm or greater. For example, edge dimensions may be between approximately 10 mm to approximately 250 mm. Though, larger or smaller edge dimensions may also be used. More generally, the area dimensions of the glass core 505 (from an overhead plan view) may be between approximately 10 mm×10 mm and approximately 250 mm×250 mm. In an embodiment, the glass core 505 may have a first side that is perpendicular or orthogonal to a second side. In a more general embodiment, the glass core 505 may comprise a rectangular prism volume with sections (e.g., vias) removed and filled with other materials (e.g., metal, etc.).
The glass core 505 may comprise a single monolithic layer of glass. In other embodiments, the glass core 505 may comprise two or more discrete layers of glass that are stacked over each other. The discrete layers of glass may be provided in direct contact with each other, or the discrete layers of glass may be mechanically coupled to each other by an adhesive or the like. The discrete layers of glass in the glass core 505 may each have a thickness less than approximately 50 μm. For example, discrete layers of glass in the glass core 505 may have thicknesses between approximately 25 μm and approximately 50 μm. Though, discrete layers of glass may have larger or smaller thicknesses in some embodiments. As used herein, “approximately” may refer to a range of values within ten percent of the stated value. For example approximately 50 μm may refer to a range between 45 μm and 55 μm.
The glass core 505 may be any suitable glass formulation that has the necessary mechanical robustness and compatibility with semiconductor packaging manufacturing and assembly processes. For example, the glass core 505 may comprise aluminosilicate glass, borosilicate glass, alumino-borosilicate glass, silica, fused silica, or the like. In some embodiments, the glass core 505 may include one or more additives, such as, but not limited to, Al2O3, B2O3, MgO, CaO, SrO, BaO, SnO2, Na2O, K2O, SrO, P2O3, ZrO2, Li2O, Ti, or Zn. More generally, the glass core 505 may comprise silicon and oxygen, as well as any one or more of aluminum, boron, magnesium, calcium, barium, tin, sodium, potassium, strontium, phosphorus, zirconium, lithium, titanium, or zinc. In an embodiment, the glass core 505 may comprise at least 23 percent silicon (by weight) and at least 26 percent oxygen (by weight). In some embodiments, the glass core 505 may further comprise at least 5 percent aluminum (by weight).
In an embodiment, the core 505 may comprise cladding 503 above and/or below the core 505. The cladding 503 may include an electrically conductive material, such as one comprising copper or the like. While shown with cladding 503, other embodiments may include a core 505 that omits one or both cladding 503 layers.
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In an embodiment, the device 520 may be similar to any device described in greater detail herein. For example, the device 520 may comprise a substrate 521 with a routing layer 523. A layer 524 may at least partially embed the substrate 521 and the routing layer 523. In an embodiment, a width of layer 524 may be less than a width of the cavity 507. Pads 522 may also be provided on the routing layer 523.
In an embodiment, the core 505 may have a first thickness T1, and the layer 524 may have a second thickness T2 that is substantially equal to the first thickness T1. A combined third thickness T3 of the substrate 521 and the routing layer 523 may be smaller than the second thickness T2. That is, the layer 524 of the device 520 modifies the overall thickness of the device 520 in order to match the thickness of the core 505 in order to simplify assembly processes.
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In an embodiment, a cavity 607 may be provided through a thickness of the core 605. A plurality of devices 620 may be embedded in the cavity 607 by a fill layer 625. For example, a first device 620A and a second device 620B are shown in
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In an embodiment, a first cavity 707A and a second cavity 707B may be provided through a thickness of the core 705. A device 720A or 720B may be embedded in each of the cavities 707A and 707B by a fill layer 725. For example, a first device 720A may be provided in the first cavity 707A, and a second device 720B may be provided in the second cavity 707B. The first device 720A and the second device 720B may be substantially similar to each other. For example, both may include a substrate 721 with a routing layer 723. Layers 724 may surround both devices 720A and 720B. In an embodiment, devices 720A and 720B may be similar to any devices described in greater detail herein. Additionally, pads 722 may be provided on each device 720. Buildup layers 711 may be provided over and/or under the core 705.
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In an embodiment, the package substrate 800 may be similar to any of the package substrates described herein. For example, the package substrate 800 may include a core 805 (e.g., a glass core 805 or an organic core 805) with buildup layers 811 above and below the core 805. The core 805 may comprise vias 808. In
In an embodiment, the device 820 may be similar to any of the devices described in greater detail herein. For example, the device 820 may be a passive component such as one or more of an inductor, a capacitor, a resistor, or the like. The device 820 may have a total thickness that is substantially equal to a thickness of the core 805. In an embodiment, the device 820 may comprise a substrate 821 and a routing layer 823, both of which may be at least partially embedded by a layer 824.
In an embodiment, one or more dies 895 may be coupled to the package substrate 800 by interconnects 894. The interconnects 894 may comprise first level interconnects (FLIs), such as solder balls, copper bumps, hybrid bonding interfaces, or the like. The die 895 may be any type of die, such as a central processing unit (CPU), a graphics processing unit (GPU), an XPU, a communications die, a memory die, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or the like. In an embodiment, the device 820 is electrically coupled to the one or more dies 895 in order to control and/or improve power delivery that is provided to the die 895.
These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).
The communication chip 906 enables wireless communications for the transfer of data to and from the computing device 900. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 906 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device 900 may include a plurality of communication chips 906. For instance, a first communication chip 906 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 906 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
The processor 904 of the computing device 900 includes an integrated circuit die packaged within the processor 904. In some implementations of the disclosure, the integrated circuit die of the processor may be part of an electronic package that includes a device with a substrate that is at least partially embedded in a mold layer that has a thickness that is substantially equal to a thickness of a core of the package substrate, in accordance with embodiments described herein. The term “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
The communication chip 906 also includes an integrated circuit die packaged within the communication chip 906. In accordance with another implementation of the disclosure, the integrated circuit die of the communication chip may be part of an electronic package that includes a device with a substrate that is at least partially embedded in a mold layer that has a thickness that is substantially equal to a thickness of a core of the package substrate, in accordance with embodiments described herein.
In an embodiment, the computing device 900 may be part of any apparatus. For example, the computing device may be part of a personal computer, a server, a mobile device, a tablet, an automobile, or the like. That is, the computing device 900 is not limited to being used for any particular type of system, and the computing device 900 may be included in any apparatus that may benefit from computing functionality.
The above description of illustrated implementations of the disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. While specific implementations of, and examples for, the disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as those skilled in the relevant art will recognize.
These modifications may be made to the disclosure in light of the above detailed description. The terms used in the following claims should not be construed to limit the disclosure to the specific implementations disclosed in the specification and the claims. Rather, the scope of the disclosure is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.
Example 1: an apparatus, comprising: a substrate with a first width, wherein the substrate comprises a first surface, a second surface opposite from the first surface, and sidewall surfaces coupling the first surface to the second surface; and a layer with a second width that is greater than the first width, wherein the layer contacts the substrate and covers the sidewall surfaces and the first surface of the substrate.
Example 2: the apparatus of Example 1, wherein the substrate further comprises: a dielectric layer over the second surface, and wherein the layer covers sidewalls of the dielectric layer.
Example 3: the apparatus of Example 2, further comprising: a pad over the dielectric layer, wherein the pad is electrically conductive.
Example 4: the apparatus of Examples 1-3, wherein the substrate comprises a silicon substrate.
Example 5: the apparatus of Examples 1-4, wherein the layer comprises an epoxy or an organic dielectric material.
Example 6: the apparatus of Examples 1-5, wherein the substrate comprises one or more of an inductor, a capacitor, or a resistor.
Example 7: the apparatus of Examples 1-6, wherein a first thickness of the layer between a sidewall of the layer and the sidewall of the substrate is smaller than a second thickness of the layer between a bottom of the layer and the first surface of the substrate.
Example 8: the apparatus of Examples 1-7, wherein a thickness of the apparatus is approximately 1.0 mm or greater.
Example 9: the apparatus of Example 8, wherein a thickness of the substrate is up to approximately 700 μm.
Example 10: an apparatus, comprising: a core wherein the core has a first thickness; a cavity through a thickness of the core; a device in the cavity, wherein the device has a second thickness that is substantially equal to the first thickness, and wherein the device comprises: a first layer; and a passive component at least partially embedded in the first layer; and a second layer around the device within the cavity.
Example 11: the apparatus of Example 10, wherein the first layer is a different material than the second layer.
Example 12: the apparatus of Example 10 or Example 11, wherein the first layer is an epoxy, and wherein the second layer is an organic buildup film.
Example 13: the apparatus of Examples 10-12, wherein a surface of the first layer is substantially coplanar with a surface of the passive component.
Example 14: the apparatus of Examples 10-13, wherein the passive component comprises one or more of an inductor, a capacitor, or a resistor.
Example 15: the apparatus of Examples 10-14, wherein the core is an organic core or a glass core with a rectangular prism form factor.
Example 16: the apparatus of Examples 10-15, wherein the first layer covers a bottom surface of the passive component and sidewall surfaces of the passive component.
Example 17: an apparatus, comprising: a board; a package substrate coupled to the board, wherein the package substrate comprises: a core with a first thickness; and a passive component in a cavity through the core, wherein the passive component is embedded in an epoxy mold layer with a second thickness that is substantially equal to the first thickness, and wherein a width of the epoxy mold layer is smaller than a width of the cavity; and a die coupled to the package substrate.
Example 18: the apparatus of Example 17, wherein the passive component has a third thickness that is smaller than the first thickness.
Example 19: the apparatus of Example 17 or Example 18, wherein the passive component comprises one or more of an inductor, a capacitor, or a resistor.
Example 20: the apparatus of Examples 17-19, wherein the apparatus is part of a personal computer, a server, a mobile device, a tablet, or an automobile.
