Patent Application
20230137996
Flip-chip packaging is a method for interconnecting semiconductor devices, such as integrated circuit (IC) dies and micro-electromechanical systems (MEMS), to external circuitry using solder bumps that have been deposited onto die pads. The solder bumps are deposited on die pads on the top side of a semiconductor wafer during wafer processing. In order to mount the chip to external circuitry, such as a circuit board or another chip, the wafer is flipped over so that its top side faces down. The upside-down wafer is then aligned so that conductive pads on the wafer align with matching pads on the external circuit or lead frame. Solder on the bumps is reflowed to complete the interconnect between the devices. The bumps are conductive members that electrically and mechanically couple device areas of the dies through metal redistribution layers, polyimide layers, passivation layers, die pads, etc.
A semiconductor package includes a semiconductor die having a device side, a conductive layer coupled to the device side, a conductive pillar coupled to the conductive layer, the conductive pillar having an upper portion and a base portion, the upper portion having a wider diameter than the base portion and the conductive pillar having a mushroom shape, a polyimide layer coupled to the conductive layer and surrounding the conductive pillar, a solder layer coupled to the conductive pillar, wherein the polyimide layer does not extend between a top surface of the conductive pillar and the solder layer, and a conductive terminal, such as a lead frame, coupled to the solder layer and exposed to a surface of the semiconductor package, the device side of the semiconductor die facing the conductive terminal.
A semiconductor package includes a semiconductor die having a device side, a conductive layer coupled to the device side, a conductive pillar coupled to the conductive layer, the conductive pillar having an upper portion and a base portion, the base portion having a wider diameter than the upper portion, wherein the base portion of the conductive pillar has sloped sides extending from the upper portion to the conductive layer, a polyimide layer coupled to the conductive layer and surrounding the conductive pillar, a solder layer coupled to the conductive pillar, wherein the polyimide layer does not extend between a top surface of the conductive pillar and the solder layer, and a conductive terminal coupled to the solder layer and exposed to a surface of the semiconductor package, the device side of the semiconductor die facing the conductive terminal.
A method of manufacturing a semiconductor package includes providing a semiconductor wafer having a device side, forming a conductive layer above the device side, forming a conductive pillar above the conductive layer, the conductive pillar having a base portion and an upper portion, wherein one of the base or upper portions is wider than the other portion such that the conductive pillar has a mushroom shape or the base portion has sloped sides extending from the upper portion to the conductive layer, forming a polyimide layer abutting the conductive layer and surrounding the conductive pillar, positioning a conductive member on the conductive pillar, wherein the polyimide layer does not extend between a top surface of the conductive pillar and the conductive member, reflowing the conductive member, singulating the semiconductor wafer to produce a die having the conductive layer, the conductive pillar, the polyimide layer, and the reflowed conductive member, coupling the reflowed conductive member to a conductive terminal using a reflow technique, thereby producing a solder layer coupling the conductive pillar to the conductive terminal, and covering the die, the conductive pillar, the solder layer, and the conductive terminal in a molding, the conductive terminal exposed to a surface of the molding.
Having thus described the invention in general terms, reference will now be made to the accompanying drawings, wherein:
The present disclosure is described with reference to the attached figures. The figures are not drawn to scale, and they are provided merely to illustrate the disclosure. Several aspects of the disclosure are described below with reference to example applications for illustration. It should be understood that numerous specific details, relationships, and methods are set forth to provide an understanding of the disclosure. The present disclosure is not limited by the illustrated ordering of acts or events, as some acts may occur in different orders and/or concurrently with other acts or events. Furthermore, not all illustrated acts or events are required to implement a methodology in accordance with the present disclosure.
In the drawings, like reference numerals refer to like elements throughout, and the various features are not necessarily drawn to scale. Corresponding numerals and symbols in the different figures generally refer to corresponding parts, unless otherwise indicated. In the following discussion and in the claims, the terms “including,” “includes,” “having,” “has,” “with,” or variants thereof are intended to be inclusive in a manner similar to the term “comprising”, and thus should be interpreted to mean “including, but not limited to . . . ” Also, the terms “coupled,” “couple,” and/or or “couples” is/are intended to include indirect or direct electrical or mechanical connection or combinations thereof. For example, if a first device couples to or is electrically coupled with a second device that connection may be through a direct electrical connection, or through an indirect electrical connection via one or more intervening devices and/or connections. Terms such as “top,” “bottom,” “front,” “back,” “over,” “above,” “under,” “below,” and such, may be used in this disclosure. These terms should not be construed as limiting the position or orientation of a structure or element but should be used to provide spatial relationship between structures or elements.
In flip chip packaging, products use a solder alloy to bond metallic pillars or posts, which are formed on a semiconductor die, to a lead frame. Typically, the posts are copper (Cu), and the lead frame is copper. In one example, manufacturing costs may be reduced by eliminating a typical sputter and etch process step and by applying a passivation layer, such as a polyimide (PI) layer, after creation of the posts. While a solder bond provides a good connection between the copper posts and a copper lead frame, there are potential solder-joint quality and reliability issues when a passivation layer is applied after creating the posts and not removed before solder is attached to the posts. For example, the PI layer may overlap the top of the post if a typical post design is used. This PI overlap can reduce the interfacial surface area between the solder and the post, for example, by covering an outer edge on the top surface of the post, thereby leaving a smaller area available on the top of the post for bonding to the solder. As used herein, the term interfacial region refers to an exposed area on one feature adapted for bonding to another feature. By reducing the interfacial surface area, the bond between the solder and the post may be subject to higher stress due to its smaller connection, which is detrimental to the package's lifespan and may reduce the electronic performance to the package.
An example process for producing a flip-chip device is disclosed herein. The process eliminates PI overlap by modifying the structure of the posts on the semiconductor wafer. In one configuration, a mushroom-like post is created by applying a resist thickness that is lower than a target post height. As used herein, the term mushroom-like refers to a structure having a columnar base with a wider circular top, such as an umbrella-shaped cap. In another configuration, a footing is created on the posts by modifying photoresist process parameters. The footing provides a wide base portion of the post. In one example, the footing has sloping sides that ramp downward from the post to a contact layer. These configurations create structures that prevent the PI layer from overlapping the post, which thereby prevents a reduction in interfacial surface area between the post and the solder.
Prior to applying the solder ball 105 to post 103, a PI passivation layer 107 is applied over semiconductor die 101 and contact area 102. The PI layer 107 also surrounds post 103 and, using existing designs, a portion 107a of the PI layer 103 typically overlaps at least a portion of top surface 103a on post 103. As a result, the interfacial region 104 between post 103 and solder ball 105 is less than the entire top surface 103a of post 103. The solder ball 105 forms a layer between post 103 and lead frame 106. Because the interfacial region 104 is narrower than the available post surface 103a, current capacity through post 103 to or from circuitry on die 101 may be limited. Furthermore, because the post-solder interface is narrower than otherwise possible, there may be a tendency for cracks to form between lead frame 106 and post 103, for example, due to thermal cycling.
Steps 201 and 202 are illustrated in
The method 200 further comprises exposing and developing the photoresist layer to create an orifice 305. In one example, as illustrated in
The method 200 further comprises plating a conductive pillar in the developed area of the photoresist layer 204. For example, as shown in
The method 200 further comprises stripping the photoresist layer 205 to expose a mushroom-shaped conductive pillar with a domed top surface. As shown in
The method 200 comprises placing (e.g., dropping) a conductive member on the conductive pillar 207. For example, in
The method 200 then comprises singulating the wafer (e.g., using a sawing technique) to produce a die 209 that includes the structures depicted in
Steps 401 and 402 are illustrated in
The method 400 further comprises exposing and developing the photoresist layer to create an opening 505. As
The method 400 further comprises plating a conductive pillar in the developed area of the photoresist layer 404. For example, as shown in
The method 400 further comprises stripping the photoresist layer 405 to expose a conductive pillar with a wide footing portion. As shown in
The method 400 comprises placing (e.g., dropping) a conductive member on the conductive pillar 407. For example, in
The method 400 then comprises singulating the wafer (e.g., using a sawing technique) to produce a die 409 that includes the structures depicted in
An example semiconductor package includes a semiconductor die having a device side with a conductive layer coupled to the device side. A conductive pillar is coupled to the conductive layer. The conductive pillar has an upper portion and a base portion. The upper portion has a wider diameter than the base portion so that a lip on the underside of the upper portion extends away from the base portion. A polyimide layer is coupled to the conductive layer and surrounds the conductive pillar. A solder layer is coupled to the conductive pillar. The polyimide layer does not extend between a top surface of the conductive pillar and the solder layer. A conductive terminal, such as a lead frame, is coupled to the solder layer and is exposed to a surface of the semiconductor package. The device side of the semiconductor die faces the conductive terminal. The conductive pillar may be copper. The conductive pillar may have a mushroom shape. The top surface of the conductive pillar may have a convex or domed shape. The upper portion of the conductive pillar extends farther away from the device side of the semiconductor die than does the polyimide layer.
Another example semiconductor package includes a semiconductor die having a device side. A conductive layer is coupled to the device side. A conductive pillar is coupled to the conductive layer. The conductive pillar has an upper portion and a base portion. The base portion has a wider diameter than the upper portion. A polyimide layer is coupled to the conductive layer and surrounds the conductive pillar. A solder layer is coupled to the conductive pillar. The polyimide layer does not extend between a top surface of the conductive pillar and the solder layer. A conductive terminal, such as a lead frame, is coupled to the solder layer and is exposed to a surface of the semiconductor package. The device side of the semiconductor die faces the conductive terminal. The conductive pillar may be copper. The base portion of the conductive pillar may have sloped sides that extend from the upper portion to the conductive layer. The top surface of the conductive pillar may have a convex or domed shape. The upper surface of the conductive pillar extends farther away from the device side of the semiconductor die than does the polyimide layer.
An example method of manufacturing a semiconductor package includes the steps of providing a semiconductor wafer having a device side, forming a conductive layer above the device side, forming a conductive pillar above the conductive layer, the conductive pillar having a base portion and an upper portion, wherein one of the base or upper portions is wider than the other portion. The example method further includes forming a polyimide layer abutting the conductive layer and surrounding the conductive pillar, positioning a conductive member on the conductive pillar, wherein the polyimide layer does not extend between a top surface of the conductive pillar and the conductive member. The example method further includes reflowing the conductive member, singulating the semiconductor wafer to produce a die having the conductive layer, the conductive pillar, the polyimide layer, and the reflowed conductive member, coupling the reflowed conductive member to a conductive terminal using a reflow technique, thereby producing a solder layer coupling the conductive pillar to the conductive terminal, and covering the die, the conductive pillar, the solder layer, and the conductive terminal in a molding, the conductive terminal exposed to a surface of the molding. The conductive member may be copper. The upper portion of the conductive pillar may a wider diameter than the base portion in one example such that the conductive pillar has a mushroom shape. The base portion of the conductive pillar may have a wider diameter than the upper portion in another example, and sloped sides on the base portion may extend from the upper portion to the conductive layer. Forming the polyimide layer may include preventing the polyimide layer from extending over the top surface of the conductive pillar due to the shape of the upper portion of the conductive pillar. Alternatively, forming the polyimide layer may include preventing the polyimide layer from extending over the top surface of the conductive pillar due to the shape of the lower portion of the conductive pillar.
While various examples of the present disclosure have been described above, it should be understood that they have been presented by way of example only and not limitation. Numerous changes to the disclosed examples can be made in accordance with the disclosure herein without departing from the spirit or scope of the disclosure. Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims. Thus, the breadth and scope of the present invention should not be limited by any of the examples described above. Rather, the scope of the disclosure should be defined in accordance with the following claims and their equivalents.
