Claims
- 1. A test apparatus for an integrated circuit wafer, comprising:
a motherboard substrate having a bottom surface and a top surface, and a plurality of electrical conductors extending from the bottom surface to the top surface; a probe chip substrate comprising a probe surface and a connector surface, a plurality of probe springs on the probe surface, a plurality of electrical contacts on the connector surface, and a plurality of probe chip electrical connections, wherein each of the probe springs is electrically connected to at least one contact through at least one probe chip electrical connection; at least one intermediate connector located between the motherboard substrate and the probe chip substrate, the intermediate connector comprising at least one electrically conductive connection between each of the plurality of electrical contacts on the probe chip substrate and each of the electrical conductors on the bottom surface of the motherboard substrate; and a probe chip carrier attached in relation to the motherboard substrate, the probe chip carrier comprising a compliant member; wherein the probe chip substrate is supported by the compliant member relative to the motherboard.
- 2. The test apparatus of claim 1, wherein the plurality of probe springs comprise a fixed portion attached to the probe chip substrate and a free portion, initially attached to the probe chip substrate, which upon release, extend away from the probe chip substrate as a result of an inherent stress gradient.
- 3. The test apparatus of claim 2, wherein the plurality of probe springs each comprise a plurality of layers, and wherein the free portions of probe springs extend away upon release from the probe chip substrate as a result of the inherent stress gradient defined between the plurality of layers.
- 4. The test apparatus of claim 2, wherein the plurality of probe springs are sputter formed.
- 5. The test apparatus of claim 2, wherein the plurality of probe springs are plateably formed.
- 6. The test apparatus of claim 2, wherein said plurality of probe springs are photolithographically patterned springs, in which the free portions define a three-dimensional structure.
- 7. The test apparatus of claim 1, wherein at least one of the electrical connections comprises a plurality of electrically conductive vias.
- 8. The test apparatus of claim 1, wherein the compliant member is attached to the connector surface of the probe chip substrate.
- 9. The test apparatus of claim 1, further comprising:
a stiffener plate fixedly attached to the top surface of the motherboard substrate.
- 10. The test apparatus of claim 9, wherein the stiffener plate comprises a rigid material.
- 11. The test apparatus of claim 9, wherein the stiffener plate comprises stainless steel.
- 12. The test apparatus of claim 9, wherein at least one component recess is defined in the stiffener plate proximate the top surface of the motherboard substrate, and wherein the apparatus further comprises:
at least one component extending from the motherboard substrate within the component recess.
- 13. The test apparatus of claim 12, wherein the component is a capacitor.
- 14. The test apparatus of claim 1, wherein the probe chip substrate comprises an inner region and an outer peripheral region, and wherein the compliant member is attached to the peripheral region of the probe chip substrate.
- 15. The test apparatus of claim 1, wherein the probe chip substrate comprises an inner region and an outer peripheral region, and wherein the compliant member is adhesively attached to the peripheral region of the probe chip substrate.
- 16. The test apparatus of claim 1, wherein the compliant member is a film.
- 17. The test apparatus of claim 16, wherein the film comprises polyimide.
- 18. The test apparatus of claim 16, wherein the probe chip comprises an outer periphery, and wherein the film is attached about the outer periphery.
- 19. The test apparatus of claim 1, wherein the compliant member is a screen.
- 20. The test apparatus of claim 1, wherein the compliant member is a mesh.
- 21. The test apparatus of claim 1, wherein the compliant member comprises KAPTON™.
- 22. The test apparatus of claim 1, wherein the intermediate connector comprises an interposer having a first plurality of compliant electrical contacts on a first surface and a second plurality of compliant electrical contacts on a second surface opposite the first surface.
- 23. The test apparatus of claim 1, further comprising:
a permanent electrical interface between the intermediate connector and the motherboard substrate.
- 24. The test apparatus of claim 23, wherein the permanent interface comprises a solder ball array.
- 25. The test apparatus of claim 23, wherein the permanent interface comprises an anisotropic conductive film.
- 26. The test apparatus of claim 23, wherein the permanent interface comprises a plurality of electrically conductive pins.
- 27. The test apparatus of claim 1, further comprising:
at least one standoff fixedly attached to the probe surface of the probe chip substrate.
- 28. The test apparatus of claim 1, further comprising:
at least one standoff fixedly attached to the connector surface of the probe chip substrate.
- 29. The test apparatus of claim 1, further comprising:
at least one passive component incorporated as an assembled component on the probe chip substrate.
- 30. The test apparatus of claim 29, wherein the passive component is mounted on the connector surface of the probe chip substrate.
- 31. The test apparatus of claim 29, wherein the passive component is a capacitor.
- 32. The test apparatus of claim 29, wherein the capacitor is a decoupling capacitor.
- 33. The test apparatus of claim 29, wherein the passive component is a resistor.
- 34. The test apparatus of claim 29, wherein the passive component is an inductor.
- 35. The test apparatus of claim 1, further comprising:
at least one capacitor fabricated on the probe chip substrate.
- 36. The apparatus of claim 1, wherein at least one of the substrates is comprised of silicon, and further comprising:
at least one capacitor fabricated within at least one of the substrates.
- 37. The test apparatus of claim 1, further comprising:
a planarity adjustment mechanism in which the planarity of the probe chip is adjustable relative to the motherboard substrate.
- 38. The test apparatus of claim 1, wherein the intermediate connector comprises a printed wiring board, and wherein the plurality of electrically conductive connections comprise vias having means for electrical connection to the probe chip and means for electrical connection to the motherboard.
- 39. The test apparatus of claim 38, wherein the means for electrical connection to the motherboard comprises an interposer.
- 40. The test apparatus of claim 38, wherein the means for electrical connection to the probe chip comprises an interposer.
- 41. The test apparatus of claim 1, wherein the intermediate connector comprises a Z-block, comprising a vertical translation substrate having a lower surface and an upper surface, and a plurality of electrically conductive connections which extend from the lower surface to the upper surface thereof, each of the electrically conductive connections comprising at least one electrically conductive via.
- 42. The test apparatus of claim 41, further comprising an interposer between the Z-block and the motherboard substrate.
- 43. The test apparatus of claim 41, further comprising an interposer between the Z-block and the probe chip substrate.
- 44. The test apparatus of claim 1, wherein the probe chip substrate comprises a plurality of holes defined therethrough between the probe surface and the connector surface, and wherein each of the plurality of probe chip electrical connections are electrically conductive vias located within each of the plurality of holes in the probe chip substrate.
- 45. The test apparatus of claim 1, wherein the probe chip substrate comprises an electrically insulative material.
- 46. The test apparatus of claim 1, wherein the probe chip substrate comprises a dielectric material.
- 47. The test apparatus of claim 1, wherein the probe chip substrate comprises an electrically conductive material.
- 48. The test apparatus of claim 1, further comprising:
at least one bypass capacitor electrically connected to at least one of the plurality of electrical connections on the probe chip substrate.
- 49. The test apparatus of claim 1, wherein the intermediate connector comprises an electrically conductive pin block having a plurality of holes defined between a lower surface and an upper surface thereof, and wherein the plurality of electrically conductive connections comprise pins extending through the plurality of holes, the pins comprising means for connection to the probe chip and means for connection to the motherboard.
- 50. The test apparatus of claim 49, further comprising:
dielectric within the plurality of holes.
- 51. The test apparatus of claim 49, further comprising:
an electrically conductive ground contact between at least one of the pins and the pin block.
- 52. The test apparatus of claim 49, further comprising:
a zero activation force (ZIF) actuation template located between the metal pin block and the motherboard.
- 53. The test apparatus of claim 49, further comprising:
a lower pin template located on the lower surface of the pin block, in which the pins extend through the lower pin template.
- 54. The test apparatus of claim 53, wherein the lower pin template comprises KAPTON™.
- 55. The test apparatus of claim 49, further comprising:
an upper pin template located on the upper surface of the pin block, in which the pins extend through the upper pin template.
- 56. The test apparatus of claim 55, wherein the upper pin template comprises KAPTON™.
- 57. The test apparatus of claim 49, wherein the means for electrical connection to the probe chip comprises a solder ball array.
- 58. The test apparatus of claim 49, wherein the means for electrical connection to the probe chip comprises solder joints.
- 59. The test apparatus of claim 49, wherein the means for electrical connection to the motherboard comprises a pin grid array.
- 60. The test apparatus of claim 49, wherein the means for electrical connection to the probe chip comprises a plurality of springs.
- 61. The test apparatus of claim 49, wherein the means for electrical connection to the motherboard comprises a pin socket array in the motherboard.
- 62. The test apparatus of claim 49, wherein the means for electrical connection to the motherboard comprises solder joints.
- 63. The test apparatus of claim 49, wherein the means for electrical connection to the motherboard comprises press fit pin connections.
- 64. The test apparatus of claim 1, wherein the motherboard substrate further comprises at least one electrically conducting path with matched impedance.
- 65. The test apparatus of claim 1, wherein the intermediate connector further comprises at least one electrically conducting path with matched impedance.
- 66. The test apparatus of claim 1, wherein the probe chip substrate further comprises at least one electrically conducting path with matched impedance.
- 67. The test apparatus of claim 1, further comprising:
at least one electrically conducting path with matched impedance extending from the top surface of the motherboard substrate to the probe surface of the probe chip substrate.
- 68. A test apparatus for an integrated circuit wafer, the test apparatus connectable to a prober, comprising:
a motherboard substrate having a bottom surface and a top surface, and a plurality of electrical conductors extending from the bottom surface to the top surface; a probe chip substrate having a probe surface and a connector surface, a plurality of probe springs on the probe surface, a plurality of electrical contacts on the connector surface, and a plurality of probe chip electrical connections, wherein each of the probe springs is electrically connected to at least one contact through at least one probe chip electrical connection, wherein the plurality of electrical contacts on the connector surface contact at least one of the plurality of electrical conductors on the bottom surface of the motherboard; and a probe chip carrier attached in relation to the motherboard substrate, the probe chip carrier comprising a compliant member; wherein the probe chip substrate is supported by the compliant member relative to the motherboard.
- 69. The test apparatus of claim 68, wherein the plurality of probe springs comprise a fixed portion attached to the probe chip substrate and a free portion, initially attached to the probe chip substrate, which upon release, extend away from the probe chip substrate as a result of an inherent stress gradient.
- 70. The test apparatus of claim 69, wherein the plurality of probe springs each comprise a plurality of layers, and wherein the free portions of probe springs extend away upon release from the probe chip substrate as a result of the inherent stress gradient defined between the plurality of layers.
- 71. The test apparatus of claim 69, wherein the plurality of probe springs are sputter formed.
- 72. The test apparatus of claim 69, wherein the plurality of probe springs are plateably formed.
- 73. The test apparatus of claim 69, wherein said plurality of probe springs are photolithographically patterned springs, in which the free portions define a three-dimensional structure.
- 74. The test apparatus of claim 68, wherein at least one of the probe chip electrical connections comprises a plurality of electrically conductive vias.
- 75. The test apparatus of claim 68, wherein the compliant member is attached to the connector surface of the probe chip substrate.
- 76. The test apparatus of claim 68, further comprising:
a stiffener plate fixedly attached to the top surface of the motherboard substrate.
- 77. The test apparatus of claim 76, wherein the stiffener plate comprises a rigid material.
- 78. The test apparatus of claim 76, wherein the stiffener plate comprises stainless steel.
- 79. The test apparatus of claim 76, wherein a component recess is defined in the stiffener plate proximate the top surface of the motherboard substrate, and wherein the apparatus further comprises:
a component extending from the motherboard substrate within the component recess.
- 80. The test apparatus of claim 79, wherein the component is a capacitor.
- 81. The test apparatus of claim 68, wherein the probe chip substrate comprises an inner region and an outer peripheral region, and wherein the compliant member is attached to the peripheral region of the probe chip substrate.
- 82. The test apparatus of claim 68, wherein the probe chip substrate comprises an inner region and an outer peripheral region, and wherein the compliant member is adhesively attached to the peripheral region of the probe chip substrate.
- 83. The test apparatus of claim 68, wherein the compliant member is a film.
- 84. The test apparatus of claim 83, wherein the film comprises polyimide.
- 85. The test apparatus of claim 84, wherein the probe chip substrate comprises an outer periphery, and wherein the film is attached about the outer periphery.
- 86. The test apparatus of claim 68, wherein the compliant member is a screen.
- 87. The test apparatus of claim 68, wherein the compliant member is a mesh.
- 88. The test apparatus of claim 68, wherein the compliant member comprises KAPTON™.
- 89. The test apparatus of claim 68, further comprising:
at least one standoff fixedly attached to the probe surface of the probe chip substrate.
- 90. The test apparatus of claim 68, further comprising:
at least one standoff fixedly attached to the connector surface of the probe chip substrate.
- 91. The test apparatus of claim 68, further comprising:
at least one passive component incorporated as an assembled component on the probe chip substrate.
- 92. The test apparatus of claim 91, wherein the passive component is mounted on the connector surface of the probe chip substrate.
- 93. The test apparatus of claim 91, wherein the passive component is a capacitor.
- 94. The test apparatus of claim 91, wherein the capacitor is a decoupling capacitor.
- 95. The test apparatus of claim 91, wherein the passive component is a resistor.
- 96. The test apparatus of claim 91, wherein the passive component is an inductor.
- 97. The test apparatus of claim 68, further comprising:
at least one capacitor fabricated on the probe chip substrate.
- 98. The apparatus of claim 68, wherein at least one of the substrates is comprised of silicon, and further comprising:
at least one capacitor fabricated within at least one of the substrates.
- 99. The test apparatus of claim 68, further comprising:
a planarity adjustment mechanism in which the planarity of the probe chip substrate is adjustable relative to the prober.
- 100. The test apparatus of claim 68, wherein the probe chip substrate includes a plurality of holes defined therethrough between the probe surface and the connector surface, and wherein each of the probe chip electrical connections comprise electrically conductive vias located within each of the plurality of holes in the probe chip substrate.
- 101. The test apparatus of claim 68, wherein the probe chip substrate comprises an electrically insulative material.
- 102. The test apparatus of claim 68, wherein the probe chip substrate comprises a dielectric material.
- 103. The test apparatus of claim 68, wherein the probe chip substrate comprises an electrically conductive material.
- 104. The test apparatus of claim 68, further comprising:
at least one bypass capacitor electrically connected to at least one of the plurality of electrical connections on the probe chip substrate.
- 105. The test apparatus of claim 68, wherein the motherboard substrate further comprises at least one electrically conducting path with matched impedance.
- 106. The test apparatus of claim 68, wherein the probe chip substrate further comprises at least one electrically conducting path with matched impedance.
- 107. The test apparatus of claim 68, further comprising:
at least one electrically conducting path with matched impedance extending from the top surface of the motherboard substrate to the probe surface of the probe chip substrate.
- 108. The test apparatus of claim 68, further comprising:
at least one electrically conducting path with matched impedance extending from the top surface of the motherboard substrate to the probe surface of the probe chip substrate.
- 109. A decal assembly process, comprising the steps of:
providing a probe chip substrate having an outer periphery and an inner region, and having a probe surface and a connector surface, a plurality of probe springs on the probe surface within the inner region, a plurality of electrical contacts on the connector surface within the inner region, wherein each of the probe springs is electrically connected to at least one electrical contact; providing a compliant substrate having a defined attachment region; and attaching the defined connection region of the compliant substrate to the outer periphery of the probe chip substrate.
- 110. A decal assembly process, comprising the steps of:
providing a probe chip substrate having an outer periphery and an inner region, and having a probe surface and a connector surface, a plurality of probe springs on the probe surface within the inner region, and a plurality of electrical contacts on the connector surface within the inner region, wherein each of the probe springs is electrically connected to at least one electrical contact; applying an adhesive to the outer periphery of the connector surface of the probe chip substrate; providing a mounting ring having an opening defined there through, the opening larger than the outer periphery of the probe chip substrate; attaching a compliant member across the mounting ring; adhesively attaching compliant member to the applied adhesive on the outer periphery of the probe chip substrate.
- 111. A package for connection to an integrated circuit device, comprising:
a package substrate having a first surface and a second surface; a plurality of electrical connections extending through the package substrate between the first surface and the second surface; and a plurality of probe springs located on the first surface and extending from the electrical connections, the plurality of probe springs being at least temporarily connectable to at least one integrated circuit device.
- 112. The package of claim 111, wherein the plurality of probe springs comprise a fixed portion attached to the probe chip substrate and a free portion, initially attached to the package substrate, which upon release, extend away from the package substrate as a result of an inherent stress gradient.
- 113. The package of claim 112, wherein the plurality of probe springs each comprise a plurality of layers, and wherein the free portions of probe springs extend away upon release from the package substrate as a result of the inherent stress gradient defined between the plurality of layers.
- 114. The package of claim 112, wherein the plurality of probe springs are sputter formed.
- 115. The package of claim 112, wherein the plurality of probe springs are plateably formed.
- 116. The package of claim 111, wherein the plurality of probe springs are photolithographically patterned springs, in which the free portions define a three-dimensional structure.
- 117. The package of claim 111, further comprising;
a permanent connection between the package and at least an integrated circuit device based upon a verification that the integrated circuit is good.
- 118. The package of claim 117, wherein the permanent connection comprises solder.
- 119. The package of claim 117, wherein the permanent connection comprises electrically conductive epoxy.
- 120. The package of claim 117, wherein the permanent connection comprises anisotropic conductive film.
- 121. The package of claim 117, wherein at least one integrated circuit devices is permanently connected to the probe springs on the first surface of the package substrate.
- 122. The package of claim 111, wherein the plurality of electrical connections further comprise pads on the second surface of the package substrate.
- 123. The package of claim 111, further comprising;
a plurality solder balls on the second surface of the package, wherein each of the plurality of electrical connections is electrically connected to at least one of the solder balls.
- 124. The package of claim 111, further comprising;
a plurality electrically conductive pins on the second surface of the package, wherein each of the plurality of electrical connections is electrically connected to at least one of the electrically conductive pins.
- 125. The package of claim 111, wherein at least one of the electrical connections comprises an impedance matched RF signal path.
- 126. The package of claim 111, further comprising:
at least one passive device located on at least one surface of the package substrate.
- 127. The package of claim 126, wherein the passive device is a capacitor.
- 128. The package of claim 126, wherein the passive device is a resistor.
- 129. The package of claim 126, wherein the passive device is an inductor.
- 130. The package of claim 111, further comprising:
at least one capacitor within the second surface of the package substrate.
- 131. The package of claim 111, further comprising:
a ground return path within the package substrate below the probe springs, such that when at least one of the integrated circuit devices is put in contact with the substrate the electrical contacts minimize impedance mismatch from low to high frequencies.
- 132. The package of claim 111, further comprising:
a vacuum pull down port defined through the package substrate from the first surface to the second surface under at least one of the integrated circuits.
- 133. The package of claim 111, further comprising:
a lid for holding the integrated circuits in contact with the package.
- 134. The package substrate of claim 111, further comprising:
a second substrate comprising a third surface and fourth surface, said second substrate providing at least one electrical connection extending from the package substrate to the fourth surface of the second substrate, wherein the third surface is adjacent to the first surface of the package substrate, and the said plurality of probe springs are instead located on the fourth surface, said second substrate optionally comprising a plurality of build up layers that are formed on the first surface of the package substrate.
- 135. The package of claim 134, wherein the second substrate comprises at least one routing layer.
- 136. A method for developing a probe assembly for connection to at least one device on a wafer, comprising the steps of:
providing a motherboard substrate having a bottom surface and a top surface, and a plurality of electrical conductors extending from the top surface to the bottom surface; providing at least one standard intermediate connector having an upper interface and a lower interface, the upper surface locatable proximate to the bottom surface of the motherboard substrate, the intermediate connector comprising at least one electrically conductive connection between the upper interface and the lower interface corresponding to each of the electrical conductors on the bottom surface of the motherboard substrate; providing a probe chip substrate design comprising a connector surface, a probe surface opposite the connector surface, and a plurality of contacts on the connector surface arranged in a fixed layout, the connector surface locatable proximate to the lower surface of the intermediate connector; receiving an interconnection specification for the at least one device on the wafer, the interconnection specification comprising electrical interconnection locations for the at least one device; and producing a probe chip substrate, wherein the substrate is based upon the probe chip substrate design, wherein the probe chip substrate further comprises a plurality of probe springs on the probe surface corresponding to the interconnection locations on the wafer, and wherein each of the probe springs is electrically connected to at least one contact on the connector surface.
- 137. The method of claim 136, wherein the plurality of probe springs comprise a fixed portion attached to the probe chip substrate and a free portion, initially attached to the probe chip substrate, which upon release, extend away from the probe chip substrate as a result of an inherent stress gradient.
- 138. The method of claim 137, wherein the plurality of probe springs each comprise a plurality of layers, and wherein the free portions of probe springs extend away upon release from the probe chip substrate as a result of the inherent stress gradient defined between the plurality of layers.
- 139. The method of claim 137, wherein the plurality of probe springs are sputter formed.
- 140. The method of claim 137, wherein the plurality of probe springs are plateably formed.
- 141. The method of claim 137, wherein said plurality of probe springs are photolithographically patterned springs, in which the free portions define a three-dimensional structure.
- 142. The method of claim 141, further comprising the step of:
producing the probe assembly comprising the motherboard substrate electrically interconnected to the probe chip assembly through the intermediate connector.
- 143. The method of claim 142, further comprising the step of:
establishing a compliant member about the periphery of the probe chip substrate; and compliantly affixing the probe chip substrate to the probe assembly with the compliant member.
- 144. The method of claim 141, wherein the intermediate connector comprises a Z-block connector, comprising a vertical translation substrate having a lower surface and an upper surface, and a plurality of electrically conductive connections which extend from the lower surface to the upper surface thereof, each of the electrically conductive connections comprising at least one electrically conductive via.
- 145. A probe assembly structure for electrical connection to interconnection locations on a wafer, comprising:
a master slice comprising at least one substrate having standardized electrical connections; and at least one customized interface connectable to the master slice, the customized interface comprising a plurality of probe springs corresponding to the interconnection locations, and wherein each of the probe springs is electrically connected to at least one standardized electrical connection on the master slice.
- 146. The probe assembly structure of claim 145, wherein the plurality of probe springs comprise a fixed portion attached to the probe chip substrate and a free portion, initially attached to the probe chip substrate, which upon release, extend away from the probe chip substrate as a result of an inherent stress gradient.
- 147. The probe assembly structure of claim 146, wherein the plurality of probe springs each comprise a plurality of layers, and wherein the free portions of probe springs extend away upon release from the probe chip substrate as a result of the inherent stress gradient defined between the plurality of layers.
- 148. The probe assembly structure of claim 146, wherein the plurality of probe springs are sputter formed.
- 149. The probe assembly structure of claim 146, wherein the plurality of probe springs are plateably formed.
- 150. The probe assembly structure of claim 146, wherein said plurality of probe springs are photolithographically patterned springs, in which the free portions define a three-dimensional structure.
- 151. A method for developing a probe assembly for connection to at least one device on a wafer, comprising the steps of:
providing a motherboard substrate having a bottom surface and a top surface, and a plurality of electrical conductors extending from the top surface to the bottom surface; providing a probe chip substrate design comprising a connector surface and a probe surface opposite the connector surface, and a plurality of contacts on the connector substrate arranged in a fixed layout, the connector surface locatable proximate to the lower surface of the motherboard substrate; receiving an interconnection specification for the at least one device on the wafer, the interconnection specification comprising electrical interconnection locations; and producing a probe chip substrate, wherein the substrate is based upon the probe chip substrate design, wherein the probe chip substrate further comprises a plurality of probe springs on the probe surface corresponding to the interconnections on the wafer, and wherein each of the probe springs is electrically connected to at least one contact on the connector surface.
- 152. The method of claim 151, wherein the plurality of probe springs comprise a fixed portion attached to the probe chip substrate and a free portion, initially attached to the probe chip substrate, which upon release, extend away from the probe chip substrate as a result of an inherent stress gradient.
- 153. The method of claim 152, wherein the plurality of probe springs each comprise a plurality of layers, and wherein the free portions of probe springs extend away upon release from the probe chip substrate as a result of the inherent stress gradient defined between the plurality of layers.
- 154. The method of claim 152, wherein the plurality of probe springs are sputter formed.
- 155. The method of claim 152, wherein the plurality of probe springs are plateably formed.
- 156. The method of claim 152, wherein said plurality of probe springs are photolithographically patterned springs, in which the free portions define a three-dimensional structure.
- 157. The method of claim 151, further comprising the step of:
producing the probe assembly comprising the motherboard substrate electrically interconnected to the connector surface of the probe chip substrate.
- 158. The method of claim 157, further comprising the step of:
establishing a compliant member about the periphery of the probe chip substrate; and compliantly affixing the probe chip substrate to the probe assembly with the compliant member.
- 159. An interposer, comprising:
a compliant membrane comprising an inner region and an outer peripheral region on either side of said inner region, the inner region defining an array of apertures through the membrane; at least one pair of electrically interconnected, compliant probe springs, each comprising a planar base region and a nonplanar region; wherein said at least one pair of compliant probe springs are attached to the compliant membrane at the planar base region thereof; and wherein the non-planar regions of the probe spring pair extend from each other in substantially opposite directions though corresponding apertures in the compliant membrane.
- 160. The interposer of claim 159, wherein the non-planar regions of the said at least one pair of probe springs, are initially attached to a substrate, and upon release said non-planar regions extend away from the substrate as a result of an inherent stress gradient in said probe springs.
- 161. The interposer of claim 159, wherein the said at least one pair of probe springs each comprise a plurality of layers, and wherein the non-planar regions, initially attached to a substrate, extend away upon release from the probe chip substrate as a result of the inherent stress gradient defined between the plurality of layers.
- 162. The interposer of claim 159, wherein the at least one pair of compliant probe springs are sputter formed.
- 163. The interposer of claim 159, wherein the at least one pair of compliant probe springs are plateably formed.
- 164. The interposer of claim 159, wherein the compliant membrane comprises polyimide.
- 165. The interposer of claim 159, further comprising;
a support ring attached to the peripheral region of the compliant membrane.
- 166. The claim of 165, wherein the support ring holds the compliant membrane in tension.
- 167. The claim of 165, wherein the support ring comprises stainless steel.
- 168. The interposer of claim 159, further comprising:
at least one plating layer on at least the non planar region of any of the compliant probe springs.
- 169. An interposer, comprising:
an interposer substrate having a first surface and a second surface; at least one electrically conductive via extending through the interposer substrate from the first surface to the second surface; at least one electrically conductive first compliant probe spring formed on the first surface of the interposer substrate comprising a first plurality of layers formed with different stress levels, which layers retain such stress until lifted, said probe spring comprising a planar region and a nonplanar region, the non-planar region formed from an inherent stress gradient within said layers; at least one electrically conductive second compliant probe spring located on a second surface of the interposer substrate, the second compliant probe spring comprising a second plurality of layers formed with different stress levels, which layers retain such stress until lifted, said probe spring comprising a planar region and a nonplanar region, the non-planar region formed from an inherent stress gradient within said layers; and at least one redundant electrically conductive element; wherein the first compliant probe spring is in electrical contact with the second compliant probe spring through at least one of the electrically conductive vias.
- 170. The interposer of claim 169, said first compliant probe spring and said second compliant probe spring further comprising:
a fixed portion attached to the interposer substrate and a free portion, initially attached to the interposer substrate, which upon release, extends away from the interposer substrate as a result of said inherent stress gradient.
- 171. The interposer of claim 170, wherein the said first compliant probe spring and said second compliant probe spring each comprise a plurality of layers, and wherein the free portions of said probe springs extend away from said substrate upon release from the probe chip substrate as a result of the inherent stress gradient defined between the plurality of layers.
- 172. The interposer of claim 170, wherein said first compliant probe spring and said second compliant probe spring are sputter formed.
- 173. The interposer of claim 170, wherein said first compliant probe spring and said second compliant probe spring are plateably formed.
- 174. The interposer of claim 169, wherein said first compliant probe spring and said second compliant probe spring are photolithographically patterned springs, in which the free portions define a three-dimensional structure.
- 175. The interposer of claim 169, wherein the redundant electrically conductive element comprises a redundant first compliant probe spring.
- 176. The interposer of claim 169, wherein the redundant electrically conductive element comprises a redundant second compliant probe spring.
- 177. The interposer of claim 169, wherein the redundant electrically conductive element comprises a redundant via.
- 178. The interposer of claim 169, further comprising:
at least one capacitor electrically connected between at least two of the first compliant probe springs.
- 179. A process of forming an interposer, comprising the steps of:
providing a substrate; forming a first release layer on the substrate; forming a first plurality of electrically conducting stress layers on the first release layer having an inherent stress gradient comprising a downward peeling stress; selectively forming a second release layer over the first plurality of stress layers; forming a second plurality of electrically conducting stress layers on the second release layer having an inherent stress gradient comprising an upward peeling stress; patterning at least one finger region in the first plurality of stress layers and the overlying second plurality of stress layers; selectively forming a compliant membrane having an inner region and a peripheral region, the inner region comprising an array of through holes surrounded by non-perforated solid portion, wherein the non-perforated solid portion covering a portion of the finger region at one end, and the through hole portion is positioned over the remaining portion of the finger region; a rigid support ring is attached to the peripheral region of the compliant membrane, holding the compliant membrane in tension; etching the release layers; wherein said finger region defines an opening through which substantially opposed, electrically interconnected compliant probe springs project.
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This Application is a Continuation In Part of U.S. patent application Ser. No. 09/980,040, entitled Construction Structures and Manufacturing Processes for Integrated Circuit Wafer Probe Card Assemblies, US Filing Date Nov. 27, 2001, which claims priority from PCT Patent Application Serial No. PCT/US00/14164, entitled Construction Structures and Manufacturing Processes for Integrated Circuit Wafer Probe Card Assemblies, US Filing Date May 23, 2000.
Continuation in Parts (1)
|
Number |
Date |
Country |
Parent |
09980040 |
Nov 2001 |
US |
Child |
10178103 |
Jun 2002 |
US |