Patent Application
20210082852
Embodiments of the present disclosure generally relate to the field of package assemblies, and in particular package assemblies that include plated bumps.
Continued reduction in end product size of mobile electronic devices such as smart phones and ultrabooks is a driving force for the development of reduced-size system-in-package components that include increased bump density.
Embodiments of the present disclosure may generally relate to systems, apparatus, and/or processes directed to manufacturing a package having a substrate with a first side and a second side opposite the first side, where a copper layer is coupled with a first region of the first side of the substrate and includes a plurality of bumps coupled with the first region of the first side of the substrate where one or more second regions on the first side of the substrate are not coupled with the copper layer, and where a layout of the one or more second regions on the first side of the substrate is to vary a growth, respectively, of each of the plurality of bumps during a plating process by modifying a local copper density of each of the plurality of bumps.
In order to increase communication bandwidth and reduce silicon area, it may be desirable to scale the bump pitch and reduce bump thickness variation in future architectures of chips and packages. For example, for EMIB bridge dies, it may be desirable to scale the bump pitch from 55 μm to 45 μm, and further to less than 30 μm. In addition, to meet projected I/O density requirements, tighter tolerance of rBTV may be required of a first level interconnect (FLI) for a die attach assembly process, for example attaching by thermal compression bonding. In addition, maintaining a bump thickness variation lower than 10 μm for assembly interactions may be desirable for future generations of package technologies.
Legacy implementations are not able to reliably approach these levels of rBTV tolerances. For example, a legacy multilayer organic substrate may have a thickness variation of greater than 40 μm even before reaching a final layer. Legacy solutions that use lithography or laser processes to control solder resist openings (SRO)/dry-film resist opening (DFRO) sizes, and subsequent bump volume and height, lack the ability to accommodate different bump volumes without multiple, expensive process techniques.
With legacy implementations, even on a flat polished surface (e.g., glass), it is very challenging to achieve uniform plated copper or tin bump height uniformity in the FLI due to the nature of the variation from via recess and metal density differences between regions with different bump pitches on the FLI layer. Furthermore, future bridging architectures, such as EMIB, will put more reliability requirements on packages to enable connection of modular dies to meet the high bandwidth die-to-die communication connection needs. This will not only drive the need for a significant decrease in rBTV at finer pitches, but also will become a significant cost driver.
Legacy approaches to meet the stringent rBTV requirements for next generation EMIB and future die tiling applications include build-up layer chemical and mechanical polishing (CMP) planarization, advanced lamination technologies, FLI layer planarization, and plating uniformity improvement. Build-up layer planarization and advanced lamination technologies are costly processes, and may require significant capital investments. FLI layer CMP planarization may be used for plated copper bumps. However, for plated solder bumps, no existing planarization slurries are currently available. FLI plating uniformity improvement is limited by the large panel size form factor as well as the small vs. large SRO pad size-induced plating height limitations post reflow.
Embodiments described herein may include use of sacrificial polymers to support temporary copper dummification, or removal areas, to improve FLI plating uniformity. These sacrificial polymers are robust enough to survive the harsh, alkaline baths encountered in backend plating (as opposed to traditional DFRs which are designed to develop or strip away in alkaline solutions, but thermally decompose under high temperatures (250-300 degrees C.)), and are photo-definable. These qualities make these sacrificial polymers useful for selective dummification as well as a number of other applications in semiconductor packaging. Embodiments described herein may modulate the height of fabricated bumps without the need for extra lithography or wet techniques. Implementation of embodiments described herein may reduce the chance for yield loss by bump misalignment, thus resulting in tighter bump tolerances and ultimately higher performing products.
In the following detailed description, reference is made to the accompanying drawings which form a part hereof, wherein like numerals designate like parts throughout, and in which is shown by way of illustration embodiments in which the subject matter of the present disclosure may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense, and the scope of embodiments is defined by the appended claims and their equivalents.
For the purposes of the present disclosure, the phrase “A and/or B” means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).
The description may use perspective-based descriptions such as top/bottom, in/out, over/under, and the like. Such descriptions are merely used to facilitate the discussion and are not intended to restrict the application of embodiments described herein to any particular orientation.
The description may use the phrases “in an embodiment,” or “in embodiments,” which may each refer to one or more of the same or different embodiments. Furthermore, the terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present disclosure, are synonymous.
The term “coupled with,” along with its derivatives, may be used herein. “Coupled” may mean one or more of the following. “Coupled” may mean that two or more elements are in direct physical or electrical contact. However, “coupled” may also mean that two or more elements indirectly contact each other, but yet still cooperate or interact with each other, and may mean that one or more other elements are coupled or connected between the elements that are said to be coupled with each other. The term “directly coupled” may mean that two or more elements are in direct contact.
Various operations may be described as multiple discrete operations in turn, in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent.
As used herein, the term “module” may refer to, be part of, or include an ASIC, an electronic circuit, a processor (shared, dedicated, or group) and/or memory (shared, dedicated, or group) that execute one or more software or firmware programs, a combinational logic circuit, and/or other suitable components that provide the described functionality.
Various Figures herein may depict one or more layers of one or more package assemblies. The layers depicted herein are depicted as examples of relative positions of the layers of the different package assemblies. The layers are depicted for the purposes of explanation, and are not drawn to scale. Therefore, comparative sizes of layers should not be assumed from the Figures, and sizes, thicknesses, or dimensions may be assumed for some embodiments only where specifically indicated or discussed.
Diagram 500b shows an output of the simulation that illustrates the effect of electrolytic plating with copper shielding on the border. As a result, in
At block 602, the process may include applying a layer of copper to a portion of the side of a substrate. In embodiments, the layer of copper may correspond to copper layer 328 of
At block 604, the process may further include removing one or more regions of the layer of copper. In embodiments, the regions of copper to be removed may correspond to the region of copper proximate to sacrificial polymer 326a, 326b, 326c of
At block 606, the process may further include applying a plating process to a remaining layer of copper to grow a plurality of bumps coupled with the remaining layer of copper, wherein a layout of the removed one or more regions is to vary a growth, respectively, of each of a plurality of bumps coupled with the copper layer during the plating process by modifying a local copper density of each of the plurality of bumps. In embodiments, the plating process may be similar to the plating process described at block 604 after a solder resist mask, such as mask 340 of
In an embodiment, the electronic system 700 is a computer system that includes a system bus 720 to electrically couple the various components of the electronic system 700. The system bus 720 is a single bus or any combination of busses according to various embodiments. The electronic system 700 includes a voltage source 730 that provides power to the integrated circuit 710. In some embodiments, the voltage source 730 supplies current to the integrated circuit 710 through the system bus 720.
The integrated circuit 710 is electrically coupled to the system bus 720 and includes any circuit, or combination of circuits according to an embodiment. In an embodiment, the integrated circuit 710 includes a processor 712 that can be of any type. As used herein, the processor 712 may mean any type of circuit such as, but not limited to, a microprocessor, a microcontroller, a graphics processor, a digital signal processor, or another processor. In an embodiment, the processor 712 includes, or is coupled with, copperless regions to control plating growth, as disclosed herein. In an embodiment, SRAM embodiments are found in memory caches of the processor. Other types of circuits that can be included in the integrated circuit 710 are a custom circuit or an application-specific integrated circuit (ASIC), such as a communications circuit 714 for use in wireless devices such as cellular telephones, smart phones, pagers, portable computers, two-way radios, and similar electronic systems, or a communications circuit for servers. In an embodiment, the integrated circuit 710 includes on-die memory 716 such as static random-access memory (SRAM). In an embodiment, the integrated circuit 710 includes embedded on-die memory 716 such as embedded dynamic random-access memory (eDRAM).
In an embodiment, the integrated circuit 710 is complemented with a subsequent integrated circuit 711. Useful embodiments include a dual processor 713 and a dual communications circuit 715 and dual on-die memory 717 such as SRAM. In an embodiment, the dual integrated circuit 710 includes embedded on-die memory 717 such as eDRAM.
In an embodiment, the electronic system 700 also includes an external memory 740 that in turn may include one or more memory elements suitable to the particular application, such as a main memory 742 in the form of RAM, one or more hard drives 744, and/or one or more drives that handle removable media 746, such as diskettes, compact disks (CDs), digital variable disks (DVDs), flash memory drives, and other removable media known in the art. The external memory 740 may also be embedded memory 748 such as the first die in a die stack, according to an embodiment.
In an embodiment, the electronic system 700 also includes a display device 750, an audio output 760. In an embodiment, the electronic system 700 includes an input device such as a controller 770 that may be a keyboard, mouse, trackball, game controller, microphone, voice-recognition device, or any other input device that inputs information into the electronic system 700. In an embodiment, an input device 770 is a camera. In an embodiment, an input device 770 is a digital sound recorder. In an embodiment, an input device 770 is a camera and a digital sound recorder.
As shown herein, the integrated circuit 710 can be implemented in a number of different embodiments, including a package substrate having copperless regions to control plating growth, according to any of the several disclosed embodiments and their equivalents, an electronic system, a computer system, one or more methods of fabricating an integrated circuit, and one or more methods of fabricating an electronic assembly that includes a package substrate having copperless regions to control plating growth, according to any of the several disclosed embodiments as set forth herein in the various embodiments and their art-recognized equivalents. The elements, materials, geometries, dimensions, and sequence of operations can all be varied to suit particular I/O coupling requirements including array contact count, array contact configuration for a microelectronic die embedded in a processor mounting substrate according to any of the several disclosed package substrates having copperless regions to control plating growth embodiments and their equivalents. A foundation substrate may be included, as represented by the dashed line of
The following paragraphs describe examples of various embodiments.
Example 1 includes a package comprising: a substrate with a first side and a second side opposite the first side; a copper layer coupled with a first region of the first side of the substrate; a plurality of bumps coupled with the first region of the first side of the substrate; one or more second regions on the first side of the substrate not coupled with a copper layer; and wherein a layout of the one or more second regions on the first side of the substrate is to vary a growth, respectively, of each of the plurality of bumps during a plating process by modifying a density of copper, respectively, proximate to each of the plurality of bumps.
Example 2 includes the package of example 1, wherein the one or more second regions on the first side of the substrate further includes: one or more volumes, respectively, proximate to the one or more second regions that extend into the substrate.
Example 3 includes the package of example 2, wherein the one or more volumes includes a fill material.
Example 4 includes the package of example 3, wherein the fill material includes a polymer.
Example 5 includes the package of example 3, wherein the fill material and a material of the substrate are different materials.
Example 6 includes the package of example 1, wherein each bump of the plurality of bumps is at substantially a same height with respect to a plane of the substrate.
Example 7 includes the package of example 1, wherein each bump in a first set of the plurality of bumps is at substantially a first height with respect to a plane of the substrate, and wherein each bump in a second set of the plurality of bumps is at substantially a second height with respect to the plane.
Example 8 includes the package of example 7, further comprising a first die coupled with the first set of the plurality of bumps; and a second die coupled with the second set of the plurality of bumps.
Example 9 includes the package of any one of examples 1-8, wherein the plating process is a copper plating process.
Example 10 is a process, comprising: applying a layer of copper to a portion of a side of a substrate; removing one or more regions of the layer of copper; and applying a plating process to a remaining layer of copper to grow a plurality of bumps coupled with the remaining layer of copper, wherein a layout of the removed one or more regions is to vary a growth, respectively, of each of the plurality of bumps coupled with the remaining layer of copper during the plating process by modifying a density of copper, respectively, proximate to each of the plurality of bumps.
Example 11 includes the process of example 10, further comprising, before applying the layer of copper: removing one or more volumes, respectively, of a material of the substrate proximate to the one or more regions of the layer of copper to create one or more cavities in the substrate; and filling the one or more cavities with a polymer.
Example 12 includes the process of example 11, wherein removing the one or more volumes of the material of the substrate further includes a selected one of skiving or drilling the one or more volumes of the material of the substrate.
Example 13 includes the process of example 10, wherein removing one or more regions of the layer of copper further includes heating the substrate to cause a polymer coupled with the one or more regions of the layer of copper to degass.
Example 14 includes the process of any one of examples 10-13, wherein the layout is determined based upon computer simulation.
Example 15 is a system, comprising: a circuit board; a package coupled with the circuit board, the package including: a substrate with a first side and a second side opposite the first side; a copper layer coupled with a first region of the first side of the substrate; a plurality of bumps coupled with the first region of the first side of the substrate; one or more second regions on the first side of the substrate not coupled with a copper layer; and wherein a layout of the one or more second regions on the first side of the substrate is to vary a growth, respectively, of each of the plurality of bumps during a plating process by modifying a density of copper, respectively, proximate to each of the plurality of bumps.
Example 16 includes the system of example 15, wherein the one or more second regions on the first side of the substrate further includes: one or more volumes, respectively, proximate to the one or more second regions and extending into the substrate.
Example 17 includes the system of example 16, wherein the one or more volumes includes a polymer.
Example 18 includes the system of any one of examples 16-17, wherein each bump of the plurality of bumps is at substantially a same height with respect to a plane.
Example 19 includes the system of example 18, wherein each bump in a first set of the plurality of bumps is at substantially a first height with respect to a plane, and wherein each bump in a second set of the plurality of bumps is at substantially a second height with respect to the plane.
Example 20 includes the system of example 19, further comprising a first die coupled with the first set of the plurality of bumps; and a second die coupled with the second set of the plurality of bumps.
Various embodiments may include any suitable combination of the above-described embodiments including alternative (or) embodiments of embodiments that are described in conjunctive form (and) above (e.g., the “and” may be “and/or”). Furthermore, some embodiments may include one or more articles of manufacture (e.g., non-transitory computer-readable media) having instructions, stored thereon, that when executed result in actions of any of the above-described embodiments. Moreover, some embodiments may include apparatuses or systems having any suitable means for carrying out the various operations of the above-described embodiments.
The above description of illustrated embodiments, including what is described in the Abstract, is not intended to be exhaustive or to limit embodiments to the precise forms disclosed. While specific embodiments are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the embodiments, as those skilled in the relevant art will recognize.
These modifications may be made to the embodiments in light of the above detailed description. The terms used in the following claims should not be construed to limit the embodiments to the specific implementations disclosed in the specification and the claims. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.
