Patent Application
20100073894
The disclosed embodiments of the invention relate generally to packages for microelectronic devices, and relate more particularly to coreless substrates for such packages and as well as to methods for manufacturing them.
Microelectronic device performance frequently depends upon, or is enhanced by, the use of capacitors. The location of such capacitors in relation to the microelectronic device can also be an important parameter affecting performance. Thus, for example, many microelectronic packages are outfitted with “land side” and/or “die side” capacitors: capacitors that are located, respectively, on the land side (sometimes called the bottom side) or the die side (sometimes called the top side) of the package. In addition to capacitors, it is also desirable to place test pads on the package for the purpose of testing electrical performance and/or the functionality of the part and of having the ability to debug the part.
However, existing microelectronic packages are characterized by large top side keep out zones, i.e., package areas that, because of processing or design requirements, cannot accept capacitors, test pads, or any other components. Often the keep out zones are occupied by an overmold or a stiffening material that is used to strengthen the package. This is especially true for packages having coreless substrates which, because they lack the stability that a substrate core would provide, must be strengthened by other means in order to avoid warpage and other deformation that would, for example, prevent the package from being reflowed to a motherboard. In this and similar scenarios top side test pads and die side capacitors cannot be used unless the package form factor grows to make additional space for them, as happens, for example, when test pads are taken to bottom side balls or lands. Such larger package form factors are themselves an undesirable result but also of concern is the fact that bottom side test pads become inaccessible once the package is reflowed to a motherboard is or otherwise permanently attached to a next-level component. Furthermore, as device and package sizes shrink, reducing package standoffs, even the capacitors placed in a bottom side package cavity are affected in that low profile components such as extremely low profile (XLP) capacitors and advanced land side capacitors (ALSCs) must be used. Among other drawbacks, these have reduced capacitance values and are very expensive.
The disclosed embodiments will be better understood from a reading of the following detailed description, taken in conjunction with the accompanying figures in the drawings in which:
For simplicity and clarity of illustration, the drawing figures illustrate the general manner of construction, and descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the discussion of the described embodiments of the invention. Additionally, elements in the drawing figures are not necessarily drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve understanding of embodiments of the present invention. The same reference numerals in different figures denote the same elements, while similar reference numerals may, but do not necessarily, denote similar elements.
The terms “first,” “second,” “third,” “fourth,” and the like in the description and in the claims, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in sequences other than those illustrated or otherwise described herein. Similarly, if a method is described herein as comprising a series of steps, the order of such steps as presented herein is not necessarily the only order in which such steps may be performed, and certain of the stated steps may possibly be omitted and/or certain other steps not described herein may possibly be added to the method. Furthermore, the terms “comprise,” “include,” “have,” and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements is not necessarily limited to those elements, but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.
The terms “left,” “right,” “front,” “back,”“top,” “bottom,” “over,” “under,” and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein. The term “coupled,” as used herein, is defined as directly or indirectly connected in an electrical or non-electrical manner. Objects described herein as being “adjacent to” each other may be in physical contact with each other, in close proximity to each other, or in the same general region or area as each other, as appropriate for the context in which the phrase is used. Occurrences of the phrase “in one embodiment” herein do not necessarily all refer to the same embodiment.
In one embodiment of the invention, a coreless substrate comprises a stiffener material having a plated via formed therein, an electrically insulating material above the stiffener material, and an electrically conductive material in the electrically insulating material. In the same or another embodiment, a package for a microelectronic device comprises a stiffener material layer having plated vias formed therein and further having a recess therein, build-up layers over the stiffener material layer, and a die attached over the build-up layers. The stiffener material layer and the build-up layers form a coreless substrate of the package. The coreless substrate has a surface, and the die covers less than all of the surface of the coreless substrate such that the surface has at least one exposed region.
Embodiments of the invention allow for the placement of standard land side capacitors in a substrate cavity for better power delivery performance. Furthermore, embodiments of the invention provide for smaller coreless package form factors due to the removal of top side keep out zones. The removal of such keep out zones provides a bare substrate top side on which to place discrete components and/or test pads that would otherwise be covered up by overmold or stiffeners. These substrates can be stiff enough to either be unit or strip processed, leading to reductions in both assembly cost and package form factor.
Referring now to the drawings,
As an example, plated via 120 can be lined (plated) with copper or another suitable electrically conductive material. Electrically conductive material 140 could also be copper or the like. Coreless substrate 100 further comprises an electrically insulating layer 160 over electrically insulating material 130. As an example, electrically insulating layer 160 can be a soldermask layer.
Package 200 further comprises a die 370 attached over build-up layers 350. As illustrated, stiffener material layer 215, build-up layers 350, and electrically insulating layer 360 form a coreless substrate 380 of package 200. Coreless substrate 380 has a surface 381, and die 370 covers less than all of surface 381 of coreless substrate 380 such that surface 381 has at least one exposed region 382. As explained above, exposed region 382 is made possible because the stiffener material on the land side of the package provides the package with sufficient stiffness and strength such that no additional stiffener, overmold, or other strengthening materials are needed on the die side of the package. This leaves a certain portion of the substrate surface exposed, open, and available for the placement of one or more desired components, as illustrated.
Die 370 is attached to coreless substrate 380 with an epoxy 390 or a similar adhesive material. Solder bumps 375 electrically connect die 370 to electrically conductive material 240. Solder balls 395 provide a means to attach package 200 to a next-level component such as a motherboard or the like.
In the illustrated embodiment, package 200 comprises capacitors 325 in recess 218. As explained above, the configuration of package 200 is such that capacitors 325 may be standard or low profile capacitors rather than ALSCs or XLP capacitors, and their placement in recess 218 enhances the power delivery performance of package 200. The standard or low profile capacitors are also less expensive than ALSCs or XLP capacitors. It should be noted that in the interest of clarity, capacitors 325 are omitted from
A step 410 of method 400 is to provide a preliminary structure comprising a core material coated on two opposing sides with an electrically conductive film. As an example, the preliminary structure can be similar to a preliminary structure 500 that is first shown in
As illustrated in
A step 420 of method 400 is to form raised or built-up areas of a first electrically conductive material on the electrically conductive film. In one embodiment, the first electrically conductive material can be copper or a similar material. Accordingly, the raised areas of electrically conductive material can be similar to copper pads 525 that are first shown in
A step 430 of method 400 is to form a spacer over a portion of the electrically conductive film. As an example, the spacer can be similar to spacers 610 that are first shown in
A step 440 of method 400 is to apply stiffener material adjacent to the spacer and over the raised areas of the electrically conductive material. As an example, the stiffener material can be similar to a stiffener material 620 that is first shown in
It should be understood that in some embodiments of method 400, steps 430 and 440 can be performed in reverse order, or combined into a single step. That is, in some embodiments the stiffener material may be applied before (or at the same time as) the spacer.
A step 450 of method 400 is to form vias in the stiffener material and plate the vias with a second electrically conductive material. In one embodiment, the second electrically conductive material is the same as or similar to the first electrically conductive material. As an example, the vias can be similar to vias 710 that are first shown in
A step 460 of method 400 is to form build-up layers over the spacer and the stiffener material. As an example, the build-up layers can be similar to build-up layers 150 that are first shown in
As illustrated in
A step 470 of method 400 is to separate the preliminary structure into a first piece and a second piece. After some further processing, discussed below, the first piece and the second piece become completed coreless substrates. Accordingly, in the illustrated embodiment, method 400 turns each preliminary structure into two separate coreless substrates. Step 470 may be accomplished using any suitable singulation technique.
A step 480 of method 400 is to remove the core material, spacer, and the electrically conductive film from the first piece and the second piece. A result of the performance of step 480 is shown in
Although the invention has been described with reference to specific embodiments, it will be understood by those skilled in the art that various changes may be made without departing from the spirit or scope of the invention. Accordingly, the disclosure of embodiments of the invention is intended to be illustrative of the scope of the invention and is not intended to be limiting. It is intended that the scope of the invention shall be limited only to the extent required by the appended claims. For example, to one of ordinary skill in the art, it will be readily apparent that the coreless substrates, the microelectronic packages, and the related methods discussed herein may be implemented in a variety of embodiments, and that the foregoing discussion of certain of these embodiments does not necessarily represent a complete description of all possible embodiments.
Additionally, benefits, other advantages, and solutions to problems have been described with regard to specific embodiments. The benefits, advantages, solutions to problems, and any element or elements that may cause any benefit, advantage, or solution to occur or become more pronounced, however, are not to be construed as critical, required, or essential features or elements of any or all of the claims.
Moreover, embodiments and limitations disclosed herein are not dedicated to the public under the doctrine of dedication if the embodiments and/or limitations: (1) are not expressly claimed in the claims; and (2) are or are potentially equivalents of express elements and/or limitations in the claims under the doctrine of equivalents.
