Crystalline Semiconductor Growth On Amorphous And Poly-Crystalline Substrates

Abstract

A multilayer semiconductor structure including at least in part a substrate and an III-N film layer. The substrate's constant of thermal expansion being substantially matched to the III-N film's constant of thermal expansion. The multilayer semiconductor structure may also include a crystal matching layer that has a lattice constant that substantially matches the lattice of constant of the III-N film. By not relying on the substrate for lattice matching the III-N film, the multilayer structure allows greater flexibility in the selection of an applicable substrate.

Description

TECHNICAL FIELD

The present invention is related to a multilayer semiconductor structure.

BACKGROUND

Group III-Nitride (III-N) semiconductors such as AlN, AlGaN, GaN, and InGaN have become important materials for the production of Light Emitting Diodes (LEDs) and high power devices such as High-Electron-Mobility Transistors (HEMTs). Other III-Nitrides such as AlN and AlGaN are often included in device structures to mitigate mismatches in lattice and thermal expansion or as barrier or cladding layers in LEDs. Homoepitaxial growth of III-Nitrides has significant commercial limitations due to the absence of crystalline III-N substrates of reasonable cost and adequate size. Accordingly, heteroepitaxial growth methods have been developed wherein the III-Nitrides are grown on non-native substrates which are not well-matched to III-Nitride films in terms of crystal lattice dimensions or coefficient of thermal expansion (CTE). The mismatch between the substrate, also referred to as the growth template, and the III-N film results in undesirable defects in the films crystal structure and distortions such as bowing or cracking of the substrate/film stack. Current techniques for heteroepitaxy growth of III-N materials involve expensive processes while only partially mitigating defect generation resulting from lattice and CTE mismatch.

BRIEF SUMMARY

Various embodiments of the invention seek to separate the CTE and lattice matching requirements for optimized III-Nitride growth by (1) creating a coefficient of thermal expansion match by providing a CTE-matched substrate and (2) creating a lattice-matched growth surface using a film or stack of films that create a crystalline lattice structure and/or lattice spacing.

Embodiments of the present invention may be achieved, for example, by selecting a bulk material for a substrate having a coefficient of thermal expansion substantially matching that of GaN or other semiconductor film and being manufactured as a wafer-like substrate with sub-nanometer-scale surface finish and selecting a thin film material or material stack that can be induced to have a crystal lattice substantially matching that of GaN. The thin film material or material stack is deposited on the bulk material in such a way that the thin film crystal structure is achieved independently of the bulk materials structure or lack of structure.

In one embodiment, the thin film crystalline layer or stack of layers establishes a crystal structure suitable for the nucleation and growth of III-Nitride films. Crystal quality can be further influence by adding seed layers, also known as underlayers, between the bulk substrate and the thin film stack. Seed layers can also be used to influence both crystal orientation and grain size of the thin film stack.

In one embodiment, the substrate is chosen to be CTE matched to the GaN film, but the substrate is not a single crystal or oriented multi-crystalline material and does not provide a crystalline template for the GaN growth. Instead, an oriented crystalline template for the GaN is provided by the intermediate layers (e.g. thin film crystalline layer, seed layer etc.).

In contrast with growth templates currently used in the art, embodiments of the invention do not rely on the structure of the bulk substrate to establish crystallinity. Crystallinity is established only in the thin film stack, with no required coincidence or crystal registry to the crystal lattice of the substrate. Consequently, the bulk material can be chosen based on CTE properties and suitability for mass production; opening the opportunity to use amorphous or low crystal quality poly-crystals with little to no crystalline orientation.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a cross sectional view of a multilayer semiconductor structure, in accordance with one exemplary embodiment of the present invention.

FIG. 1B is a cross sectional view of a multilayer semiconductor structure, in accordance with one exemplary embodiment of the present invention.

FIG. 1C is a cross sectional view of a multilayer semiconductor structure, in accordance with one exemplary embodiment of the present invention.

FIG. 1D is a cross sectional view of a multilayer semiconductor structure, in accordance with one exemplary embodiment of the present invention.

FIG. 1E is a cross sectional view of a multilayer semiconductor structure, in accordance with one exemplary embodiment of the present invention.

DETAILED DESCRIPTION

The various embodiments are described more fully with reference to the accompanying drawings. These example embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to readers of this specification having knowledge in the technical field. Like numbers refer to like elements throughout.

FIG. 1E illustrates a cross-section view of multilayer structure 100. Multilayer structure 100 includes several layers including: substrate 101, isolation layer 103, seed layer 105, crystal matching layer 107, nucleation layer 109, and III-N film 111. III-N film is a layer of semiconductor material consisting of at least one group III nitride material and/or their alloys (e.g. GaN, InN, AlGaN, InGaN). In some embodiments one or more layers 103, 105, 109, and 111 may be optional. Although, embodiments of the present invention are described below with reference to an III-N film, it is understood that any semiconductor film may be used by adjusting crystal matching layer 107 to accommodate the lattice parameter of the chosen semiconductor film.

The process of forming multilayer structure 100 is described with relation to FIGS. 1A-1E. Now with reference to FIG. 1A, multilayer structure 100 includes, in part isolation layer 103 deposited via physical layer deposition (PVD) or chemical vapor deposition (CVD) on substrate 101. Depending on various applications, substrate 101 includes, in part a semiconductor material, a compound semiconductor material, or other type of material such as a metal or non-metal. For example, the materials comprising substrate 101 may include: molybdenum, molybdenum-copper, poly-aluminum nitride ceramic, mullite ceramic, alumina, sapphire, refractory nitrides of Zr(ZrN), Ti (Ti—N), Hf (HFN) or any alloy therein, graphite, aluminum-oxynitrides, silicon, silicon carbide, zinc oxides and rare earth oxides, and/or other suitable materials. In some embodiments, substrate 101 has a thickness in the range of 250 microns to 1 mm. Depending on various applications and material composition, substrate 101 may take different structural forms. For example, substrate 101 may include an amorphous or polycrystalline structure. However, in other embodiments, substrate 101 may include a single crystal (e.g. sapphire and silicon) or oriented multi-crystalline material. Regardless of the material or the structure, substrate 101 has a coefficient of thermal expansion (CTE) substantially matching the CTE of III-N film 111.

In accordance with one embodiment of the present invention, substrate 101 for the multilayer structure 100 may be chosen for its CTE properties, and there may be no reliance on the underlying crystal structure of the substrate. As a result, substrate 101 may include any material so long as substrate 101 has a CTE (ppm per degree Kelvin or 10̂-6/K) that substantially matches the III-N film 111. Instead of depending on substrate 101 for providing a crystal structure or template for III-N film 111 growth, the crystal matching layer 107 may completely replace, upgrade, or enhance the crystal structure of substrate 101 and directly enable III-N film 111 growth.

What is considered a substantially matched CTE depends on the application of the multilayer structure 100. In accordance with one embodiment, the substrate's CTE is within ±5% of the III-N film's CTE to be substantially matching. For example, in order for a substrate to be substantially matched with GaN (having an approximate CTE of 5.6), the substrate has a CTE between 5.32 and 5.88. The CTE of molybdenum is approximately 5.4, and according to one embodiment, is substantially matched to the CTE of GaN. Applications in power semiconductor discrete devices, GaN based integrated circuits (IC), or high current density optoelectronic devices; of which creating significant thermal stresses during fabrication of semiconductor device layer on the substrate would benefit from a substantial match in CTE in accordance with one embodiment. On the other hand, a silicon substrate with an approximate CTE of 2.6, would not be substantially matched to the CTE of the GaN film according to one embodiment. According to one embodiment, other materials that substantially match GaN include but are not limited to: Zirconium, Molybdenum, pure Arsenic, ZrTi (86:14 atomic percent), Carbide, and multigrained or polycrystalline Aluminum Nitride ceramic (1 to 1 atomic ratio).

In one embodiment, a substrate's CTE substantially matches the III-N film's CTE if the substrate's CTE is within 1 unit (where 1 unit is a ppm per degree Kelvin) of the III-N film's CTE. In accordance with this embodiment, materials that substantially match GaN include, but are not limited to: Zirconium, Osmium, Hafnium, Chromium, Molybdenum, Cerium, Rhenium, Tantalum, Iridium, Ruthenium, Tungsten, Praseodymium, Germanium, InAs, InP, InSb, AlAs, AlP, GaP, GaAs, pure Arsenic, Molybdenum-Copper, alloys of ZrTi, alloys of Hffi, Carbide, and poly-Aluminum Nitride ceramic (1 to 1 atomic ratio), Titanium, alloys of Molybdenum, alloys of Tungsten, alloys of Nickel, alloys of Niobium, alloys of Iridium, Kovar, alloys of Neodymium, Molybdenum-Copper, metal alloys of Ti, alloys of Zr, alloys of Hf, Carbide, poly-Aluminum Nitride ceramic of varying atomic proportions, alumina ceramic, titania, polycrystalline SiC. Typical applications requiring a substantially matched CTE according to this embodiment include, but are not limited to, thermal annealing, thermal degas or cleaning steps, physical or chemical film growth, recrystallization steps, metal contact firing steps, implantation and subsequent annealing, or any circuit fabrication steps (mask/lithography, growth, etch/pattern, metallization, CMP, etc) that may require temperature heat up/cool down steps in any portion of the range of 1400 Celsius to room temperature and must remain below 50 microns of substrate or wafer bow over any wafer diameter.

In another embodiment, a substrate's CTE substantially matches the III-N film's CTE if the substrate's CTE is within 0.5 unit (where the unit is a ppm per degree Kelvin) of the III-N film's CTE. For example, molybdenum has a CTE of approximately 5.4, which is within 0.5 of the CTE (unit of ppm per degree Kelvin) of GaN. In accordance with this embodiment, other materials that substantially match GaN include, but are not limited to: Molybdenum, pure Arsenic, Chromium, ZrTi (86:14), Carbide, Germanium, Osmium, Zirconium, Hafnium, InSb, Kovar, and poly-Aluminum Nitride ceramic (1 to 1 atomic ratio). Typical applications requiring a substantially matched CTE according to this embodiment include, but are not limited to: thermal annealing, thermal degas or cleaning steps, physical or chemical film growth, recrystallization steps, metal contact firing steps, implantation and subsequent annealing, or any circuit fabrication step (mask/lithography, growth, etch/pattern, metallization, CMP, etc.) that requires temperature heat up/cool down steps in any portion of the range of 1400 Celsius to room temperature, and must remain below 25 microns of substrate or wafer bow over any wafer diameter.

It is known that differences in CTE between a film and substrate can lead to residual stress between the film and the substrate as a result of heating and cooling processes during film deposition. Residual stress may result in compression or tension on the film. When the film compresses, the residual stress may be relieved by buckling of the film, but when the film is under tension, the residual stress may be relieved by cracking of the film. In one embodiment, in the case of a CTE mismatch between the film and the substrate that results in residual stress, the multilayer structure 100 should be designed to create compression on III-N film 111 rather than tension on III-N film 111. Moreover, maintaining wafer flatness is crucial to manufacture devices from the deposited GaN film(s) on the substrates. For any film thickness of GaN grown on a substrate where the film thickness is less than the substrate thickness, Table 1 enumerates designs that would be allowed assuming increasing substrate diameter and corresponding thickness to achieve two categories of tolerable bow or warp, namely less than 25 microns and lower than 50 microns (limits mainly set by automatic handling equipment and limits in depth of focus for lithographic steps).

TABLE 1
As-				Extrinsic	Calcu-
sumed			Delta CTE	Strain	lated
Thick-			allowed	allowed @	max
ness	Diam-	CTE	by	1400 C.	Bow	Curva-
(mi-	eter	Match	matching	cool down	(mi-	ture
cron)	(mm)	Range	(ppm/C.)	cycle	cron)	(1/km)
675	150	+/−5%	0.28	−0.000385	3.21	1.14
725	200	+/−5%	0.28	−0.000385	5.31	1.06
825	300	+/−5%	0.28	−0.000385	10.50	0.93
675	150	+/−0.5	0.5	−0.0006875	5.73	2.04
725	200	+/−0.5	0.5	−0.0006875	9.48	1.90
825	300	+/−0.5	0.5	−0.0006875	18.75	1.67
675	150	+/−1.0	1.0	−0.001375	11.46	4.07
725	200	+/−1.0	1.0	−0.001375	18.97	3.79
825	300	+/−1.0	1.0	−0.001375	37.50	3.33

To remain below 50 microns of bow or warp any wafer diameter and any of the 3 ranges of CTE matching can be used (+/−5% of value, +/−0.5, and +/−1.0 about the value of GaN). Similarly to remain below 25 microns of bow or warp all wafer diameters are allowed for all 3 ranges of CTE matching with the exception of 300 mm for +/−1.0 ppm about the GaN value. This latter condition could be reached if wafer thickness is allowed to increase by industry standards to 1200 mm (<25 microns bow for a +/−1 ppm delta in CTE compared to GaN on 300 mm diameter).

As previously stated, the isolation layer 103 is deposited on substrate 101 by any suitable PVD or CVD process (e.g. Plasma-enhanced chemical vapor disposition (PECVD), Low-pressure chemical vapor deposition (LPCVD), Atomic layer deposition (ALD), Plasma Torch, Liquid phase epitaxy (LPE), and spin coat annealing) In some embodiments, the thickness of the isolation layer 103 is in the range of 1.0 nm (1 nm=1 nanometer=1×10⁻⁹ m) to 500 nm. In one embodiment, the isolation layer 103 is deposited via a spin on coat technique from a liquid and annealed to achieve a smooth film. The isolation layer 103 may serve as a smooth and non-reacting surface for subsequent layers. The isolation layer 103 may be also used to prevent subsequent layers from replicating an undesirable crystal structure that may be found in substrate 101, resetting the crystalline orientation and setting a new growth axis. Materials that could be used in the isolation layer 103 would have one or more of the following function(s) and properties: amorphous or lack of crystal structure, be deposited as non-conformal films, low stress, and the capability to fill in high aspect ratio morphology such as pits, grooves, or ledges. For example, glasses, glassy carbon, metal nitrides, oxy-nitrides, and oxides such as SiO2 are examples of materials that can be included in the isolation layer 103. In some embodiments, where the substrate has a desirable crystal structure isolation layer 103 may be omitted from structure 100. In one embodiment, isolation layer 103 includes silicon dioxide or silicon nitride. In some embodiments, isolation layer 103 includes multiple layers followed by a chemical mechanical polish to achieve sufficient flatness, in the range of <5 nm rms surface roughness on areas of 25 um×25 um.

Now with reference to FIG. 1B, seed layer 105 is deposited on isolation layer 103. Seed layer 105 includes, in part one or more thin film layers deposited on top of each other (i.e. in a stack) by any known CVD or PVD process. In some embodiments, the thickness of the seed layer 105 is in the range of 1 atomic layer to 500 nm. Seed layer 105 defines crystal orientation, crystal polarity, crystal structure type, and/or grain size for crystal matching layer 107 and may consist of multiple layers. In one embodiment, the seed layer 105 includes, in part at least one or more of the following materials: carbon, iron, chromium, titanium, cobalt, ruthenium, tantalum, nickel, and molybdenum. In one embodiment, seed layers will be grown using PVD techniques and will be grown at appropriate temperatures and target power to achieve dense films. In the case of wurtzite structure films, the c-axis will be normal to the growth plane, and in the case of cubic crystals, the 111 axis will be normal to the growth plane. For example, a first layer in seed layer 105 includes titanium (Ti) and may be used to lower the surface energy of substrate 101 in order to improve the growth of subsequent layers by thermodynamically favoring the (0001) direction to be normal to the plane. In another example, substrate 101 is an aluminum nitride ceramic wafer and seed layer 105 is a thin film layer of cobalt, which together establish a hexagonal close packed (HCP) structure with the c-axis perpendicular to substrate 101. The HCP structure created by seed layer 105 influences the crystal orientation of the subsequent crystal matching layer 107. In other embodiments, seed layer 105 may be used to form a face center cubic (FCC) structure, HCP, or a body centered cubic (BCC) structure, which allows the crystal matching layer 107 to grow with the HCP crystal structure. Stated another way, the seed layer 105 does not have to be a matched crystal structure to the crystal matching layer 107; instead the seed layer 105 is an appropriate crystal structure. In some embodiments where substrate 101 presents a suitable crystal structure, both isolation layer 103 and seed layer 105 may be omitted from multilayer structure 100. Examples of such substrates could include ZrTi, Molybdebdum, Hffi, c-oriented polycrystalline Aluminum Nitride, and c-oriented poly-crystalline SiC, materials with CTE within +/−5% about the value of GaN.

With reference to FIG. 1C, crystal matching layer 107 is deposited on seed layer 105. The crystal matching layer may be deposited on seed layer 105 using any known and suitable PVD or CVD method. Because, substrate 101 is selected due to its CTE qualities in relation to III-N film 111, there may exist lattice constant mismatch between substrate 101 and III-N film 111. In particular, the lattice mismatch can be extremely different, and may be greater than the 13% typically sought for heteroepitaxy. Embodiments of the invention allow for independently matching the CTE of substrate 101 and III-N film 111 without regard to the lattice parameter of substrate 101 of multilayer structure 100. The crystal matching layer 107 includes, in part one or more metal layers that accommodate and/or eliminate the lattice constant mismatch between substrate 101 and III-N film 111. The thickness of crystal matching layer 107 ranges between 5 nm and 1000 nm.

In one embodiment, the crystal matching layer includes, in part two or more constituent elements, for example two constituents includes, in part a first chemical element and a second chemical element to form a constituent element alloy. The constituent elements may have similar crystal structures at room temperature, such as an HCP structure. In addition to crystal structures, the constituent elements may have similar chemical properties. In one embodiment, the first and second chemical elements may both belong to group four elements (e.g. titanium (Ti), zirconium (Zr), hafnium (Hf) and rutherfordium (Rf)), alloys of the group four elements, nitrides of the group four elements, and the alloys further alloyed with the elements of tantalum (Ta), boron (B), silicon (Si), and the crystal matching layer 107 is capped with the nucleation layer 109. The constituent element alloy may include a third chemical element or more elements which have similar crystal structures and similar chemical properties. The different chemical elements and the proportions of those chemical elements that make up the constituent element alloy(s) of crystal matching layer 107 may be modified to substantially match the lattice constant of III-N film 111. According one embodiment, ranges for substantial match for heteroepitaxy to mimic homo-epitaxy and do not form crystal misfit and dislocation defects is within the range of +/−1-3% of the value of the III-N film layer's lattice constant (layer 111). The process of selecting and proportion these chemical elements is further described in U.S. Pat. No. 8,956,952 and U.S. patent application Ser. No. 14/106,657. By utilizing crystal matching layer 107, potential residual stress, along with point and extended defects such as crystal misfit and threading dislocation, may all together be lowered or completely removed which might otherwise occur in III-N film 111 as a result of the difference in the lattice constants between substrate 101 and III-N film 111. Substantially matching the lattice constants (i.e. +/−1-3%) of crystal matching layer 107 and III-N film 111 aids in the growth of the highest crystalline quality III-N film.

In another embodiment, the crystal matching layer 107 may comprise of a glassy carbon, graphene carbon, graphitic carbon, or pyrolyzed carbon, diamond carbon, and diamond-like coatings that has been purposefully “peppered” with point defects throughout the surface of the film. The term “graphitic crystal matching layer” and like terms refers to an embodiment where crystal matching layer 107 comprises may comprise of a glassy carbon, graphene carbon, graphitic carbon, or pyrolyzed carbon, diamond carbon, and diamond-like coatings that has been purposefully “peppered” with point defects throughout the surface of the film. The graphitic crystal matching layer 107 is comprised of >2 carbon layers (e.g. 2, 3, 4, 5), wherein the point defects are introduced in the topmost layer of carbon atoms. A point defect is created by a displacing an atom from its equilibrium lattice position.

In one embodiment, graphitic crystal matching layer 107 is initially grown on low cost metal such as copper metal, or SiC wafer, or SiC coating on Si wafer, forming graphene from the decomposition of a methane or acetylene gas, or other carbon containing gas using a vapor phase deposition. The carbon grows as graphene sheets, 1 to 5 carbon layers thick, and can be mechanically released using a thermal anneal tape or direct wafer to wafer contact transfer method, and subsequently transferred by direct application to seed layer 105 (or any other suitable layer.) Once the graphitic crystal matching layer 107 is transferred to multilayer structure 100 the tape or the carrier substrate of the graphitic crystal matching layer 107 is released by reheating to temperatures above 250 C and cooling down to room temperature.

In a second embodiment, a positive photoresist (PR) is spun directly onto seed layer 105 and then annealed at temperatures >1000 C in inert gas annealing chamber or under high vacuum, resulting in benzene rings in the PR to form hexagonal graphene or graphitic carbon as the volatile organic compounds are evaporated from the PR. Thus the PR becomes graphitic or graphene and acts as the graphitic crystal matching layer.

The ability to use graphene comes about due to the satisfied sp2 bonds associated with graphene, which in turn does not provide chemically reactive sites for traditional epitaxial growth that rely on covalent bonding out of the plane of the film on the graphene. Instead, the first layer of atoms from nucleation layer 109 is attracted to the outermost layer of atoms from graphitic crystal matching layer 107 owing to the point defects, otherwise uniform film formation would not arise without the point defect strategy. State another way, without point defects in graphitic crystal matching layer 107 subsequent layers cannot be uniformly grown on graphitic crystal matching layer 107. This means no electrons transfer and no significant lattice mismatch can form, with III-N film 111 if one can nucleate the III-N film 111 (e.g. AlGaN, GaN, InGaN) on the graphene, the only bonds of significance that determine strain are the cohesive ones within the III-N film 111 itself. Stated another way, the graphene or graphitic crystal matching layer 107 interface with substrate 101 consists of van der Waals bonds only, which allows for completely relaxed growth of III-N film 111 at its unstrained lattice parameters, producing a compliant interface. Furthermore, graphene allows for the growth of high quality III-N films since III-N film 111 does not initiate with strain. Because of the lack of strain there is no buildup as the film grows to a given thickness as is traditionally the case with heteroepitaxy of dissimilar materials. The cause for a film to form defects is the buildup of strain leading to stress which is released by forming extended defects after a critical thickness is reached. By utilizing van der Waals nucleation, defects which are typically generated due to this strain have no driving force to form. In other words, when using a graphene or graphitic crystal with sp2 bonding within the plane and no out of plane bonds for the crystal matching layer 107, requiring the addition of point defects by plasma exposure or other energetic bombardment prior to growth of nucleation layer 109, III-N film 111 film grows unstrained to underlying substrate 101 which paves the way for very high structural and crystalline quality film to grow with its equilibrium lattice constants. In one embodiment, crystals in the range of 3.1 Angstroms to 4.5 Angstroms can grow “relaxed” and without mismatch, as they are accommodated to float via van der Waal interaction.

In another embodiment, the graphitic crystal matching layer 107 is a thermal conductive layer in the range of 1000 to 2000 Watts/meter*Kelvin (W/m*k), enabling heat to be removed from this layer that is in in the range 20× to 40× more thermally conductive than the substrates or the GaN itself. Thus, for example, the graphitic crystal matching layer 107 would allow a transistor that operates at 250 C to run at 100 C for example. Typical conductivity of polycrsytalline AlN is about 150-180 W/mK, Si and GaN are approximately 50 W/mK. Thus, the graphitic crystal matching layer 107 operation as a heat sink would be a big advantage over traditional heat sinks in the semiconductor field.

Now with reference to FIG. 1D, nucleation layer 109 is deposited on the crystal matching layer 107. The nucleation layer 109 may be deposited by any suitable PVD or CVD process. The nucleation layer provides a surface that is chemically and physically compatible with III-N film 111. Nucleation layer 109 also provides a suitable growth environment (i.e. chemistry, crystal polarity, and symmetry) for growing III-N film 111. In some embodiments, nucleation layer 109 includes, in part a nitride film (e.g. aluminum nitride (AlN)). In one embodiment, nucleation layer 109 is deposited in the range of 1.0 nm to 200 nm and is pseudomorphically grown to maintain the lattice of the crystal matching layer 107. The nucleation layer 109 may be pseudomorphically (with the same lattice parameter of crystal matching layer 107) grown aluminum nitride (AlN), aluminum gallium nitride (AlGaN), gallium nitride (GaN), indium gallium nitride (InGaN). In one embodiment, the nucleation layer 109 has the same lattice parameter as the crystal matching layer 107.

With reference to FIG. 1E, III-N film 111 is deposited on the nucleation layer 109. The III-N film may be epitaxial grown by any suitable PVD or CVD process. In one embodiment, the III-N film 111 is a semiconductor compound and a member of the solid solution gallium nitride (GaN) and its alloys with aluminum (Al), indium (In), boron (B), including and not limited to: aluminum nitride (AlN), aluminum gallium nitride (AlGaN), gallium nitride (GaN), indium nitride (InN), indium gallium nitride (InGaN), and boron nitride (BN). A novel concept presented by the embodiments of the present invention is that by removing lattice mismatch and CTE mismatch independently using multilayer structure 100, for the first time there is no upper limit to the thickness of the III-N film 111 that can be grown. In an alternate embodiment III-N film 111 is deposited on the nucleation layer 109 or directly upon the crystal matching layer 107 by hydride Vapour Phase Epitaxy (HVPE). The use of HVPE for the epitaxial growth of the III-N semiconductor allows for the III-N semiconductor to grow cost effective high crystalline quality (thick) films. Typically, HVPE films can be grown from 10 microns to 1 mm in 1-3 hours, whereas the limitation in grow rates for conventional MOCVD limits grow to <10 microns, takes 10-20 hours to grow.

In one embodiment, multilayer structure 100 includes the following layers: poly AlN substrate with a diameter of 200 mm and a thickness of 825 micron (101), spin on glass such as SiO2 with a thickness of 750 nm (103), tantalum seed layer with a thickness of 10 nm (105), ZrTi with a thickness of 1000 nm (107), AlN with a thickness of 200 nm (109), and device layers of GaN with a thickness of 1 micron to 50 micron (111).

In another embodiment, multilayer structure includes the following layers: polycrystalline AlN ceramic substrate with a diameter of 200 nm and a thickness of 825 um (101), SiO2 layer with a thickness of 750 nm (103), graphene seed layer with a thickness of >2 atomic layers (107), AlN layer with a thickness of >10 nm (109), and a device layers of GaN with a thickness of 1 micron to 50 micron (111).

Many modifications and other example embodiments set forth herein will bring to mind to the reader knowledgeable in the technical field to which these example pertain to having the benefit of the teachings presented in the foregoing descriptions and the associated drawings. Therefore, it is to be understood that the embodiments are not to be limited to the specific ones disclosed and that modifications and other embodiments are intended to be included within the scope of the claims. Moreover, although the foregoing descriptions and the associated drawings describe example embodiments in the context of certain example combinations of elements and/or functions, it should be appreciated that different combinations of elements and/or functions may be provided by alternative embodiments without departing from the scope of the appended claims. In this regard, for example, different combinations of elements and/or functions other than those explicitly described above are also contemplated as may be set forth in some of the appended claims.

Claims

1. A multilayer structure comprising: a semiconductor substrate;a seed layer comprising of silicon deposited above the semiconductor substrate;a graphitic crystal matching layer comprising carbon deposited above the seed layer; anda device layer formed above the graphitic crystal matching layer, wherein the semiconductor substrate has a coefficient of thermal expansion (CTE) substantially matching a CTE of the device layer.

2. The multilayer structure of claim 1, wherein the seed layer defines crystal orientation and grain size of the graphitic crystal matching layer.

3. The multilayer structure of claim 1, wherein the semiconductor substrate is not a single crystal substrate.

4. The multilayer structure of claim 1, wherein the semiconductor substrate comprises oriented multi-crystalline material.

5. The multilayer structure of claim 1, wherein the graphitic crystal matching layer has point defects throughout its surface.

6. The multilayer structure of claim 1, wherein the device layer comprises one or more of the following materials: AlGaN, GaN, or InGaN

7. The multilayer structure of claim 5, further comprising a nucleation layer deposited on the graphitic crystal matching layer.

8. The multilayer structure of claim 1, wherein the graphitic crystal matching layer comprises at least two layers of carbon.

9. The multilayer structure of claim 8, wherein the graphitic crystal matching layer has point defects in a first layer of carbon, wherein the first layer of carbon is above all other layers of carbon.

10. A method of creating a multilayer structure comprising: forming a seed layer comprising of silicon deposited above a semiconductor substrate;forming a graphitic crystal matching layer comprising carbon above the seed layer; andforming a device layer above the graphitic crystal matching layer, wherein the semiconductor substrate has a coefficient of thermal expansion (CTE) substantially matching a CTE of the device layer.

11. The method of claim 10, wherein the seed layer defines crystal orientation and grain size of the graphitic crystal matching layer.

12. The method of claim 10, wherein the semiconductor substrate is not a single crystal substrate.

13. The method of claim 10, wherein the semiconductor substrate comprises oriented multi-crystalline material.

14. The method of claim 10, wherein the graphitic crystal matching layer has point defects throughout its surface.

15. The method of claim 10, wherein the device layer comprises one or more of the following materials: AlGaN, GaN, or InGaN

16. The method of claim 14, further comprising forming a nucleation layer deposited on the graphitic crystal matching layer.

17. The method of claim 10, wherein the graphitic crystal matching layer comprises at least two layers of carbon.

18. The method of claim 10, wherein the graphitic crystal matching layer has point defects in a first layer of carbon, wherein the first layer of carbon is above all other layers of carbon.

19. The method of claim 10, initially forming the graphitic crystal matching layer on a metal surface using vapor phase deposition, wherein the metal surface is separate from the semiconductor substrate, seed layer, and device layer; mechanically removing the graphitic crystal matching layer from the metal surface; anddepositing the graphitic crystal matching layer on the seed layer.