Patent Application
20250149521
This disclosure relates to photonics devices, and more specifically, to an interface between a digital signal processor and a photonics device.
Unless otherwise indicated herein, the materials described herein are not prior art to the claims in the present application and are not admitted to be prior art by inclusion in this section.
Modern optical transceivers for datacenters may rely on a sophisticated combination of digital signal processors (DSPs) and photonics. Signals between the DSPs and the photonics may traverse traces in a package and/or on a printed circuit board (PCB). Due to increasing speeds of communication, it is conventional practice to design the traces to form one or more transmission line (e.g., that may be distributed) circuits that may include a standard impedance (e.g., 50 ohms). Forming the transmission line circuits using the traces may be utilized due to the trace lengths being multiples of a wavelength at the symbol rate. For example, a symbol rate of 56 gigabits per second may correspond to a wavelength of approximately 5 mm in air and/or 3 mm on a microstrip transmission line on a PCB. However, photonic devices, such as modulators and detectors, have electrical impedances which may deviate from 50 ohms. In such instances a shunt termination resistor may be added in parallel with the photonic devices to avoid reflections in the transmission line (where the reflections may have a deleterious effect on the system performance). Drawbacks of adding the shunt termination resistor may include dissipated power, reduced system gain, and/or degraded signal quality.
The subject matter claimed in the present disclosure is not limited to implementations that solve any disadvantages or that operate only in environments such as those described above. Rather, this background is only provided to illustrate one example technology area where some implementations described in the present disclosure may be practiced.
In an example embodiment, an electronic device may include an electrically insulating substrate, a digital signal processor, and a photonics assembly. The electrically insulating substrate may include a main body. The digital signal processor may be disposed on a first surface of the electrically insulating substrate and may be arranged relative to the electrically insulating substrate such that a portion of the digital signal processor may extend beyond the main body of the electrically insulating substrate. The photonics assembly may be disposed adjacent to the electrically insulating substrate and may be electrically coupled to the digital signal processor.
In another embodiment, a method may include arranging a digital signal processor on a first surface of an electrically insulating substrate such that a portion of the digital signal processor may extend beyond the main body of the electrically insulating substrate. The method may also include arranging a photonics assembly adjacent to the electrically insulating substrate and proximate to the digital signal processor. The method may further include bonding the photonics assembly to the digital signal processor such that the photonics assembly may be electrically coupled to the digital signal processor.
The objects and advantages of the embodiments will be realized and achieved at least by the elements, features, and combinations particularly pointed out in the claims. Both the foregoing general description and the following detailed description are given as examples and are explanatory and not restrictive of the invention, as claimed.
Example implementations will be described and explained with additional specificity and detail using the accompanying drawings in which:
Some present interfaces between a digital signal processor (DSP) and a photonics assembly include transmission lines between the DSP and the photonics assembly to electrically couple the devices together. The transmission lines may include electrically conductive traces or micro strips arranged across a surface of a printed circuit board (PCB). In some instances, the length of the transmission lines may be tuned to be a multiple of a wavelength of a symbol rate output by the DSP. Such configurations may result in long transmission lines and/or a high impedance (due to the nature of the transmission lines). Many transmission lines include a default impedance (e.g., a fixed 50 ohm impedance), which may be difficult to match to a photonic device in the photonics assembly. Due to the impedance, a shunt termination resistor may be included to reduce reflections in the transmissions using the transmission line. The shunt resistor may introduce power dissipation, a reduction in system gain, and/or a degradation of signal quality.
Aspects of the present disclosure address these and other limitations by arranging components of an electronic device to be substantially closer to one another such that a need for a transmission line similar to previous approaches may be unnecessary. Alternatively, or additionally, the shunt resistor that was previously included to reduce reflections (and introduce system inefficiencies) may also be removed. As described herein, a DSP and a photonics assembly may be disposed near each other which may substantially reduce transmission losses, cross-talk between transmissions, and remove at least some of the inefficiencies present in traditional approaches (e.g., by removing the shunt termination resistor).
As illustrated in
In some instances, the DSP 102 may be electrically coupled to the photonics assembly 114 such that communications may occur between the DSP 102 and the photonics assembly 114. In some instances, the photonics assembly 114 may include the interposer 116 that may include electrically conductive pathways to facilitate communications from the DSP 102 to one or more photonics devices of the photonics assembly 114. For example, the interposer 116 may include the vias 118 that may be operable to route signals to the submount 120 of the photonics assembly 114.
In some instances, the connection between the DSP 102 and the photonics assembly 114 may be based on materials that are used in the photonics assembly 114. For example, in instances in which the photonics assembly 114 includes a silicon photonics device, the photonics assembly 114 may be bonded directly to the DSP 102 (e.g., the interposer 116 may not be included in the electronic device 100). In another example, in instances in which the photonics assembly 114 is a thin-film lithium niobate photonics device, then the photonics assembly 114 may be coupled with the interposer 116 and further bonded to the DSP 102. Other materials than those listed may be used, and some may facilitate bonding directly to the DSP 102 (e.g., similar to the silicon photonics device) while others may be bonded with the DSP 102 with the use of the interposer 116 (e.g., similar to the thin-film lithium niobate photonics device).
In these and other embodiments, thermocompression bonding may be utilized to couple the photonics assembly 114 to the DSP 102. Thermocompression bonding may be utilized in either of the example bonding configurations described herein, including instances in which the interposer 116 is present and/or instances in which the interposer 116 is not included in the electronic device 100. In instances in which thermocompression bonding is utilized, no solder may be included on the portion of the DSP 102 that extends beyond the main body of the PCB 104, and copper pillars on such portion of the DSP 102 may remain, such as for facilitating communications to the photonics assembly 114. Alternatively, or additionally, the photonics assembly 114 may be coupled to the DSP 102 using surface mount technology techniques, such as a ball grid array process.
In some instances, the photonics assembly 114 may be supported in place by the support structures 122. While the support structures 122 include multiple separate components, it should be appreciated that as few as a single support structure may be used to support the photonics assembly 114. In this particular embodiment, the support structures 122 may contribute to preventing an application of an undesired forces on the photonics assembly 114 that could cause structural damage to the photonics assembly 114. In some instances, the support structures 122 may be formed from electrically insulating materials, such as epoxy coated fiberglass.
As illustrated in
Modifications, additions, or omissions may be made to the electronic device 100 without departing from the scope of the present disclosure. For example, the designations of different elements in the manner described is meant to help explain concepts described herein and is not limiting. Further, the electronic device 100 may include any number of other elements or may be implemented within other systems or contexts than those described. For example, any of the components of
in accordance with at least one embodiment of the present disclosure. The electronic device 200 may include a digital signal processor (DSP) 202, a printed circuit board (PCB) 204, a shelf portion 206, first vias 212, a photonics assembly 214, an interposer 216, second vias 218, a submount 220, a first support structure 222a, a second support structure 222b, a third support structure 222c, referred to collectively as support structures 222, a photonics package 224, an electro-absorption modulator 226, a laser diode 228, a wire bond 230, and an electrical trace 232.
As illustrated in
In some instances, terminals of the DSP 202, that may be designed to interact with the photonics assembly 214, may be located on a far side of the DSP 202 as depicted. The location of the terminals of the DSP 202 may facilitate control signals being generated by the DSP 202 to be routed directly through the shelf portion 206 of the PCB 204. In some instances, a main body of the PCB 204 may include a first thickness 208 and the shelf portion 206 of the PCB 204 may include a second thickness 210. In some instances, the second thickness 210 may be substantially thinner than the first thickness 208 of the PCB 204. In some instances, the second thickness 210 (e.g., the thickness of the shelf portion 206) may be between 50 and 200 microns, while the first thickness 208 (e.g., the thickness of the main body of the PCB 204) may be between 1 mm and 6 mm.
Such an arrangement may support a disposition of the photonics assembly 214 to be beneath at least a portion of the DSP 202. As such and in conjunction with the thinness of the second thickness 210 of the shelf portion 206, the length of electrical pathways between the DSP 202 and the photonics assembly 214 may be substantially shorter than electrical pathways utilized in some current techniques of communications between a DSP and a photonics device.
In some instances, the photonics assembly 214 may include the interposer 216, and the interposer 216 may include electrically conductive pathways that helps deliver signals routed through the first vias 212 that extend through the shelf portion 206 to one or more photonics devices of the photonics assembly 214. For example, the interposer 216 may include the second vias 218 that may be operable to route signals to the submount 220 of the photonics assembly 214.
In some instances, the photonics assembly 214 may be supported in place by the support structures 222. While the support structures 222 include multiple separate components, it should be appreciated that as few as a single support structure may be used to support the photonics assembly 214. In this particular embodiment, the support structures 222 may contribute to preventing an application of an undesired forces on the shelf portion 206 that could cause structural damage to shelf portion 206 and/or the photonics assembly 214. In some instances, the support structures 222 may be formed from electrically insulating materials, such as epoxy coated fiberglass.
As illustrated in
The interposer 216 may include the wire bond 230 that may extend between the electro-absorption modulator 226 and the electrical trace 232. The wire bond 230 may be short (e.g., in terms of a physical length). For example, the wire bond 230 may include a length that may be less than 150 microns. The electrical trace 232 may be operable to route signals between the wire bond 230 and the first vias 212. As illustrated in
Modifications, additions, or omissions may be made to the electronic device 200 without departing from the scope of the present disclosure. For example, the designations of different elements in the manner described is meant to help explain concepts described herein and is not limiting. Further, the electronic device 200 may include any number of other elements or may be implemented within other systems or contexts than those described. For example, any of the components of
Modifications, additions, or omissions may be made to the first electronic device configuration 300 without departing from the scope of the present disclosure. For example, the designations of different elements in the manner described is meant to help explain concepts described herein and is not limiting. Further, the first electronic device configuration 300 may include any number of other elements or may be implemented within other systems or contexts than those described. For example, any of the components of
Modifications, additions, or omissions may be made to the second electronic device configuration 400 without departing from the scope of the present disclosure. For example, the designations of different elements in the manner described is meant to help explain concepts described herein and is not limiting. Further, the second electronic device configuration 400 may include any number of other elements or may be implemented within other systems or contexts than those described. For example, any of the components of
Modifications, additions, or omissions may be made to the third electronic device configuration 500 without departing from the scope of the present disclosure. For example, the designations of different elements in the manner described is meant to help explain concepts described herein and is not limiting. Further, the third electronic device configuration 500 may include any number of other elements or may be implemented within other systems or contexts than those described. For example, any of the components of
For simplicity of explanation, the method 600 described herein is depicted and described as a series of acts. However, acts in accordance with this disclosure may occur in various orders and/or concurrently, and with other acts not presented and described herein. Further, not all illustrated acts may be used to implement the methods in accordance with the disclosed subject matter. In addition, those skilled in the art will understand and appreciate that the methods may alternatively be represented as a series of interrelated states via a state diagram or events. Additionally, the methods disclosed in this specification may be capable of being stored on an article of manufacture, such as a non-transitory computer-readable medium, to facilitate transporting and transferring such methods to computing devices. The term article of manufacture, as used herein, is intended to encompass a computer program accessible from any computer-readable device or storage media. Although illustrated as discrete blocks, various blocks may be divided into additional blocks, combined into fewer blocks, or eliminated, depending on the desired implementation.
At block 602, a DSP on a first surface of an electrically insulating substrate may be arranged such that a portion of the DSP may extend beyond the main body of the electrically insulating substrate. In some instances, the electrically insulating substrate may be printed circuit board and may include a glass core.
In some instances, the electrically insulating substrate may include a shelf portion that may extend from the main body. The shelf portion may include multiple vias disposed therein, where the multiple vias may extend from a first side of the shelf portion to a second side of the shelf portion. The portion of the DSP may be disposed on the first side of the shelf portion and the photonics assembly may be disposed on the second side of the shelf portion. The photonics assembly may be electrically coupled to the DSP using the multiple vias.
At block 604, a photonics assembly may be arranged adjacent to the electrically insulating substrate and may be proximate to the DSP. In some instances, an interposer may be disposed between the shelf portion and the photonics assembly. Alternatively, or additionally, the interposer may be disposed between the DSP and the photonics assembly.
The interposer may include electrically conductive pathways which may facilitate communication between the DSP and the photonics assembly. In instances in which the shelf portion is included, the interposer may include electrically conductive pathways aligned with the multiple vias in the shelf portion to facilitate communication between the DSP and the photonics assembly.
At block 606, the photonics assembly may be bonded to the DSP such that the photonics assembly may be electrically coupled to the DSP. In some instances, the bonding of the photonics assembly to the digital signal processor may include thermocompression bonding.
Modifications, additions, or omissions may be made to the method 600 without departing from the scope of the present disclosure. For example, in some instances, an optical signal may be output from an electro-absorption modulated laser that may be associated with the first diode and the second diode. The optical signal may be based at least on the photocurrent. In another example, a reflection of the optical signal may be obtained and an optical alignment of the electro-absorption modulated laser may be performed using the optical signal and/or the reflected optical signal.
In another example, the designations of different elements in the manner described is meant to help explain concepts described herein and is not limiting. Further, the method 600 may include any number of other elements or may be implemented within other systems or contexts than those described.
Terms used in the present disclosure and especially in the appended claims (e.g., bodies of the appended claims) are generally intended as “open terms” (e.g., the term “including” should be interpreted as “including, but not limited to.”).
Additionally, if a specific number of an introduced claim recitation is intended, such an intent will be explicitly recited in the claim, and in the absence of such recitation no such intent is present. For example, as an aid to understanding, the following appended claims may contain usage of the introductory phrases “at least one” and “one or more” to introduce claim recitations. However, the use of such phrases should not be construed to imply that the introduction of a claim recitation by the indefinite articles “a” or “an” limits any particular claim containing such introduced claim recitation to implementations containing only one such recitation, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an” (e.g., “a” and/or “an” should be interpreted to mean “at least one” or “one or more”); the same holds true for the use of definite articles used to introduce claim recitations.
In addition, even if a specific number of an introduced claim recitation is expressly recited, those skilled in the art will recognize that such recitation should be interpreted to mean at least the recited number (e.g., the bare recitation of “two recitations,” without other modifiers, means at least two recitations, or two or more recitations). Furthermore, in those instances where a convention analogous to “at least one of A, B, and C, etc.” or “one or more of A, B, and C, etc.” is used, in general such a construction is intended to include A alone, B alone, C alone, A and B together, A and C together, B and C together, or A, B, and C together, etc.
Further, any disjunctive word or phrase preceding two or more alternative terms, whether in the description, claims, or drawings, should be understood to contemplate the possibilities of including one of the terms, either of the terms, or both of the terms. For example, the phrase “A or B” should be understood to include the possibilities of “A” or “B” or “A and B.”
All examples and conditional language recited in the present disclosure are intended for pedagogical objects to aid the reader in understanding the present disclosure and the concepts contributed by the inventor to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions. Although implementations of the present disclosure have been described in detail, various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the present disclosure.
This U.S. Patent Application claims priority to U.S. Provisional Patent Application No. 63/597,245, titled “DIGITAL SIGNAL PROCESSOR TO PHOTONICS INTERFACE,” and filed on Nov. 8, 2023, the disclosure of which is hereby incorporated by reference in its entirety.
| Number | Date | Country | |
|---|---|---|---|
| 63597245 | Nov 2023 | US |
