Field of the Invention
The field relates to dimension compensation control for directly bonded structures.
Description of the Related Art
Semiconductor elements, such as semiconductor wafers or integrated device dies, can be stacked and directly bonded to one another without an adhesive. For example, in some hybrid direct bonded structures, nonconductive field regions of the elements can be directly bonded to one another, and corresponding conductive contact structures can be directly bonded to one another. In some applications, it can be challenging to create reliable electrical connections between opposing contact pads, particularly for finely pitched contact pads. Accordingly, there remains a continuing need for improved contact structures for direct bonding.
Specific implementations will now be described with reference to the following drawings, which are provided by way of example, and not limitation.
Various embodiments disclosed herein relate to directly bonded structures 1 in which two elements 2, 3 can be directly bonded to one another without an intervening adhesive. Two or more semiconductor elements (such as integrated device dies, wafers, etc.) 2, 3 may be stacked on or bonded to one another to form a bonded structure 1. Conductive contact pads 4a of a first element 2 may be electrically connected to corresponding conductive contact pads 4b of a second element 3. Any suitable number of elements can be stacked in the bonded structure 1. For example, a third element (not shown) can be stacked on the second element 3, a fourth element (not shown) can be stacked on the third element, etc. Additionally or alternatively, one or more additional elements (not shown) can be stacked laterally adjacent one another along the first element 1.
In some embodiments, the elements 2, 3 are directly bonded to one another without an adhesive. In various embodiments, a non-conductive or dielectric material can serve as a first bonding layer 5a of the first element 2 which can be directly bonded to a corresponding non-conductive or dielectric field region serving as a second bonding layer 5b of the second element 3 without an adhesive. The nonconductive bonding layers 5a, 5b can be disposed on respective front sides 14 of device portions 6a, 6b, such as a semiconductor (e.g., silicon) portion of the elements 2, 3. Active devices and/or circuitry can be patterned and/or otherwise disposed in or on the device portions 6a, 6b. Active devices and/or circuitry can be disposed at or near the front sides 14 of the device portions 6a, 6b, and/or at or near opposite back sides 15 of the device portions 6a, 6b. The non-conductive material can be referred to as a nonconductive bonding region or bonding layer 5a of the first element 2. In some embodiments, the non-conductive bonding layer 5a of the first element 2 can be directly bonded to the corresponding non-conductive bonding layer 5b of the second element 3 using dielectric-to-dielectric bonding techniques. For example, nonconductive or dielectric-to-dielectric bonds may be formed without an adhesive using the direct bonding techniques disclosed at least in U.S. Pat. Nos. 9,564,414; 9,391,143; and 10,434,749, the entire contents of each of which are incorporated by reference herein in their entirety and for all purposes. It should be appreciated that in various embodiment, the bonding layers 5a and/or 5b can comprise a nonconductive materials such as a dielectric material, such as silicon oxide, or an undoped semiconductor material, such as undoped silicon.
In various embodiments, direct hybrid bonds can be formed without an intervening adhesive. For example, dielectric bonding surfaces 8a, 8b can be polished to a high degree of smoothness. The bonding surfaces 8a, 8b can be cleaned and exposed to a plasma and/or etchants to activate the surfaces 8a, 8b. In some embodiments, the surfaces 8a, 8b can be terminated with a species after activation or during activation (e.g., during the plasma and/or etch processes). Without being limited by theory, in some embodiments, the activation process can be performed to break chemical bonds at the bonding surface 8a, 8b, and the termination process can provide additional chemical species at the bonding surface 8a, 8b that improves the bonding energy during direct bonding. In some embodiments, the activation and termination are provided in the same step, e.g., a plasma or wet etchant to activate and terminate the surfaces 8a, 8b. In other embodiments, the bonding surface 8a, 8b can be terminated in a separate treatment to provide the additional species for direct bonding. In various embodiments, the terminating species can comprise nitrogen. Further, in some embodiments, the bonding surfaces 8a, 8b can be exposed to fluorine. For example, there may be one or multiple fluorine peaks near layer and/or bonding interfaces 7. Thus, in the directly bonded structures 1, the bonding interface 7 between two nonconductive materials (e.g., the bonding layers 5a, 5b) can comprise a very smooth interface with higher nitrogen content and/or fluorine peaks at the bonding interface 7. Additional examples of activation and/or termination treatments may be found throughout U.S. Pat. Nos. 9,564,414; 9,391,143; and 10,434,749, the entire contents of each of which are incorporated by reference herein in their entirety and for all purposes.
In various embodiments, conductive contact pads 4a of the first element 2 can also be directly bonded to corresponding conductive contact pads 4b of the second element 3. For example, a hybrid bonding technique can be used to provide conductor-to-conductor direct bonds along the bond interface 7 that includes covalently direct bonded nonconductive-to-nonconductive (e.g., dielectric-to-dielectric) surfaces, prepared as described above. In various embodiments, the conductor-to-conductor (e.g., contact pad 4a to contact pad 4b) direct bonds and the dielectric-to-dielectric hybrid bonds can be formed using the direct bonding techniques disclosed at least in U.S. Pat. Nos. 9,716,033 and 9,852,988, the entire contents of each of which are incorporated by reference herein in their entirety and for all purposes.
For example, nonconductive (e.g., dielectric) bonding surfaces 8a, 8b can be prepared and directly bonded to one another without an intervening adhesive as explained above. Conductive contact pads 4a, 4b (which may be surrounded by nonconductive dielectric field regions within the bonding layers 5a, 5b) may also directly bond to one another without an intervening adhesive. In some embodiments, the respective contact pads 4a, 4b can be recessed below exterior (e.g., upper) surfaces 5a, 5b of the dielectric field or nonconductive bonding layers 5a, 5b, for example, recessed by less than 30 nm, less than 20 nm, less than 15 nm, or less than 10 nm, for example, recessed in a range of 2 nm to 20 nm, or in a range of 4 nm to 10 nm. The nonconductive bonding layers 5a, 5b can be directly bonded to one another without an adhesive at room temperature in some embodiments and, subsequently, the bonded structure 1 can be annealed. Upon annealing, the contact pads 4a, 4b can expand and contact one another to form a metal-to-metal direct bond. Beneficially, the use of Direct Bond Interconnect, or DBI®, techniques commercially available from Xperi of San Jose, CA, can enable high density of pads 4a, 4b connected across the direct bond interface 7 (e.g., small or fine pitches for regular arrays). In some embodiments, the pitch of the bonding pads 4a, 4b, or conductive traces embedded in the bonding surface of one of the bonded elements, may be less than 40 microns or less than 10 microns or even less than 2 microns. For some applications the ratio of the pitch of the bonding pads 4a, 4b to one of the dimensions (e.g., a diameter) of the bonding pad is less than 5, or less than 3 and sometimes desirably less than 2. In other applications the width of the conductive traces embedded in the bonding surface of one of the bonded elements may range between 0.3 to 3 microns. In various embodiments, the contact pads 4a, 4b and/or traces can comprise copper, although other metals may be suitable.
Thus, in direct bonding processes, a first element 2 can be directly bonded to a second element 3 without an intervening adhesive. In some arrangements, the first element 2 can comprise a singulated element, such as a singulated integrated device die. In other arrangements, as shown in
As explained herein, the first and second elements 2, 3 can be directly bonded to one another without an adhesive, which is different from a deposition process. In one application, a width of the first element 2 in the bonded structure is similar to a width of the second element 3. In some other embodiments, a width of the first element 2 in the bonded structure 1 is different from a width of the second element 3. Similarly, the width or area of the larger element in the bonded structure may be at least 10% larger than the width or are of the smaller element. The first and second elements 2, 3 can accordingly comprise non-deposited elements. Further, directly bonded structures 1, unlike deposited layers, can include a defect region along the bond interface 7 in which nanovoids are present. The nanovoids may be formed due to activation of the bonding surfaces 8a, 8b (e.g., exposure to a plasma). As explained above, the bond interface 7 can include concentration of materials from the activation and/or last chemical treatment processes. For example, in embodiments that utilize a nitrogen plasma for activation, a nitrogen peak can be formed at the bond interface 7. In embodiments that utilize an oxygen plasma for activation, an oxygen peak can be formed at the bond interface 7. In some embodiments, the bond interface 7 can comprise silicon oxynitride, silicon oxycarbonitride, or silicon carbonitride. As explained herein, the direct bond can comprise a covalent bond, which is stronger than van Der Waals bonds. The bonding layers 5a, 5b can also comprise polished surfaces that are planarized to a high degree of smoothness.
In various embodiments, the metal-to-metal bonds between the contact pads 4a, 4b can be joined such that copper grains grow into each other across the bond interface 7. In some embodiments, the copper can have grains oriented along the 111 crystal plane for improved copper diffusion across the bond interface 7. The bond interface 7 can extend substantially entirely to at least a portion of the bonded contact pads 4a, 4b, such that there is substantially no gap between the nonconductive bonding layers 5a, 5b at or near the bonded contact pads 4a, 4b. In some embodiments, a barrier layer may be provided under the contact pads 4a, 4b (e.g., which may include copper). In other embodiments, however, there may be no barrier layer under the contact pads 4a, 4b, for example, as described in U.S. 2019/0096741, which is incorporated by reference herein in its entirety and for all purposes.
Beneficially, the use of the hybrid bonding techniques described herein can enable extremely fine pitch between adjacent contact pads 4a or 4b, and/or small pad sizes. For example, in various embodiments, the pitch p (see
In some devices, the elements 2, 3 can have different respective thicknesses T1, T2. For example, in some embodiments, the first element 2 can have a first thickness T1 that is greater than a second thickness T2 of the second element 3. For example, in the illustrated embodiment, the first element 2 can comprise a substrate, such as a wafer, that has a thickness of at least 500 microns, at least 600 microns, at least 700 microns, or at least 750 microns e.g., about 725 microns or about 775 microns for a 300 mm wafer nominal thickness. In other embodiments, the second element 3 can have a greater thickness than the first element 2. In the arrangement of
As shown in the left hand side of
As shown in the right hand side of
As explained herein, the residual stress in the layer 5b can cause the element 3′ in wafer form to be bowed or warped. Compressive stresses in the bonding layer 5b can induce the curvature shown in
For example, as shown in
As shown in
Although the pads 4a, 4b at the peripheral portion 31 are misaligned, other sets of pads 4a, 4b at an inner portion 30 of the second element 3 may be adequately aligned so as to form reliable electrical contacts, e.g., aligned pad pairs 9a. Because the die growth is amplified at the peripheral portions (including at diagonally-oriented positions of the wafer) 31, pad pairs 9a in the inner portion 30 may experience little or no misalignment. In the illustration of
Accordingly, it can be important to predict the amount of warpage due to thickness differentials between the first and second elements 2, 3, and to control and/or compensate for this warpage in order to ensure electrical connectivity across the bonded structure 1. For example, the skilled artisan can use the Stoney equation to model the warpage in the second element 3 due to residual stresses in the layer 5b, accounting for the final thickness of the second element 3 after thinning. As explained above, analytical or numerical models and/or experimentation can be used to account for, e.g., wafer or die thickness, bond energy, bond initiation force, and other factors to provide an estimate of the degree of stretching of the second element 3 in singulated form.
Thus, in various embodiments, the amount of warpage of the second element 3′ in wafer form can be determined based on a number of factors as explained above. Based on the amount of warpage of the second element 3′ in wafer form, the runout of the second element 3 in singulated form (e.g., as a die) can be determined. Based on the estimated runout, the misalignment distances d between opposing pads 4a, 4b of the bonded structure 1 can be determined. Without compensating for this runout, as explained above, misaligned pad pairs 9b may not form electrical connections.
Various embodiments disclosed herein compensate for contact pad misalignment that results from differential expansion of the first and second semiconductor elements 2, 3 due to their differential thicknesses (e.g., T2 being different from T1). Beneficially, various embodiments can compensate for these misalignments during wafer fabrication of the first or second elements 2′, 3′ in wafer form. For example, in some embodiments, a lithographic magnification correction factor F can be derived from the differential expansion of the first and second semiconductor elements 2, 3 due to the differential thicknesses. The lithographic magnification correction factor F can comprise a scale factor by which the magnification of the lithographic system can be adjusted when performing lithography on the first or second element 2′, 3′. Beneficially, the magnification can be adjusted during lithography without modifying any hardware. In other embodiments, the lithographic magnification correction factor F can be implemented by creating a new mask for the first or second element 2, 3 that compensates for the runout and misalignment. The correction factor F may be for the bonding surface only, or for a plurality of (e.g., 2-3) layers near the bonding surface, depending on the magnitude of change sought for the particular pair (e.g., a 200 micron die bonding to a 725 micron thick wafer may only utilize lithographic compensation in the bonding layer, whereas a 25 micron die bonding to a 725 micron thick wafer will have more runout and may utilize compensation in multiple (e.g., 2-3) metal layers.
Once the lithographic magnification correction factor F has been determined based on the final die thicknesses and materials stack, the first element 2′ or the second element 3′ in wafer form can be patterned with the lithography process, using appropriate magnification based on the determined lithographic magnification correction factor F. In some embodiments, the lithographic magnification correction factor F can be applied to the first element 2′, but not the second element 3′. In such embodiments, the lithographic magnification correction factor F can serve to enlarge the pads 4a and pitches p of the singulated first element 2 by the lithographic magnification correction factor F to align with the pads 4b of the stretched second element 3 during bonding. In other embodiments, the lithographic magnification correction factor F can be applied to the second element 3′, but not the first element 2′. In such embodiments, the lithographic magnification correction factor F can serve to shrink the pads 4b and pitches p of the second element 3′ in wafer form by the lithographic magnification correction factor F such that, after thinning, the stretching of the pads 4b and pitches p of the second element 3 will expand by the determined amount to align with the pads 4a of the unmodified first element 2.
Accordingly, in various embodiments, a plurality of first contact pads 4a (also referred to herein as contact features) can be patterned on the first semiconductor element 2′ in wafer form. A plurality of second contact pads 4b can be patterned on the second semiconductor element 3′ in wafer form. To compensate for the differential expansion due to different thicknesses, the lithographic magnification correction factor F can be applied to one of the first patterning of the first element 2′ and the second patterning of the second element 3′ without applying the lithographic magnification correction factor to the other of the first patterning and the second patterning. It should be appreciated that, although the lithographic magnification correction factor F is only applied to one element and not the other element, other scaling or correction factors may be applied to the patterning of the first and/or second elements 2′, 3′ based on other factors. In some embodiments, respective corrective magnification factors F can be applied to both elements 2′, 3′ to compensate for differential expansion. As an example, a first correction factor F can be applied to the patterning of the first element 2′ as a first partial compensation and a second correction factor F can be applied to the patterning of the second element 3′ as a second partial compensation. The first partial compensation can serve to enlarge the features of the first element 2′, and the second partial compensation can serve to shrink the features of the second element 3′ such that the combined effect of the first and second partial compensations is that the pads 4a, 4b are aligned when bonded. Accordingly, the lithographic magnification correction factor F described here can serve as a modification factor that applied to the first and/or second elements 2′, 3′ that modifies the pattern of that element to compensate for differential thicknesses.
After the elements 2′, 3′ in wafer form have been patterned and suitably processed, the second element 3′ can be thinned to the second thickness T2, for example, by etching, grinding, etc. The first element 2′ may or may not be thinned to the first thickness T1, which is greater than the second thickness T2. The second element 3′ in wafer form may then be singulated into a plurality of singulated second elements 3 (e.g., device dies). The first element 2′ may also be singulated in some embodiments, or may remain in wafer form. As used herein, the first element 2 is shown as being a singulated element, but it should be appreciated that the first element 2 may instead remain in wafer form.
It should be appreciated that, in some embodiments, multiple elements (in addition to the second element 3) may be mounted and directly bonded to the first element 2. For example, additional semiconductor elements (e.g., dies) may be laterally spaced apart along the first element 2. In such embodiments, additional correction factor(s) F can be applied to one of the additional elements and the first element 2. The additional correction factor(s) F can be different from the correction factor F applied to the bonding of the first and second elements 2, 3. Additionally or alternatively, one or more additional semiconductor elements can be mound and/or directly bonded on the second semiconductor element 3. In such embodiments, a correction factor F can be applied to one of the additional elements and the second element 3. The correction factors F may be different for the different elements.
As a result of applying the lithographic magnification correction factor F to the first or second element 2, 3, the contact pads 4a, 4b of the bonded structure 1 may be aligned such that there is electrical connectivity across the bonded structure.
In
In various embodiments, the contact pads 4a of the first semiconductor element 2 can have generally uniform feature sizes, and contact pads 4b of the second semiconductor element 3 can have generally uniform feature sizes. In various embodiments, the pitches p of the pads 4a, 4b can be generally uniform. In various embodiments, each of the first and second pluralities of contact pads 4a, 4b can have at least two contact pads 4a or 4b that are of different size and/or shape.
It should be further appreciated that the die bow is affected by not only the stress in the film (e.g., the bonding layer 5b), but also the thickness of the layer 5b. The combined effect of stress and thickness in the layer 5b can affect the magnitude of the wafer bow, which in turn determines the runout when the wafer is thinned and singulated.
Thus, in various embodiments, the lithographic magnification correction factor F can be determined by experimental measurement and/or analytical or numerical models. The correction factor F can be a function of die surface stress and die thickness T2. The factor F can apply a simple linear correction without requiring modifications to hardware systems. The disclosed embodiments are well-suited for single-sided die with manageable die bow after thinning and singulation. However, if the die warpage is too high for direct hybrid bonding, then as explained below, a differential expansion compensation structure 40 can be provided in or on the second element 3. As explained below, the differential expansion compensation structures 40 may comprise one or multiple dielectric layers on the back side 15 of the element 3, or embedded in the element 3. To reduce pad misalignments, the lithographic magnification correction factor F can also compensate for the presence of additional structure from the differential expansion compensation structure (e.g., by experimentation and/or analytical or numerical modeling). For example, experimentation and/or modeling can account for any changes in runout caused by the presence of the differential expansion compensation structure 40.
Accordingly, as explained herein, the material stack (e.g., the combination of nonconductive and/or metallic layers) on both sides of the second element 3 can affect the amount of residual stress and, hence, the degree of warpage and runout in the element 3. The balance of the layers on each side of the semiconductor portion 6b, the materials of the layers, and the total thickness of the semiconductor or device portion 6b (e.g., silicon) may also affect the warpage and the degree of further correction. In some embodiments, the use of the lithographic correction factor F can be applied to the patterning of the first or second elements 2, 3 to substantially correct for misalignments. In such embodiments in which the correction factor F is sufficient to correct for misalignments, no separate differential expansion structure 40 may be provided. In other embodiments, the differential expansion structure 40 may sufficiently correct for misalignments, such that no lithographic correction factor F is applied to the patterning before bonding. In still other embodiments, the lithographic correction factor F can be applied to the first or second elements 2, 3, and a differential expansion structure 40 may also be used on the second element 3. In such embodiments, using a physical mechanism (such as the differential expansion structure 40) to physically reduce warpage in combination with a lithographic correction factor F can beneficially substantially reduce or eliminate runout and contact pad misalignment.
Further as shown in
In various embodiments, the bonded structure 1 may include a signature indicative of the hydrogen diffusion process, e.g., the differential expansion compensation structure 40. For example, skilled artisans would understand that barrier layers may be provided before depositing damascene or non-damascene contact pads (e.g., copper pads) and when forming other conductive structures. The barrier layers can serve to prevent diffusion of the copper into the neighboring non-conductive material(s). For example, the barrier layer(s) can include materials such as titanium nitride, tantalum nitride, etc. In some barrier layer(s), the hydrogen from the plasma 16 may be adsorbed into the barrier layer(s). For example, for non-stoichiometric Ti- and Ta-based barrier layers, hydride may be present in the barrier layer(s) in the bonded structure 1. Accordingly, in various embodiments, the differential expansion compensation structure 40 can comprise a signature indicative of hydrogen ion presence in the barrier layer of the bonded element 3, 3′ for example, as a result of the plasma 16.
The amount of alignment runout can be reduced appreciably for the element 3d with embedded layer 17. For some elements 3d, the differential expansion compensation structure 40 may reduce the warpage such that the runout does not cause sufficient misalignment so as to prevent electrical connections between misaligned pads 4a, 4b. In some embodiments, although the differential expansion compensation structure 40 is effective in reducing runout and misalignment, it may be beneficial to additionally apply the lithographic magnification correction factor F to further reduce misalignment. In such embodiments, the correction factor F can be determined based on the element 3d with the embedded dielectric layer 17 so that the correction factor F accounts for any changes in runout caused by the presence of the dielectric layer 17.
Turning to
Turning to
Turning to
In
Accordingly, various embodiments disclosed herein can utilize one or more of a lithographic magnification correction factor F and a differential expansion compensation structure 40 to compensate for thermal expansion and reduce misalignments between opposing contact pads 4a, 4b. For example, the use of the correction factor F and/or the compensation structure(s) 40 can ensure that at least 85%, at least 90%, at least 95%, or at least 99% of all contact pad pairs 9a in the bonded structure 1 are aligned and make electrical contact across the bond interface 7. As another example, in an uncompensated bonded structure, a radially-outermost misaligned pad pair 9b in the peripheral portion 31 may have an uncompensated center-to-center separation distance duc due to thermal expansion and corresponding runout. Beneficially, the use of the correction factor F and/or the compensation structure 40 can reduce the separation distance d to a compensated separation distance dc to be within a range of 0% to 20%, 0% to 15%, 0% to 10%, 0% to 5%, 0.1% to 10%, 0.1% to 5%, or 0.5% to 5% of the uncompensated separation distance duc.
In one embodiment, a method of direct hybrid bonding first and second semiconductor elements of differential thickness is disclosed. The method can include: obtaining a lithographic magnification correction factor derived from differential expansion of the first and second semiconductor elements due to the differential thicknesses; first patterning a plurality of first contact features on the first semiconductor element; second patterning a plurality of second contact features on the second semiconductor element corresponding to the first contact features for direct hybrid bonding; and applying the lithographic magnification correction factor to one of the first patterning and second patterning without applying the lithographic magnification correction factor to the other of the first patterning and the second patterning.
In some embodiments, the method comprises thinning the second semiconductor element to produce the differential thickness; and subsequently direct hybrid bonding the first semiconductor element to the second semiconductor element, including directly bonding nonconductive layers of the first and second semiconductor elements and directly bonding the first contact features with the corresponding second contact features. In some embodiments, the method comprises providing a differential expansion compensation structure on the second semiconductor element, the differential expansion compensation structure configured to compensate for differential expansion between the first and second semiconductor elements to reduce misalignment between opposing contact features. In some embodiments, providing the differential expansion compensation structure comprises providing one or more dielectric layers on a back side of the second semiconductor element, the back side opposite the second bonding surface. In some embodiments, the one or more dielectric layers comprises a compressive layer configured to counterbalance stresses on the nonconductive layer of the second semiconductor element. In some embodiments, the one or more dielectric layers comprises a plurality of dielectric layers. In some embodiments, the plurality of dielectric layers comprises a first dielectric layer on the back side of the second semiconductor element and a second dielectric layer on a third semiconductor element, and wherein providing the differential expansion compensation structure comprises directly bonding the second dielectric layer to the first dielectric layer without an adhesive. In some embodiments, the plurality of dielectric layers comprises a first dielectric layer and a second dielectric layer, and wherein providing the differential expansion compensation structure comprises providing a metal layer between the first and second dielectric layers. In some embodiments, providing the differential expansion compensation structure comprises diffusing hydrogen ions in the second semiconductor element. In some embodiments, the method comprises heating and applying a vacuum to the bonded first and second elements to remove the hydrogen ions. In some embodiments, diffusing hydrogen ions comprises exposing the second semiconductor element to a hydrogen-containing plasma. In some embodiments, providing the differential expansion compensation structure comprises patterning a metal layer in the nonconductive layer of at least one of the first and second semiconductor elements. In some embodiments, providing the differential expansion compensation structure comprises adjusting a temperature difference between the first semiconductor element and the second semiconductor element during the direct hybrid bonding. In some embodiments, the first semiconductor element is thicker than the second semiconductor element, the method comprising applying the lithographic magnification correction factor to the first patterning, wherein the application of the lithographic magnification correction factor enlarges the first contact features of the first semiconductor element relative to the corresponding second contact features of the second semiconductor element. In some embodiments, the application of the lithographic magnification correction factor enlarges first spacings between adjacent first contact features relative to corresponding second spacings between adjacent second contact features. In some embodiments, the first semiconductor element is thicker than the second semiconductor element, the method comprising applying the lithographic magnification correction factor to the second patterning, wherein the application of the lithographic magnification correction factor shrinks the second contact features of the second semiconductor element relative to the corresponding first contact features of the first semiconductor element. In some embodiments, the application of the lithographic magnification correction factor shrinks second spacings between adjacent second contact features relative to corresponding first spacings between adjacent first contact features. In some embodiments, the method comprises applying the lithographic magnification correction factor to the first patterning and applying a second lithographic magnification correction factor to the second patterning, the second lithographic magnification correction factor different from the lithographic magnification correction factor. In some embodiments, the method comprises applying the lithographic magnification correction to the first patterning, performing the first patterning with the first semiconductor element in wafer form, thinning the first semiconductor element, and singulating the first semiconductor element into a plurality of singulated semiconductor elements. In some embodiments, the method comprises direct hybrid bonding a third semiconductor element to the second semiconductor element, the third semiconductor element laterally spaced from the first semiconductor element and having a thickness different from the first semiconductor element. In some embodiments, the method comprises applying a second lithographic magnification correction factor to one of the second and third semiconductor elements, but not the other of the second and third semiconductor elements.
In another embodiment, a method of bonding a first semiconductor element and a second semiconductor element is disclosed. The method can include: providing a first semiconductor element; providing a second semiconductor element; obtaining a lithographic magnification correction factor to compensate for differential expansion between the first and second semiconductor elements if the first and second semiconductor elements are bonded together when the first semiconductor element has a first thickness and the second semiconductor element has a second thickness less than the first thickness; patterning a first plurality of first contact features on a first bonding surface of the first semiconductor element; patterning a second plurality of second contact pads on a second bonding surface of the second semiconductor element; and with the first semiconductor element having the first thickness and the second semiconductor element having the second thickness, bonding the second plurality of second contact pads to the first plurality of first contact pads; wherein the lithographic magnification correction factor is applied to one of but not the other of the patterning of the first and second contact features.
In some embodiments, the lithographic magnification correction is applied to the patterning of the first contact features, such that the first contact features are larger than corresponding second contact features. In some embodiments, the lithographic magnification correction is applied to the patterning of the second contact features, such that the second contact features are smaller than corresponding first contact features. In some embodiments, the bonding comprises directly bonding without an intervening adhesive. In some embodiments, the method comprises providing a differential expansion compensation structure on at least one of the first semiconductor element and the second semiconductor element, the differential expansion compensation structure configured to compensate for differential expansion between the first and second semiconductor elements to reduce misalignment between opposing contact features.
In another embodiment, a bonded structure is disclosed. The bonded structure can include: a first semiconductor element having a first bonding surface, the first bonding surface including a first contact feature at an inner portion of the first semiconductor element and a second contact feature spaced apart from the first contact feature at a peripheral portion of the first semiconductor element, the first element having a first thickness; and a second semiconductor element having a second bonding surface bonded to the first bonding surface of the first semiconductor element, the second bonding surface having a third contact feature at an inner portion of the second semiconductor element and a fourth contact feature spaced apart from the third contact feature at a peripheral portion of the second semiconductor element, the second semiconductor element having a second thickness, wherein the first contact feature is aligned with and bonded to the third contact feature, wherein the second contact feature is aligned with and bonded to the fourth contact feature, and wherein the first and second contact features are larger than the third and fourth contact features.
In some embodiments, a width of the first contact feature is no more than 10% larger than a width of the third contact feature. In some embodiments, a width of the first contact feature is no more than 5% larger than a width of the third contact feature. In some embodiments, a width of the first contact feature is no more than 1% larger than a width of the third contact feature. In some embodiments, prior to bonding, the first thickness is larger than the second thickness. In some embodiments, the first and second semiconductor elements are directly hybrid bonded to one another without an adhesive. In some embodiments, the first semiconductor element includes a first plurality of contact features having uniform feature sizes, and wherein the second semiconductor element includes a second plurality of contact features having uniform feature sizes. In some embodiments, the first and second pluralities of contact features have respective uniform pitches. In some embodiments, the first semiconductor element includes a first plurality of contact features, and wherein the second semiconductor element includes a second plurality of contact features, each of the first and second pluralities of contact features having at least two contact features that are of different size and/or shape. In some embodiments, the bonded structure can include a differential expansion compensation structure on at least one of the first and the second semiconductor elements, the differential expansion compensation structure configured to compensate for differential expansion between the first and second semiconductor elements to reduce misalignment between the second and fourth contact features. In some embodiments, the differential expansion compensation structure comprises one or more dielectric layers on a back side of the second semiconductor element, the back side opposite the second bonding surface. In some embodiments, the differential expansion compensation structure further comprises a third semiconductor element, wherein the one or more dielectric layers comprises a first dielectric layer on the back side of the second semiconductor element and a second dielectric layer on the third semiconductor element, the first and second dielectric layers directly bonded to one another without an adhesive. In some embodiments, the first and second dielectric layers are embedded between a first semiconductor portion of the second element and a second semiconductor portion of the third element. In some embodiments, the second element comprises a compound semiconductor layer on a carrier dielectric layer, the compound semiconductor layer disposed between the second bonding surface and the carrier dielectric layer. In some embodiments, the carrier dielectric layer is disposed on a carrier substrate layer, a backside dielectric layer of the carrier substrate layer being directly bonded to a bonding surface of a third element. In some embodiments, the one or more dielectric layers comprises a first dielectric layer and a second dielectric layer, the differential expansion compensation structure further comprising a metal layer between the first and second dielectric layers. In some embodiments, the differential expansion compensation structure comprises a signature indicative of hydrogen ion diffusion into the second semiconductor element. In some embodiments, the differential expansion compensation structure comprises a patterned metal layer on at least one of the first bonding surface and the second bonding surface.
In another embodiment, a bonded structure is disclosed. The bonded structure can include a first semiconductor element having a first bonding surface, the first bonding surface including a first contact feature at an inner portion of the first semiconductor element and a second contact feature at a peripheral portion of the first semiconductor element, the first element having a first thickness; a second semiconductor element having a second bonding surface bonded to the first bonding surface of the first semiconductor element, the second bonding surface having a third contact feature at an inner portion of the second semiconductor element and a fourth contact feature at a peripheral portion of the second semiconductor element, the second semiconductor element having a second thickness, wherein the first contact feature is bonded to the third contact feature, and wherein the second contact feature is bonded to the fourth contact feature; and a differential expansion compensation structure on at least one of the first and the second semiconductor elements, the differential expansion compensation structure configured to compensate for differential expansion between the first and second semiconductor elements to reduce misalignment between at least the second and fourth contact features.
In some embodiments, the second thickness is less than the first thickness at least before the first and second elements are bonded. In some embodiments, the first and second semiconductor elements are directly bonded without an intervening adhesive. In some embodiments, the differential expansion compensation structure comprises one or more dielectric layers on a back side of the second semiconductor element, the back side opposite the second bonding surface. In some embodiments, the one or more dielectric layers comprises a stressed layer configured to counterbalance stresses at or near the second bonding surface. In some embodiments, the one or more dielectric layers comprises a plurality of dielectric layers. In some embodiments, the differential expansion compensation structure further comprises a third semiconductor element, wherein the plurality of dielectric layers comprises a first dielectric layer on the back side of the second semiconductor element and a second dielectric layer on the third semiconductor element, the first and second dielectric layers directly bonded to one another without an adhesive. In some embodiments, the second and third semiconductor elements having different coefficients of thermal expansion. In some embodiments, the first and second dielectric layers are embedded between a first semiconductor portion of the second element and a second semiconductor portion of the third element. In some embodiments, the second element comprises a compound semiconductor layer on a carrier dielectric layer, the compound semiconductor layer disposed between the second bonding surface and the carrier dielectric layer. In some embodiments, the carrier dielectric layer is disposed on a carrier substrate layer, a backside dielectric layer of the carrier substrate layer being directly bonded to a bonding surface of a third element. In some embodiments, the plurality of dielectric layers comprises a first dielectric layer and a second dielectric layer, the differential expansion compensation structure further comprising a metal layer between the first and second dielectric layers. In some embodiments, the differential expansion compensation structure comprises one or more dicing street etches in at least one of the first and the second semiconductor elements. In some embodiments, the differential expansion compensation structure comprises a signature indicative of hydrogen ion diffusion into the second semiconductor element. In some embodiments, the differential expansion compensation structure comprises a patterned metal layer on at least one of the first bonding surface and the second bonding surface.
In another embodiment, a method of bonding a first element and a second element is disclosed. The method can include: providing a first semiconductor element having a first bonding surface, the first bonding surface including a first contact feature at an inner portion of the first semiconductor element and a second contact feature at a peripheral portion of the first semiconductor element, the first element having a first thickness; providing a second semiconductor element having a second bonding surface, the second bonding surface having a third contact feature at an inner portion of the second semiconductor element and a fourth contact feature at a peripheral portion of the second semiconductor element, the second semiconductor element having a second thickness less than the first thickness; bonding the first bonding surface to the second bonding surface such that the first contact feature is bonded to the third contact feature and the second contact feature is bonded to the fourth contact feature; and providing a differential expansion compensation structure on at least one of the first and second elements, the differential expansion compensation structure configured to compensate for differential expansion between the first and second semiconductor elements to reduce misalignment between at least the second and fourth contact features.
In some embodiments, the bonding comprises directly bonding without an intervening adhesive. In some embodiments, providing the differential expansion compensation structure comprises providing one or more dielectric layers on a back side of the second semiconductor element, the back side opposite the second bonding surface. In some embodiments, the one or more dielectric layers comprises a compressive layer configured to counterbalance stresses at or near the second bonding surface. In some embodiments, the one or more dielectric layers comprises a plurality of dielectric layers. In some embodiments, the plurality of dielectric layers comprises a first dielectric layer on the back side of the second semiconductor element and a second dielectric layer on a third semiconductor element, and wherein providing the differential expansion compensation structure comprises directly bonding the second dielectric layer to the first dielectric layer without an adhesive. In some embodiments, the plurality of dielectric layers comprises a first dielectric layer and a second dielectric layer, and wherein providing the differential expansion compensation structure comprises providing a metal layer between the first and second dielectric layers. In some embodiments, providing the differential expansion compensation structure comprises forming one or more dicing street etches in at least one of the first and the second semiconductor elements. In some embodiments, providing the differential expansion compensation structure comprises diffusing hydrogen ions into the second semiconductor element. In some embodiments, applying a vacuum to the bonded first and second elements to remove the hydrogen ions. In some embodiments, diffusing hydrogen ions comprises exposing the second element to a hydrogen-containing plasma. In some embodiments, providing the differential expansion compensation structure comprises patterning a metal layer on at least one of the first bonding surface and the second bonding surface. In some embodiments, providing the differential expansion compensation structure comprises adjusting a temperature difference between the first element and the second element during the bonding. In some embodiments, the method can include before the bonding, obtaining a lithographic magnification correction factor to compensate for differential expansion between the first and second semiconductor elements at their different thicknesses at the time of bonding; first patterning a first plurality of contact features on the first semiconductor element; second patterning a second plurality of contact features on the second semiconductor element; and applying the lithographic magnification correction factor to one of the first patterning and second patterning without applying the lithographic magnification correction factor to the other of the first patterning and the second patterning.
In another embodiment, a method of compensating for lithographic runout of an element is disclosed. The method can include: providing a first semiconductor element having a first bonding surface; and exposing the first semiconductor element to hydrogen ions to control the runout of the first semiconductor element.
In some embodiments, the first semiconductor element has a first bonding surface including a first contact feature at an inner portion of the first semiconductor element and a second contact feature at a peripheral portion of the first semiconductor element, the first element having a thickness smaller than a lateral dimension of the first semiconductor element. In some embodiments, exposing the first semiconductor element to hydrogen ions comprises exposing the first semiconductor element to a hydrogen plasma.
Unless the context clearly requires otherwise, throughout the description and the claims, the words “comprise,” “comprising,” “include,” “including” and the like are to be construed in an inclusive sense, as opposed to an exclusive or exhaustive sense; that is to say, in the sense of “including, but not limited to.” The word “coupled”, as generally used herein, refers to two or more elements that may be either directly connected, or connected by way of one or more intermediate elements. Likewise, the word “connected”, as generally used herein, refers to two or more elements that may be either directly connected, or connected by way of one or more intermediate elements. Additionally, the words “herein,” “above,” “below,” and words of similar import, when used in this application, shall refer to this application as a whole and not to any particular portions of this application. Moreover, as used herein, when a first element is described as being “on” or “over” a second element, the first element may be directly on or over the second element, such that the first and second elements directly contact, or the first element may be indirectly on or over the second element such that one or more elements intervene between the first and second elements. Where the context permits, words in the above Detailed Description using the singular or plural number may also include the plural or singular number respectively. The word “or” in reference to a list of two or more items, that word covers all of the following interpretations of the word: any of the items in the list, all of the items in the list, and any combination of the items in the list.
Moreover, conditional language used herein, such as, among others, “can,” “could,” “might,” “may,” “e.g.,” “for example,” “such as” and the like, unless specifically stated otherwise, or otherwise understood within the context as used, is generally intended to convey that certain embodiments include, while other embodiments do not include, certain features, elements and/or states. Thus, such conditional language is not generally intended to imply that features, elements and/or states are in any way required for one or more embodiments.
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the disclosure. Indeed, the novel apparatus, methods, and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the disclosure. For example, while blocks are presented in a given arrangement, alternative embodiments may perform similar functionalities with different components and/or circuit topologies, and some blocks may be deleted, moved, added, subdivided, combined, and/or modified. Each of these blocks may be implemented in a variety of different ways. Any suitable combination of the elements and acts of the various embodiments described above can be combined to provide further embodiments. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the disclosure.
This application claims priority to U.S. Provisional Patent Application No. 62/991,775, filed Mar. 19, 2020, the entire contents of which are hereby incorporated by reference in their entirety and for all purposes.
Number | Name | Date | Kind |
---|---|---|---|
3175025 | Geen et al. | Mar 1965 | A |
3423823 | Ansley | Jan 1969 | A |
4612083 | Yasumoto et al. | Sep 1986 | A |
4818728 | Rai et al. | Apr 1989 | A |
5451547 | Himi et al. | Sep 1995 | A |
5668057 | Eda et al. | Sep 1997 | A |
5747857 | Eda et al. | May 1998 | A |
5753536 | Sugiyama et al. | May 1998 | A |
5771555 | Eda et al. | Jun 1998 | A |
5773836 | Hartley | Jun 1998 | A |
6080640 | Gardner et al. | Jun 2000 | A |
6180496 | Farrens et al. | Jan 2001 | B1 |
6423640 | Lee et al. | Jul 2002 | B1 |
6465892 | Suga | Oct 2002 | B1 |
6495398 | Goetz | Dec 2002 | B1 |
6502271 | Epshteyn | Jan 2003 | B1 |
6645828 | Farrens et al. | Nov 2003 | B1 |
6877209 | Miller et al. | Apr 2005 | B1 |
6887769 | Kellar et al. | May 2005 | B2 |
6908027 | Tolchinsky et al. | Jun 2005 | B2 |
6908832 | Farrens et al. | Jun 2005 | B2 |
7037804 | Kellar et al. | May 2006 | B2 |
7045453 | Canaperi et al. | May 2006 | B2 |
7105980 | Abbott et al. | Sep 2006 | B2 |
7109092 | Tong | Sep 2006 | B2 |
7126212 | Enquist et al. | Oct 2006 | B2 |
7192841 | Wei et al. | Mar 2007 | B2 |
7193423 | Dalton et al. | Mar 2007 | B1 |
7213314 | Abbott et al. | May 2007 | B2 |
7230512 | Carpenter et al. | Jun 2007 | B1 |
7335572 | Tong et al. | Feb 2008 | B2 |
7466022 | Miller et al. | Dec 2008 | B2 |
7602070 | Tong et al. | Oct 2009 | B2 |
7750488 | Patti et al. | Jul 2010 | B2 |
7803693 | Trezza | Sep 2010 | B2 |
8035464 | Abbott et al. | Oct 2011 | B1 |
8183127 | Patti et al. | May 2012 | B2 |
8349635 | Gan et al. | Jan 2013 | B1 |
8377798 | Peng et al. | Feb 2013 | B2 |
8441131 | Ryan | May 2013 | B2 |
8476165 | Trickett et al. | Jul 2013 | B2 |
8482132 | Yang et al. | Jul 2013 | B2 |
8501537 | Sadaka et al. | Aug 2013 | B2 |
8524533 | Tong et al. | Sep 2013 | B2 |
8620164 | Heck et al. | Dec 2013 | B2 |
8647987 | Yang et al. | Feb 2014 | B2 |
8697493 | Sadaka | Apr 2014 | B2 |
8716105 | Sadaka et al. | May 2014 | B2 |
8735219 | Enquist et al. | May 2014 | B2 |
8802538 | Liu | Aug 2014 | B1 |
8809123 | Liu et al. | Aug 2014 | B2 |
8975158 | Plach et al. | Mar 2015 | B2 |
8988299 | Kam et al. | Mar 2015 | B2 |
9093350 | Endo et al. | Jul 2015 | B2 |
9142517 | Liu et al. | Sep 2015 | B2 |
9171756 | Enquist et al. | Oct 2015 | B2 |
9184125 | Enquist et al. | Nov 2015 | B2 |
9224704 | Landru | Dec 2015 | B2 |
9230941 | Chen et al. | Jan 2016 | B2 |
9257399 | Kuang et al. | Feb 2016 | B2 |
9299736 | Chen et al. | Mar 2016 | B2 |
9312229 | Chen et al. | Apr 2016 | B2 |
9331149 | Tong et al. | May 2016 | B2 |
9337235 | Chen et al. | May 2016 | B2 |
9368866 | Yu | Jun 2016 | B2 |
9385024 | Tong et al. | Jul 2016 | B2 |
9394161 | Cheng et al. | Jul 2016 | B2 |
9437572 | Chen et al. | Sep 2016 | B2 |
9443796 | Chou et al. | Sep 2016 | B2 |
9461007 | Chun et al. | Oct 2016 | B2 |
9496239 | Edelstein et al. | Nov 2016 | B1 |
9536848 | England et al. | Jan 2017 | B2 |
9559081 | Lai et al. | Jan 2017 | B1 |
9620481 | Edelstein et al. | Apr 2017 | B2 |
9656852 | Cheng et al. | May 2017 | B2 |
9698126 | Enquist et al. | Jul 2017 | B2 |
9723716 | Meinhold | Aug 2017 | B2 |
9728521 | Tsai et al. | Aug 2017 | B2 |
9741620 | Uzoh et al. | Aug 2017 | B2 |
9799587 | Fujii et al. | Oct 2017 | B2 |
9852988 | Enquist et al. | Dec 2017 | B2 |
9881882 | Hsu et al. | Jan 2018 | B2 |
9893004 | Yazdani | Feb 2018 | B2 |
9899442 | Katkar | Feb 2018 | B2 |
9929050 | Lin | Mar 2018 | B2 |
9941241 | Edelstein et al. | Apr 2018 | B2 |
9941243 | Kim et al. | Apr 2018 | B2 |
9953941 | Enquist | Apr 2018 | B2 |
9960142 | Chen et al. | May 2018 | B2 |
10002844 | Wang et al. | Jun 2018 | B1 |
10026605 | Doub et al. | Jul 2018 | B2 |
10075657 | Fahim et al. | Sep 2018 | B2 |
10177735 | Ruby et al. | Jan 2019 | B2 |
10204893 | Uzoh et al. | Feb 2019 | B2 |
10269756 | Uzoh | Apr 2019 | B2 |
10276619 | Kao et al. | Apr 2019 | B2 |
10276909 | Huang et al. | Apr 2019 | B2 |
10418277 | Cheng et al. | Sep 2019 | B2 |
10446456 | Shen et al. | Oct 2019 | B2 |
10446487 | Huang et al. | Oct 2019 | B2 |
10446532 | Uzoh et al. | Oct 2019 | B2 |
10454447 | Solal et al. | Oct 2019 | B2 |
10508030 | Katkar et al. | Dec 2019 | B2 |
10522499 | Enquist et al. | Dec 2019 | B2 |
10707087 | Uzoh et al. | Jul 2020 | B2 |
10727219 | Uzoh et al. | Jul 2020 | B2 |
10784191 | Huang et al. | Sep 2020 | B2 |
10790262 | Uzoh et al. | Sep 2020 | B2 |
10840135 | Uzoh | Nov 2020 | B2 |
10840205 | Fountain, Jr. et al. | Nov 2020 | B2 |
10854578 | Morein | Dec 2020 | B2 |
10879212 | Uzoh et al. | Dec 2020 | B2 |
10886177 | DeLaCruz et al. | Jan 2021 | B2 |
10892246 | Uzoh | Jan 2021 | B2 |
10923408 | Huang et al. | Feb 2021 | B2 |
10923413 | DeLaCruz | Feb 2021 | B2 |
10950547 | Mohammed et al. | Mar 2021 | B2 |
10964664 | Mandalapu et al. | Mar 2021 | B2 |
10985133 | Uzoh | Apr 2021 | B2 |
10991804 | DeLaCruz et al. | Apr 2021 | B2 |
10998292 | Lee et al. | May 2021 | B2 |
11011494 | Gao et al. | May 2021 | B2 |
11011503 | Wang et al. | May 2021 | B2 |
11031285 | Katkar et al. | Jun 2021 | B2 |
11037919 | Uzoh et al. | Jun 2021 | B2 |
11056348 | Theil | Jul 2021 | B2 |
11069734 | Katkar | Jul 2021 | B2 |
11088099 | Katkar et al. | Aug 2021 | B2 |
11127738 | DeLaCruz et al. | Sep 2021 | B2 |
11158606 | Gao et al. | Oct 2021 | B2 |
11171117 | Gao et al. | Nov 2021 | B2 |
11176450 | Teig et al. | Nov 2021 | B2 |
11222863 | Hua et al. | Jan 2022 | B2 |
11256004 | Haba et al. | Feb 2022 | B2 |
11264357 | DeLaCruz et al. | Mar 2022 | B1 |
11276676 | Enquist et al. | Mar 2022 | B2 |
11329034 | Tao et al. | May 2022 | B2 |
11348898 | DeLaCruz et al. | May 2022 | B2 |
11355443 | Huang et al. | Jun 2022 | B2 |
11631586 | Enquist et al. | Apr 2023 | B2 |
11664357 | Fountain, Jr. et al. | May 2023 | B2 |
20010037995 | Akatsu et al. | Nov 2001 | A1 |
20020030198 | Coman et al. | Mar 2002 | A1 |
20020048900 | Lo et al. | Apr 2002 | A1 |
20020068396 | Fitzergald | Jun 2002 | A1 |
20030022412 | Higgins et al. | Jan 2003 | A1 |
20030030119 | Higgins, Jr. et al. | Feb 2003 | A1 |
20040084414 | Sakai et al. | May 2004 | A1 |
20060057945 | Hsu et al. | Mar 2006 | A1 |
20060076559 | Faure et al. | Apr 2006 | A1 |
20060121696 | Shiota et al. | Jun 2006 | A1 |
20060138907 | Koizumi et al. | Jun 2006 | A1 |
20060199353 | Kub et al. | Sep 2006 | A1 |
20060255341 | Pinnington et al. | Nov 2006 | A1 |
20060273068 | Maunand Tussot et al. | Dec 2006 | A1 |
20060284167 | Augustine et al. | Dec 2006 | A1 |
20070096294 | Ikeda et al. | May 2007 | A1 |
20070111386 | Kim et al. | May 2007 | A1 |
20070222048 | Huang | Sep 2007 | A1 |
20070295456 | Gudeman et al. | Dec 2007 | A1 |
20080061291 | Dusa | Mar 2008 | A1 |
20090004822 | Murakami et al. | Jan 2009 | A1 |
20090042356 | Takayama et al. | Feb 2009 | A1 |
20090068831 | Enquist et al. | Mar 2009 | A1 |
20090191719 | Dupont | Jul 2009 | A1 |
20090321869 | Fukuoka et al. | Dec 2009 | A1 |
20110053339 | Ozawa | Mar 2011 | A1 |
20110128399 | Fujii | Jun 2011 | A1 |
20110290552 | Palmateer et al. | Dec 2011 | A1 |
20120003813 | Chuang et al. | Jan 2012 | A1 |
20120028440 | Castex et al. | Feb 2012 | A1 |
20120077329 | Broekaart | Mar 2012 | A1 |
20120119224 | Tai et al. | May 2012 | A1 |
20120132922 | Arena et al. | May 2012 | A1 |
20120168792 | Kang et al. | Jul 2012 | A1 |
20120183808 | Tong | Jul 2012 | A1 |
20120212384 | Kam et al. | Aug 2012 | A1 |
20120270231 | Smith et al. | Oct 2012 | A1 |
20130130473 | Ben Mohamed et al. | May 2013 | A1 |
20130228775 | Noda et al. | Sep 2013 | A1 |
20140167230 | Kitada et al. | Jun 2014 | A1 |
20140175655 | Chen et al. | Jun 2014 | A1 |
20140225795 | Yu | Aug 2014 | A1 |
20150064498 | Tong | Mar 2015 | A1 |
20150097022 | Di Cioccio et al. | Apr 2015 | A1 |
20160049384 | Lu et al. | Feb 2016 | A1 |
20160181228 | Higuchi et al. | Jun 2016 | A1 |
20160343682 | Kawasaki | Nov 2016 | A1 |
20170036419 | Adib et al. | Feb 2017 | A1 |
20170194271 | Hsu et al. | Jul 2017 | A1 |
20170338143 | Peidous et al. | Nov 2017 | A1 |
20180068965 | Chen et al. | Mar 2018 | A1 |
20180175012 | Wu et al. | Jun 2018 | A1 |
20180182639 | Uzoh et al. | Jun 2018 | A1 |
20180182666 | Uzoh et al. | Jun 2018 | A1 |
20180190580 | Haba et al. | Jul 2018 | A1 |
20180190583 | DeLaCruz et al. | Jul 2018 | A1 |
20180219038 | Gambino et al. | Aug 2018 | A1 |
20180323177 | Yu et al. | Nov 2018 | A1 |
20180323227 | Zhang et al. | Nov 2018 | A1 |
20180331066 | Uzoh et al. | Nov 2018 | A1 |
20190096741 | Uzoh et al. | Mar 2019 | A1 |
20190115277 | Yu et al. | Apr 2019 | A1 |
20190123709 | Inoue et al. | Apr 2019 | A1 |
20190131277 | Yang et al. | May 2019 | A1 |
20190157333 | Tsai | May 2019 | A1 |
20190164919 | Hu et al. | May 2019 | A1 |
20190170631 | Shachar et al. | Jun 2019 | A1 |
20190198409 | Katkar et al. | Jun 2019 | A1 |
20190221607 | Gudeman | Jul 2019 | A1 |
20190265411 | Huang et al. | Aug 2019 | A1 |
20190288660 | Goto et al. | Sep 2019 | A1 |
20190295883 | Yokokawa | Sep 2019 | A1 |
20190333550 | Fisch | Oct 2019 | A1 |
20190348336 | Katkar et al. | Nov 2019 | A1 |
20190385935 | Gao et al. | Dec 2019 | A1 |
20190385966 | Gao et al. | Dec 2019 | A1 |
20200006145 | Li et al. | Jan 2020 | A1 |
20200006266 | Chen et al. | Jan 2020 | A1 |
20200013637 | Haba | Jan 2020 | A1 |
20200013765 | Fountain, Jr. et al. | Jan 2020 | A1 |
20200028486 | Kishino et al. | Jan 2020 | A1 |
20200035641 | Fountain, Jr. et al. | Jan 2020 | A1 |
20200075520 | Gao et al. | Mar 2020 | A1 |
20200075534 | Gao et al. | Mar 2020 | A1 |
20200075553 | DeLaCruz et al. | Mar 2020 | A1 |
20200118973 | Wang et al. | Apr 2020 | A1 |
20200126906 | Uzoh et al. | Apr 2020 | A1 |
20200194396 | Uzoh | Jun 2020 | A1 |
20200227367 | Haba et al. | Jul 2020 | A1 |
20200243380 | Uzoh et al. | Jul 2020 | A1 |
20200279821 | Haba et al. | Sep 2020 | A1 |
20200294908 | Haba et al. | Sep 2020 | A1 |
20200328162 | Haba et al. | Oct 2020 | A1 |
20200328164 | DeLaCruz et al. | Oct 2020 | A1 |
20200328165 | DeLaCruz et al. | Oct 2020 | A1 |
20200328193 | Enquist et al. | Oct 2020 | A1 |
20200335408 | Gao et al. | Oct 2020 | A1 |
20200371154 | DeLaCruz et al. | Nov 2020 | A1 |
20200395321 | Katkar et al. | Dec 2020 | A1 |
20200411483 | Uzoh et al. | Dec 2020 | A1 |
20210098412 | Haba et al. | Apr 2021 | A1 |
20210118864 | DeLaCruz et al. | Apr 2021 | A1 |
20210143125 | DeLaCruz et al. | May 2021 | A1 |
20210181510 | Katkar et al. | Jun 2021 | A1 |
20210193603 | Katkar et al. | Jun 2021 | A1 |
20210193624 | DeLaCruz et al. | Jun 2021 | A1 |
20210193625 | DeLaCruz et al. | Jun 2021 | A1 |
20210242152 | Fountain, Jr. et al. | Aug 2021 | A1 |
20210305202 | Uzoh et al. | Sep 2021 | A1 |
20210366820 | Uzoh | Nov 2021 | A1 |
20210407941 | Haba | Dec 2021 | A1 |
20220005784 | Gao et al. | Jan 2022 | A1 |
20220077063 | Haba | Mar 2022 | A1 |
20220077087 | Haba | Mar 2022 | A1 |
20220139867 | Uzoh | May 2022 | A1 |
20220139869 | Gao et al. | May 2022 | A1 |
20220208650 | Gao et al. | Jun 2022 | A1 |
20220208702 | Uzoh | Jun 2022 | A1 |
20220208723 | Katkar et al. | Jun 2022 | A1 |
20220246497 | Fountain, Jr. et al. | Aug 2022 | A1 |
20220285303 | Mirkarimi et al. | Sep 2022 | A1 |
20220319901 | Suwito et al. | Oct 2022 | A1 |
20220320035 | Uzoh et al. | Oct 2022 | A1 |
20220320036 | Gao et al. | Oct 2022 | A1 |
20230005850 | Fountain, Jr. | Jan 2023 | A1 |
20230019869 | Mirkarimi et al. | Jan 2023 | A1 |
20230036441 | Haba et al. | Feb 2023 | A1 |
20230067677 | Lee et al. | Mar 2023 | A1 |
20230069183 | Haba | Mar 2023 | A1 |
20230100032 | Haba et al. | Mar 2023 | A1 |
20230115122 | Uzoh et al. | Apr 2023 | A1 |
20230122531 | Uzoh | Apr 2023 | A1 |
20230123423 | Gao et al. | Apr 2023 | A1 |
20230125395 | Gao et al. | Apr 2023 | A1 |
20230130259 | Haba et al. | Apr 2023 | A1 |
20230132632 | Katkar et al. | May 2023 | A1 |
20230140107 | Uzoh et al. | May 2023 | A1 |
20230142680 | Guevara et al. | May 2023 | A1 |
20230154816 | Haba et al. | May 2023 | A1 |
20230154828 | Haba et al. | May 2023 | A1 |
20230187264 | Uzoh et al. | Jun 2023 | A1 |
20230187317 | Uzoh | Jun 2023 | A1 |
20230187412 | Gao et al. | Jun 2023 | A1 |
20230197453 | Fountain, Jr. et al. | Jun 2023 | A1 |
20230197496 | Theil | Jun 2023 | A1 |
20230197559 | Haba et al. | Jun 2023 | A1 |
20230197560 | Katkar et al. | Jun 2023 | A1 |
20230197655 | Theil et al. | Jun 2023 | A1 |
20230207322 | Enquist et al. | Jun 2023 | A1 |
20230207402 | Fountain, Jr. et al. | Jun 2023 | A1 |
20230207437 | Haba | Jun 2023 | A1 |
20230207474 | Uzoh et al. | Jun 2023 | A1 |
20230207514 | Gao et al. | Jun 2023 | A1 |
20230215836 | Haba et al. | Jul 2023 | A1 |
20230245950 | Haba et al. | Aug 2023 | A1 |
20230253383 | Fountain, Jr. et al. | Aug 2023 | A1 |
20230268300 | Uzoh et al. | Aug 2023 | A1 |
20230299029 | Theil et al. | Sep 2023 | A1 |
20230343734 | Uzoh et al. | Oct 2023 | A1 |
20230360950 | Gao | Nov 2023 | A1 |
20230361074 | Uzoh et al. | Nov 2023 | A1 |
20230369136 | Uzoh et al. | Nov 2023 | A1 |
20230375613 | Haba et al. | Nov 2023 | A1 |
20240079376 | Suwito et al. | Mar 2024 | A1 |
Number | Date | Country |
---|---|---|
0823780 | Feb 1998 | EP |
0616426 | Sep 1998 | EP |
0591918 | Jul 1999 | EP |
3 482 231 | Sep 2022 | EP |
2 849 268 | Jun 2004 | FR |
2011-200933 | Oct 2011 | JP |
2013-33786 | Feb 2013 | JP |
2018-160519 | Oct 2018 | JP |
10-2015-0097798 | Aug 2015 | KR |
10-2018-0114896 | Oct 2018 | KR |
WO 2005043584 | May 2005 | WO |
WO 2006100444 | Sep 2006 | WO |
WO 2015191082 | Dec 2015 | WO |
WO 2017151442 | Sep 2017 | WO |
WO 2019180922 | Sep 2019 | WO |
Entry |
---|
Shen et al., “Structure and magnetic properties of Ce-substituted yttrium iron garnet prepared by conventional sintering techniques,” J Supercond, 2017, pp. 937. |
Vasili et al., “Direct observation of multivalent states and 4 f-3d charge transfer in Ce-doped yttrium iron garnet thin films,” Physical Review, 2017, pp. 1-10. |
International Search Report and Written Opinion dated Jul. 12, 2021, in International Application No. PCT/US2021/023048, 9 pages. |
Taylor, S. et al., “A review of the plasma oxidation of silicon and its applications,” Semicond. Sci. Technol., 1993, vol. 8, pp. 1426-1433. |
Amirfeiz et al., “Formation of silicon structures by plasma-activated wafer bonding,” Journal of The Electrochemical Society, 2000, vol. 147, No. 7, pp. 2693-2698. |
Bengtsson, S. et al., “Low Temperature Bonding,” International Conference on Compliant & Alternative Substrate Technology, Meeting Program & Abstract Book, Sep. 29-23, p. 10. |
Farrens et al., “Chemical Free Room Temperature Wafer to Wafer Direct Bonding”, J. Electrochem. Soc., vol. 142, No. 11, Nov. 1995, pp. 3949-3955. |
Gan, Qing, “Surface activation enhanced low temperature silicon wafer bonding,” Dissertation submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy, Department of Mechanical Engineering and Materials Science, Duke University, Aug. 4, 2000, 192 pages. |
Gösele, U. et al., “Semiconductor Wafer Bonding, a Flexible Approach to Materials Combinations in Microelectronics, Micromechanics and Optoelectronics”, 1997 IEEE, pp. 23-32. |
International Search Report and Written Opinion dated Feb. 7, 2014 in PCT/US2013/057536 filed Aug. 30, 2013. |
International Search Report and Written Opinion dated Mar. 7, 2019, in International Application No. PCT/US2018/060044, 14 pages. |
International Search Report and Written Opinion dated Apr. 22, 2019 in International Application No. PCT/US2018/064982, 13 pages. |
Ker, Ming-Dou et al., “Fully process-compatible layout design on bond pad to improve wire bond reliability in CMOS Ics,” IEEE Transactions on Components and Packaging Technologies, Jun. 2002, vol. 25, No. 2, pp. 309-316. |
Moriceau, H. et al., “Overview of recent direct wafer bonding advances and applications,” Advances in Natural Sciences-Nanoscience and Nanotechnology, 2010, 11 pages. |
Nakanishi, H. et al., “Studies on SiO2-SiO2 bonding with hydrofluoric acid. Room temperature and low stress bonding technique for MEMS,” Sensors and Actuators, 2000, vol. 79, pp. 237-244. |
Oberhammer, J. et al., “Sealing of adhesive bonded devices on wafer level,” Sensors and Actuators A, 2004, vol. 110, No. 1-3, pp. 407-412, see pp. 407-412, and Figures 1 (a)-1 (I), 6 pages. |
Plobi, A. et al., “Wafer direct bonding: tailoring adhesion between brittle materials,” Materials Science and Engineering Review Journal, 1999, R25, 88 pages. |
Reiche et al., “The effect of a plasma pretreatment on the Si/Si bonding behaviouir,” Electrochemical Society Proceedings, 1998, vol. 97-36, pp. 437-444. |
Darling, R.B., “Wafer Bonding,” EE-527: Microfabrication, Winter 2013, 32 pages. |
Mizumoto et al., Direct wafer bonding and its application to waveguide optical isolators, Department of Electrical and Electronic Engineering, Tokyo Institute of Technology, Materials, ISSN: 1996-1944, www.mdpi.com/journal/materials, Mar. 31, 2012, pp. 985-1004. |
Suga et al., “Combined process for wafer direct bonding by means of the surface activation method,” IEEE, 2004, pp. 484-490. |
Takagi et al., “Room-temperature wafer bonding of Si to LiNbO3, LiTaO3 and Gd3Ga5012 by Ar-beam surface activation,” Journal of Micromechanics and Microengineering, 2001, vol. 11, No. 4, pp. 348. |
Takei et al., “Effects of wafer precleaning and plasma irradiation to wafer surfaces on plasma-assisted surface-activated direct bonding,” Japanese Journal of Applied Physics, 2010, vol. 49, pp. 1-3. |
“Wafer Bonding—An Overview,” ScienceDirect Topics, Journals & Books, https://www.sciencedirect.com/topics/engineering/wafer-bonding, printed Jun. 27, 2019, 12 pages. |
Bush, Steve, “Electronica: Automotive power modules from On Semi,” ElectronicsWeekly.com, indicating an Onsemi AR0820 product was to be demonstrated at a Nov. 2018 trade show, https://www.electronicsweekly.com/news/products/power-supplies/electronica-automotive-power-modules-semi-2018-11/ (published Nov. 8, 2018; downloaded Jul. 26, 2023). |
Morrison, Jim et al., “Samsung Galaxy S7 Edge Teardown,” Tech Insights (posted Apr. 24, 2016), includes description of hybrid bonded Sony IMX260 dual-pixel sensor, https://www.techinsights.com/blog/samsung-galaxy-s7-edge-teardown, downloaded Jul. 11, 2023, 9 pages. |
Onsemi AR0820 image, cross section of a CMOS image sensor product. The part in the image was shipped on Sep. 16, 2021. Applicant makes no representation that the part in the image is identical to the part identified in the separately submitted reference Bush, Nov. 8, 2018, ElectronicsWeekly.com (“Bush article”); however, the imaged part and the part shown in the Bush article share the part number “Onsemi AR0820.”. |
Sony IMX260 image, a first cross section of Sony product labeled IMX260, showing a hybrid bonded back side illuminated CMOS image sensor with a pad opening for a wire bond. The second image shows a second cross-section with peripheral probe and wire bond pads in the bonded structure. The part in the images was shipped in Apr. 2016. Applicant makes no representation that the part in the images is identical to the part identified in the separately submitted reference Morrison et al. (Tech Insights article dated Apr. 24, 2016), describing and showing a similar sensor product within the Samsung Galaxy S7; however the imaged part and the part shown in the Morrison et al. article share the part name “Sony IMX260 image.”. |
Number | Date | Country | |
---|---|---|---|
20210296282 A1 | Sep 2021 | US |
Number | Date | Country | |
---|---|---|---|
62991775 | Mar 2020 | US |