Patent Application
20250210613
Implementations of the present disclosure relate to apparatus, systems, and methods of digitalized interconnect redistribution enabled chiplet packaging, for example to provide a better area and line input/output density than a 2.5D interposer method, 2D fan-out packaging method, and 2.3D silicon bridge method
Electronic devices, such as are included in tablets, computers, copiers, digital cameras, smart phones, control systems, and automated teller machines, among others, often include integrated circuit die(s) for some desired functionality. A heterogeneous integration module (HIM) (which may also be referred to or be a type of multi-chip module (MCM)) is a type of microelectronics device that integrates multiple different chips, materials, components, and/or technologies into a single compact package. This approach allows designers to create more complex and powerful systems by integrating different components, without the need for full system-on-chip integration. For example, this type of device aims to provide a high level of functionality and performance while also reducing the overall size, cost, and complexity of the system. HIMs devices are commonly used in a wide range of applications, including smartphones, wearable devices, and internet of things (IoT) devices, as well as in various fields such as telecommunications, computing, and robotics. They are designed to overcome the limitations of traditional microelectronics devices, which often rely on a single technology or material, by bringing together complementary components and technologies in a single, integrated package. Some examples of HIMS devices include multi-layer microelectronics packages, system-in-package (SiP) devices, and 2D and 3D integrated circuits (3D ICs). These devices can offer improved performance, higher functional density, and better thermal management compared to traditional microelectronics devices. However, combining different components into a single component package can lead to alignment and other integration issues, requiring relatively larger interconnect pitch, resulting in higher interconnect resistivity, or both.
According to one or more embodiments, a method of forming a packaged multichip module, includes molding a set of chips in a medium, mapping a position and orientation of the chips within the set of chips that are molded in the medium, forming an interconnect substrate. The forming the interconnect substrate including patterning a first interconnect layer to form a first plurality of patterned vias that each have an opening that is configured to connect with an interconnect formed on the chips within the set of chips based at least in part on the position and orientation information detected during the mapping and bonding the interconnect substrate to the multichip module, wherein bonding includes positioning and aligning the interconnect substrate to the molded set of chips such that the interconnects of each chip within the set of chips are aligned with the first plurality of patterned vias formed in the interconnect substrate and attaching a stacked chip to the multichip module via the interconnect substrate, wherein interconnects of the stacked chip are electrically coupled to conductive layers formed in the first plurality of patterned vias of the first interconnect layer.
According to one or more embodiments, a method for forming a packaged multichip module includes disposing an interconnect substrate on a multichip module of the packaged multichip module. The disposing of the interconnect substrate including forming a first interconnect layer, patterning a first plurality of patterned vias through the first interconnect layer and the interconnect substrate so that each have an opening that is configured to connect with an interconnect formed on each chip of a set of chips of the multichip module based at least in part on position and orientation information detected during a mapping of alignment marks formed on each chip in the set of chips, forming a first plurality of metal interconnects in the first plurality of patterned vias, and bonding the interconnect substrate to the multichip module, wherein bonding comprises positioning and aligning the interconnect substrate to a molded set of chips such that the interconnects of each chip within the set of chips are aligned with the first plurality of patterned vias formed in the interconnect substrate.
According to one or more embodiments a packaged multichip module includes a set of chips molded in a medium, each chip having at least one alignment mark and a plurality of interconnects, an interconnect substrate bonded to the set of chips. The interconnect substrate including a first interconnect layer disposed over a base substrate comprising a first plurality of patterned vias that are patterned based at least in part on position and orientation information detected during a mapping of the alignment marks and the plurality of interconnects, a second interconnect layer disposed over the first interconnect layer comprising a first contacting surface formed on one side of the second interconnect layer comprising a first plurality of metal interconnects that match a pattern of the first plurality of patterned vias and a second contacting surface formed on a second side of the second interconnect layer comprising a second plurality of metal interconnects that are configured to connect with an interconnect formed on a stacked chip, and a stacked chip attached to one or more of the chips of the multichip module via the interconnect substrate.
So that the manner in which the above recited features of the present disclosure can be understood in detail, a more particular description of the disclosure, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only exemplary embodiments and are therefore not to be considered limiting of its scope, and may admit to other equally effective embodiments.
To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.
A multichip module (MCM) (or heterogeneous integration module (HIM)) may incorporate a number of semiconductor devices formed on or in a substrate (e.g., chips or chiplets). Examples of interconnection types used for HIMs include 2D fan-out type, 2.3D silicon bridge type, and 2.5D performance gap type.
A 2D fan-out packaging is a type of chip packaging technology that allows multiple chips or dies to be integrated onto a single package using a 2D layout. In this approach, the dies are mounted on a substrate, which is then molded with an insulating material to create a flat surface. The substrate is then etched to create a pattern of electrical interconnects, which connect the dies to each other and to the package's external pins. This packaging technique may allow for increased integration density and reduced form factor, as well as improved thermal performance due to the use of a thin and uniform package. Additionally, 2D fan-out packaging can offer better electrical performance compared to traditional packaging methods such as wire bonding, as the shorter interconnects and reduced parasitics can result in faster signal propagation and lower power consumption.
2.3D Si Bridge packaging is a type of semiconductor packaging technology that enables the integration of multiple dies or chips on a single package using a 2.5D or 3D layout. This approach involves using a silicon interposer or “bridge” that provides high-density electrical connections between the dies and other components, such as memory or sensors. In a 2.3D Si Bridge package, the interposer is thinned down to reduce the distance between the dies and minimize electrical parasitics, resulting in improved performance and power efficiency. This approach can also enable the use of heterogeneous integration, where different types of dies or technologies can be integrated on the same package. 2.3D Si Bridge packaging can offer a range of benefits, including increased performance, higher integration density, reduced power consumption, and improved thermal management, making it an attractive solution for high-performance computing, Al, and other advanced applications.
A multichip module that uses a 2.5D interposer is a type of electronic package that combines multiple chips or dies, that each may be fabricated using different processes and technologies, into a single module. In a 2.5D module, the individual dies are mounted on a silicon or organic interposer, which serves as a bridge between the dies and provides electrical and thermal connections.
In some cases, 2D fan out (X-Y) line space limits are at (2/2 um-5/5 um), which is typically not far from the line patterning capability of a system, but may present concerns of long-term reliability (e.g., on an organic dielectric) due to wafer/substrate global coefficient of thermal expansion (CTE) mismatch by and between one or more wafers and the substrate, CTE being the measure of the ability of a material to expand or contract with temperature changes. This problem may be especially acute for cross multi-die space areas.
In some cases, 2.3D (silicon (Si) Bridge) and 2.5D interposer type approaches use solder bumps (e.g., copper pillar (Cu-Pillar) solder bumps). Such solder bumps are typically associated with a higher electrical resistance than a direct Cu junction. The input/output area density is limited by solder bump pitch.
Implementations of the present disclosure relate to apparatus, systems, and methods of digitalized interconnect redistribution enabled chiplet packaging, for example to provide a better area and line input/output density than a 2.5D interposer method, 2D fan-out packaging method, and 2.3D silicon bridge method. It is also believed that the disclosed packaging structure and methods provided herein will also provide a lower electrical resistance than 2.5D & 2.3D packaging and better packaging process-induced stress management from a localized direct CTE-compatible RDL stack scheme from traditional 2-D packaging.
One or more embodiments disclosed herein includes a method of forming a multichip module, including printing or forming a set of alignment marks on a set of chips to be integrated into a multi-chip module, each chip having at least one alignment mark, molding the set of chips in a medium to secure each chip relative to each other chip, mapping each alignment mark of for a corresponding chip of the set of chips that are molded in the medium. The method further includes forming and bonding an interconnect substrate including a first interconnect layer having a plurality of vias that are based at least in part on the mapping, and at least one additional interconnect layer including first interconnects tailored to the patterning of the vias of the first interconnect layer on a first surface and second interconnects on a second surface tailored to mate with interconnecting features (e.g., pads, vias, traces, pins, etc.) formed in chips that are to be attached to the multichip module. For ease of discussion the term interconnect, die interconnect, or chip interconnect are often used herein to generally describe an interconnecting feature formed on a chip.
In an embodiment, the electrical or DSP chip 102 may include any high-density chip having a high I/O pin count. In one example, the high-density chip has between 100 and 2000 I/O pins or up to and greater than 2000 I/O pin counts. Examples of electrical or DSP chips 102 include but not limited to data center SWITCH chips, artificial intelligence (AI) chips, and the like.
The PIC unit 106 includes a fiber connector region 110 configured to be coupled to a fiber connector for removably connecting a fiber cable to the PIC unit 106. In an embodiment, the fiber cable may be plugged into the fiber connector to operably connect the fiber cable to the chips of the multichip module 100. In an embodiment, the PIC unit 106 is configured for connecting fiber cables of the fiber connector region 110 including, but not limited to, single-mode fiber optic cables having 9 micron fiber core diameters. The fiber connector of the fiber connector region 110 may further include a plurality of optical fibers to operably connect fiber cables having between 1 to 74 fiber cores, 74 to 148 fiber cores, and up to and greater than 148 fiber cores to the PIC unit 106.
In an embodiment, the PIC unit 106 in the multichip module 100 is configured to transmit signals between the electrical or DSP chip 102 and the fiber cable of the fiber connector region 110 connected to the PIC unit 106. In one example, the PIC unit 106 includes a chip 302, such as an optical transceiver integrated circuit (SiPho chip). In one example, the chip 302 is mounted directly onto the multichip module (
In some embodiments, the multichip module 200 includes an interconnect structure and associated semiconductor devices (e.g., chiplets, including Active, Passive, or Electrical path chiplets) during formation of the multichip module. In some examples, the formed multichip module 200 may be or be referred to as digitalized interconnect redistribution enabled chiplet packaging.
At operation 402, a set of alignment marks 216 are formed on each chip of a set of chips to be integrated into multichip module 200 (
At operation 404 each chip of the set of chips are positioned and then molded into a medium to secure each chip relative to each other chip. In one example, operation 404 includes the operations shown in
The set of dies, including both the first type and second type, are adhered to the temporary carrier 202 (and tape 201) “face down” such that the pads or interconnects 203 of the dies contact face toward the temporary carrier 202. In some embodiments, the set of dies are arranged in separate die units across the surface of the temporary carrier 202, such as generally illustrated in
At operation 406, each of the alignment marks 216 of the molded set of dies are mapped by use of an optical inspection system that includes a camera and a system controller that includes a processor (CPU), nonvolatile memory and I/O components. For example, position and orientation information of the molded set of dies is determined based on the mapping of the alignment marks 216. The molded set of dies (i.e. chips) having the alignment marks 216 are scanned, analyzed and stored in memory of a system controller. Each chip (die) shift and orientation is scanned and recorded, for example in a graphic data system (GDS) file. In one or more embodiments, all digital map input and fiducial correction information is computed and consolidated at device level test as a file (e.g., GDS file) for separated interposer patterning use. As such, in some embodiments, the alignments marks 216 are die level alignment marks for use with a digital lithography technology (DLT) patterning process.
Some more of the advantages of this approach include that there is no reticle size limit on the interconnection pattern. Also, the digitalized interconnect redistribution substrate unit manufacturing process can be also decoupled from a single substrate manufacturing batch sequence and thus substrate units can be produced with other types of multiple-chiplet unit substrates as needed, which will provide additional manufacturing flexibility. In some embodiments, the recorded GDS file can also be reused in cases where the process needs to be repeated, or the data can be further pattern optimized through the substrate via interconnect and chiplet top metal patterning mapping. Moreover, it is easy to scale up the described operations to cover full multiple chiplet connection module, or both.
At operation 408, an interconnect substrate 218 (which may also be referred to as a direct interconnect land substrate (DILS)) is formed based on the scanned set of dies (i.e., the mapping). The interconnect substrate 218 is bonded to the multichip module 200 (i.e., the molded set of chips). The operations for forming the interconnect substrate 218 are illustrated in
In one or more examples, the base substrate 222 and the first interconnect layer 220 are etched in a pattern that is defined by the mapping process, as discussed in relation to operation 406.
In one or more embodiments, the interconnect substrate 218 is etched according to a pattern to form the first plurality of patterned vias 224 that are positioned and aligned based on their relative position and orientation variation within each of the die units, as determined by the data (position and orientation information) collected from the scanning process (i.e., the mapping during operation 406) discussed above in relation to
In some embodiments, the first interconnect layer 220 and the direct interconnection portions (direct connection layers), such as the base substrate 222, are etched prior to attachment to the molded set of dies. In other embodiments, one or more interconnect layers can be formed on the first interconnect layer 220 of the interconnect substrate 218 that is attached to the molded set of dies at a later step in the processing sequence (e.g., see
In one or more embodiments, a base substrate thinning process is performed. In some embodiments, the base substrate thinning process is performed before the first plurality of patterned vias 224 are etched. In other embodiments, the base substrate thinning process is performed after the first plurality of patterned vias 224 are etched. In one or more embodiments, the base substrate thickness can be modulated.
In one or more examples, the interconnect substrate 218 is then diced into individual interconnect units, as shown by the formation of a separating feature 247.
The interconnect substrate 218 may be aligned so that each individual interconnect unit is attached to the corresponding die unit. Stated differently the interconnect substrate 218 is aligned so that the interconnects 203 on each die (i.e. chip) in the molded set of dies (i.e., the set of chips) are aligned the first plurality of patterned vias 225.
The interconnect substrate 218 is then attached (bonded) to the molded set of dies (i.e., the multichip module 200) based on the alignment of the interconnect substrate units.
Next, the first plurality of patterned vias 224 are filled to form a first plurality of metal interconnects 225a.
In some embodiments, the connection between the interconnect substrate 218 (interposer) vias and the contacts of the chiplets (e.g., the pads of the chiplet, die or chip), which are not a solder interface, have a superior Cu line to Cu via interface connection (e.g., lowered resistivity) than prior conventional solder techniques. In some embodiments, the via density (input/output (I/O) area density is equal to or denser than prior techniques (e.g., a traditional 2.5D through substrate via (TSV) interposer approach). In some embodiments, the RDL line density is at least equal to Si interposer or Si bridge level, for example due to a similar rigid interconnect substrate (e.g., DILS substrate) flatness. However, in some embodiments, because the first plurality of metal interconnects 225a are positioned based on misalignments between each die of the sets of dies (i.e., the alignment marks) additional stacked chips used in packaging, such as a printed circuit boards (PCB), SiPho chips, and EIC chips (if not included in the molded set of dies) cannot be readily attached to the multichip module 200. Stated differently, the first plurality of metal interconnects 225a are not compatible (are out of alignment) with traces and/or other internal circuitry of stacked chips because the first plurality of metal interconnects 225a are positioned based on misalignment of the molded set of chips of the multichip module 200.
Therefore, at operation 409, additional interconnect layers having interconnects that are tailored to both the first plurality of metal interconnects 225a and the to be attached stacked chips may be formed over the first interconnect layer 220. In another example, the additional interconnect layers may be formed before the interconnect substrate 218 is attached to the molded set of dies.
In one or more embodiments, the second interconnect layer 230 is an RDL structure. In other embodiments the second interconnect layer 230 is a C4/Cu pillar layer. The second interconnect layer 230 can be added after via formation of the interconnect substrate 218, for example for next level substrate integration. In one or more embodiments, prior to attaching the second interconnect layer 230, an inter-die fill can be applied to (formed on) the interconnect substrate 218. In some embodiments, the inter-die fill is spun on. In one example, the second interconnect layer 230 is deposited across the entire first interconnect layer 220 and is then singulated into separate portions configured to fit over each interconnect substrate unit. For example, the second interconnect layer 230 is singulated into a first portion 230a over the first interconnect substrate unit 240 and a second portion 230b over the second interconnect substrate unit 241. In another example, the first portion 230a and the second portion 230b are formed and attached separately.
In one or more embodiments, the second interconnect layer includes a first contacting surface 248 and a second contacting surface 249. The first contacting surface 248 comprises a second plurality of metal interconnects 225b. The first contacting surface 248 is formed on a first surface, such as a bottom surface, of the second interconnect layer 230. The second contacting surface 249 comprises a third plurality of metal interconnects 225c. The second contacting surface 249 is formed on a second surface, such as a top surface, of the second interconnect layer 230. The second and third plurality of metal interconnects 225b, 225c are formed on the second interconnect layer 230 so that stacked chips are able to be attached to at least one side of the multichip module 200. The second plurality of metal interconnects 225b are tailored (patterned) to the pattern of the first plurality of metal interconnects 225a and traces 226. The third plurality of metal interconnects 225c are tailored to match interconnects and traces of stacked devices (chips) such that the stacked devices (chips) can be easily and successfully attached to the multichip module 200 without the need to take into account the variation in the position of the die with the die unit. A fourth plurality of metal interconnects may be formed within the second interconnect layer 230. The fourth plurality of metal interconnects are each configured to form connections between the second plurality of metal interconnects 225b and the third plurality of metal interconnects 225c. The fourth plurality of metal interconnects 225d can be formed between the second plurality of metal interconnects 225b and the third plurality of metal interconnects 225c to allow communication between each set of dies (e.g., A-1, B-1, C-1, etc.) and the stacked chips attached to the multichip module 200. For example, one of the fourth plurality of interconnects is configured to couple interconnect 227b of the second plurality of metal interconnects 225b to interconnect 229c of the third plurality of metal interconnects 225c.
In one example, the second, third, and fourth pluralities of metal interconnects may also be formed using a DLT tool according to a file including die shift and orientation information (e.g., a second GDS file, or a second set of data in the GDS file associated with the previously formed interconnect layer and the to be attached stacked chip(s) (e.g. the first interconnect layer 220) or additional layers that are to be formed over the second interconnect layer 230. In one or more examples, as described above, more than one additional interconnected layers may be formed over the first interconnect layer 220. Each additional interconnect layer may include metal interconnects on each side of each additional interconnect layer that are tailored to continuously compensate for misalignments of the first plurality of metal interconnects 225a (due to misalignments between the molded set of chips). In the same manner described above, the top surface of the last (i.e., top) layer of the additional interconnect layers can have a pattern of metal interconnects tailored to be attached to a stacked chip that allow the molded set of chips to be in communication with the attached stacked chips.
Advantageously, each of the pluralities of metal interconnects of the interconnect substrate 218 can be used to form a connection to the chiplets (e.g., each chip of the molded set of chips) without a solder interface, which can provide a superior copper line to copper via interface (e.g., more reliable, lower resistivity). In some embodiments, after the second interconnect layer 230 is attached, metalized traces 231 can be processed (e.g., by a DLT tool) according to a file including die shift and orientation information (e.g., a second GDS file, or a second set of data in the GDS file associated with the previously formed interconnect layer (e.g. the first interconnect layer 220) or additional layers that are to be formed over the second interconnect layer 230. In some embodiments, the density can be equal to a silicon Si interposer or silicon bridge level approach due to a similar rigid DILS substrate flatness. According to one or more embodiments, the interconnect substrate 218 and layers can be extended to further layers using further DILI (e.g., including a direct interconnect substrate and RDL), each of which can include active or passive components, RDL, and so on. Each further layer may include a plurality of metal interconnects such as metal interconnects 225b-225d to allow chips to be attached to the multichip module 200 and communicate with the misaligned dies of the multichip module 200.
At operation 410 stacked chip(s) are attached to the multichip module 200, forming a packaged multichip module.
Referring to
In some embodiments, as shown in
Additionally, the PCB 304 may be attached to the multichip module 200 via the third plurality of metal interconnects 225c. In one example, the PCB 304 may be coupled to an SOC chip (die C-1) via the third plurality of metal interconnects 225c. In one example, the PCB may include an optional core substrate 306 (e.g., silicon or glass core substrate). The PCB 304 may include metal traces 316. Advantageously, while the first plurality of metal interconnects 225a are tailored to the alignment marks 216 (i.e., the misalignments between the set of dies) the third plurality of metal interconnects 225c are tailored to the metal traces 316 and/or internal circuitry of the PCB 304 allowing for a standardly configured PCB or PCB with a known configuration to be coupled to the multichip module 200 even if the set of dies are misaligned. In examples in which the PCB 304 includes a core substrate 306, the core substrate 306 may include metal interconnects 320 to allow connections between metal traces 316 of the PCB 304 on opposite sides of the core substrate 306.
Referring to
In some embodiments, as shown in
Referring to
Referring to
