Patent Application
20240204083
IC (integrated circuit) fabrication usually includes two stages. The first stage is referred to as the front end of line (FEOL). The second stage is referred to as the back end of line (BEOL). In the FEOL, individual components (e.g., transistor, capacitors, resistors, etc.) can be patterned in a wafer. In the BEOL, metal layers, vias, and insulating layers can be formed to get the individual components interconnected. The BEOL usually starts with forming the first metal layer on the wafer. The first metal layer is often called M0. More metal layers can be formed on top of M0, and these metal layers are often called M1, M2, and so on.
Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings.
The systems, methods, and devices of this disclosure each have several innovative aspects, no single one of which is solely responsible for all the desirable attributes disclosed herein. Details of one or more implementations of the subject matter described in this specification are set forth in the description below and the accompanying drawings.
Continued scaling of transistors and design cell height leads to narrow BEOL metal lines. This creates a challenge for metal patterning, via landing, or edge placement error control and the need to ensure low resistance of metal lines and vias. Taking vias connected to FEOL transistors and M0 for example, shorting margin of VCG and VCT is usually achieved through metal recess of GCN and TCN in M0. VCG is via connecting gate, such as a via connected or coupled to the gate electrode of a transistor. VCT is via connecting transistor, such as a via connected or coupled to the source contact or drain contact of a transistor. VCG may be connected to GCN, which is gate contact (e.g., gate electrode) or a metal line in a metal layer (e.g., M0, M1, etc.) that is coupled to the gate of the transistor. VCT may be connected to TCN, which is trench contact (e.g., source or drain contact of the transistor) or a metal line in metal layer (e.g., M0, M1, etc.) that is coupled to the source or drain contact of the transistor. As the gate electrode is usually at a different electrical potential from the source contact or drain contact, VCG needs to be insulated from TCN. Also, VCT needs to be insulated from GCN. The purpose of metal recess to provide a sufficient distance (i.e., a sufficient shorting margin) between VCG and TCN or between VCT and GCN.
However, a challenge of metal recess is that metal recess is not controllable. For instance, the amount of metal removed during a metal recess process can be difficult to control. This can lead to variations in metal line dimensions or surface smoothness, which can degrade performance of the IC device. Also, through metal recess, the electrical insulator between VCG and TCN or between VCT and GCN is usually the same material as the electrical insulator between the metal lines, e.g., ILD (interlayer dielectric). There is hardly any other material choice. Given the fallbacks of metal recess, improvement technologies for providing shorting margin of vias are needed.
Embodiments of the present disclosure may improve on at least some of the challenges and issues described above by providing DSA-based spacers and liners to improve shorting margins of vias. In various embodiments of the present disclosure, a DSA layer is formed over an underlayer including conductive structures and insulative structures. The conductive structures may be used as contacts of a semiconductor device in a FEOL section, such as the gate contact, source contact, and drain contact of a transistor. Alternatively, the conductive structures may be used as metal lines in a BEOL section, such as metal lines in M0, M1, M2, etc. The DSA layer may be formed through self-assembly of a diblock copolymer. The diblock copolymer may include two types of monomers: A and B. The diblock copolymer may have a phase (e.g., a lamellar phase) that has a periodic distribution of A and B. The self-assembly of a diblock copolymer produces an alternating pattern of polymer A and polymer B. One of the polymers can be removed from the DSA layer to create openings in the DSA layer. One or more electrical insulators can be provided into the openings to form the spacers. The spacers may include one or more different materials from the insulative structures in the BEOL layer.
Liners can be formed around the spacers. For example, an electrical insulator may be provided to form a liner wrapping around a spacer at least partially. The liner may surround one or more side surfaces of the spacer. In some embodiments, a side surface of the space may extend in a direction that is perpendicular or substantially perpendicular to the underlayer or a substrate. Each pair of liner and spacer can form an insulative spacing structure for providing a shorting margin of vias connected to the conductive structures. As the spacers are formed based on the self-alignment of the diblock copolymer, the spacers may be aligned with the insulative structures in the underlayer. Each spacer may be over an insulative structure in the layer. The liner around the spacer may be over one or more conductive structures in the underlayer. A via can be placed at least partially between two adjacent insulative spacing structures and connected to a conductive structure in the underlayer. The via can be separated from one or more other conductive structures in the underlayer (e.g., conductive structures that are adjacent to the conductive structure connected to the via) through the insulative spacing structures. Despite that the conductive structures in the underlayer may have the same height, the insulative spacing structures can sufficient shorting margin to avoid shorting between the via and the other conductive structures that are not connected to the via.
With the DSA-based spacers and liners in the present disclosure, metal recess can be avoided so that the fallbacks of metal recess can be avoided. The DSA process for forming the spacers and liners is more controller than metal recess. It also allows independent material choice so that the spacers and liners can have different materials from the electrical insulator between the metal lines or can have different materials from each other. Additionally, compared with metal recess, the DSA-based spacers and liners does not reduce the heights of contacts or metal lines and therefore, can facilitate fabrication of taller devices with lower resistance, such as taller memory devices (e.g., static random-access memory (SRAM)). Therefore, the present disclosure provides a more advantageous technology for providing shorting margins of vias than the currently available technologies.
It should be noted that, in some settings, the term “nanoribbon” has been used to describe an elongated semiconductor structure that has a substantially rectangular transverse cross-section (e.g., a cross-section in a plane perpendicular to the longitudinal axis of the structure), while the term “nanowire” has been used to describe a similar structure but with a substantially circular or square transverse cross-sections. In the following, a single term “nanoribbon” is used to describe an elongated semiconductor structure independent of the shape of the transverse cross-section. Thus, as used herein, the term “nanoribbon” is used to cover elongated semiconductor structures that have substantially rectangular transverse cross-sections (possibly with rounded corners), elongated semiconductor structures that have substantially square transverse cross-sections (possibly with rounded corners), elongated semiconductor structures that have substantially circular or elliptical/oval transverse cross-sections, as well as elongated semiconductor structures that have any polygonal transverse cross-sections. A longitudinal axis of a structure refers to a line (e.g., an imaginary line) that runs down the center of the structure in a direction perpendicular to a transverse cross-section of the structure.
In the following, some descriptions may refer to a particular source or drain (S/D) region or contact being either a source region/contact or a drain region/contact. However, unless specified otherwise, which region/contact of a transistor or diode is considered to be a source region/contact and which region/contact is considered to be a drain region/contact is not important because, as is common in the field of FETs, designations of source and drain are often interchangeable. Therefore, descriptions of some illustrative embodiments of the source and drain regions/contacts provided herein are applicable to embodiments where the designation of source and drain regions/contacts may be reversed.
As used herein, the term “metal layer” may refer to a layer above a substrate that includes electrically conductive interconnect structures for providing electrical connectivity between different IC components. Metal layers described herein may also be referred to as “interconnect layers” to clearly indicate that these layers include electrically conductive interconnect structures which may, but do not have to be, metal.
The systems, methods and devices of this disclosure each have several innovative aspects, no single one of which is solely responsible for all of the desirable attributes disclosed herein. Details of one or more implementations of the subject matter described in this specification are set forth in the description below and the accompanying drawings.
In the following detailed description, various aspects of the illustrative implementations may be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. For example, the term “connected” means a direct electrical or magnetic connection between the things that are connected, without any intermediary devices, while the term “coupled” means either a direct electrical or magnetic connection between the things that are connected, or an indirect connection through one or more passive or active intermediary devices. The term “circuit” means one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function. If used, the terms “oxide,” “carbide,” “nitride,” etc. refer to compounds containing, respectively, oxygen, carbon, nitrogen, etc., the term “high-k dielectric” refers to a material having a higher dielectric constant (k) than silicon oxide, while the term “low-k dielectric” refers to a material having a lower k than silicon oxide. The terms “substantially,” “close,” “approximately,” “near,” and “about,” generally refer to being within +/−10%, e.g., within +/−5% or within +/−2%, of a target value based on the context of a particular value as described herein or as known in the art. Similarly, terms indicating orientation of various elements, e.g., “coplanar,” “perpendicular,” “orthogonal,” “parallel,” or any other angle between the elements, generally refer to being within +/−8% of a target value, e.g., within +/−5% of a target value or within +/−2% of a target value, based on the context of a particular value as described herein or as known in the art. Also, the term “or” refers to an inclusive “or” and not to an exclusive “or.”
The terms “over,” “under,” “between,” and “on” as used herein refer to a relative position of one material layer or component with respect to other layers or components. For example, one layer disposed over or under another layer may be directly in contact with the other layer or may have one or more intervening layers. Moreover, one layer disposed between two layers may be directly in contact with the two layers or may have one or more intervening layers. In contrast, a first layer “on” a second layer is in direct contact with that second layer. Similarly, unless explicitly stated otherwise, one feature disposed between two features may be in direct contact with the adjacent features or may have one or more intervening layers.
For the purposes of the present disclosure, the phrase “A and/or B” means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). The term “between,” when used with reference to measurement ranges, is inclusive of the ends of the measurement ranges. As used herein, the notation “A/B/C” means (A), (B), and/or (C).
The description may use the phrases “in an embodiment” or “in embodiments,” which may each refer to one or more of the same or different embodiments. Furthermore, the terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present disclosure, are synonymous. The disclosure may use perspective-based descriptions such as “above,” “below,” “top,” “bottom,” and “side”; such descriptions are used to facilitate the discussion and are not intended to restrict the application of disclosed embodiments. The accompanying drawings are not necessarily drawn to scale. Unless otherwise specified, the use of the ordinal adjectives “first,” “second,” and “third,” etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.
In the following detailed description, reference is made to the accompanying drawings that form a part hereof, and in which is shown, by way of illustration, embodiments that may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense. For convenience, if a collection of drawings designated with different letters are present, e.g.,
In the drawings, some schematic illustrations of example structures of various devices and assemblies described herein may be shown with precise right angles and straight lines, but it is to be understood that such schematic illustrations may not reflect real-life process limitations which may cause the features to not look so “ideal” when any of the structures described herein are examined using e.g., scanning electron microscopy (SEM) images or transmission electron microscope (TEM) images. In such images of real structures, possible processing defects could also be visible, e.g., not-perfectly straight edges of materials, tapered vias or other openings, inadvertent rounding of corners or variations in thicknesses of different material layers, occasional screw, edge, or combination dislocations within the crystalline region, and/or occasional dislocation defects of single atoms or clusters of atoms. There may be other defects not listed here but that are common within the field of device fabrication. Inspection of layout and mask data and reverse engineering of parts of a device to reconstruct the circuit using e.g., optical microscopy, TEM, or SEM, and/or inspection of a cross-section of a device to detect the shape and the location of various device elements described herein using, e.g., Physical Failure Analysis (PFA) would allow determination of presence of DSA-based spacers and liners as described herein.
Various operations may be described as multiple discrete actions or operations in turn in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations may not be performed in the order of presentation. Operations described may be performed in a different order from the described embodiment. Various additional operations may be performed, and/or described operations may be omitted in additional embodiments.
Various DSA-based spacers and liners as described herein may be implemented in, or associated with, one or more components associated with an IC or/and may be implemented between various such components. In various embodiments, components associated with an IC include, for example, transistors, diodes, power sources, resistors, capacitors, inductors, sensors, transceivers, receivers, antennas, etc. Components associated with an IC may include those that are mounted on IC or those connected to an IC. The IC may be either analog or digital and may be used in a number of applications, such as microprocessors, optoelectronics, logic blocks, audio amplifiers, etc., depending on the components associated with the IC. The IC may be employed as part of a chipset for executing one or more related functions in a computer.
In the embodiments of
The support structure 115 may be any suitable structure, such as a substrate, a die, a wafer, or a chip, based on which the transistors 117 can be built. The support structure 115 may, e.g., be the wafer 2000 of
Although a few examples of materials from which the support structure 115 may be formed are described here, any material that may serve as a foundation upon which an IC may be built falls within the spirit and scope of the present disclosure. In various embodiments, the support structure 115 may include any such substrate, possibly with some layers and/or devices already formed thereon, not specifically shown in the present figures. As used herein, the term “support” does not necessarily mean that it provides mechanical support for the IC devices/structures (e.g., transistors, capacitors, interconnects, and so on) built thereon. For example, some other structure (e.g., a carrier substrate or a package substrate) may provide such mechanical support and the support structure 115 may provide material “support” in that, e.g., the IC devices/structures described herein are build based on the semiconductor materials of the support structure 115. However, in some embodiments, the support structure 115 may provide mechanical support.
A transistor 117 may be a field-effect transistor (FET), such as metal-oxide-semiconductor FET (MOSFET), tunnel FET (TFET), fin-based transistor (e.g., FinFET), nanoribbon-based transistor, nanowire-based transistor, gate-all-around (GAA) transistor, other types of FET, or a combination of both. The transistor 117A includes a semiconductor structure that includes a channel region 140A, a source region 143A, and a drain region 147A. The transistor 117A includes a semiconductor structure that includes a channel region 140B, a source region 143B, and a drain region 147B. The channel regions 140A and 140B are collectively referred to as “channel regions 140” or “channel region 140.” The source regions 143A and 143B are collectively referred to as “source regions 143” or “source region 143.” The drain regions 147A and 147B are collectively referred to as “drain regions 147” or “drain region 147.”
The semiconductor structure of each transistor 117 may be at least partially in the support structure 115. The support structure 115 may include a semiconductor material, from which at least a portion of the semiconductor structure is formed. The semiconductor structure of a transistor 117 (or a portion of the semiconductor structure, e.g., the channel region 140) may be a planar structure or a non-planar structure. A non-planar structure is a three-dimensional structure, such as fin, nanowire, or nanoribbon. A non-planar structure may have a longitudinal axis and a transvers cross-section perpendicular to the longitudinal axis. In some embodiments, a dimension of the non-planar structure along the longitudinal axis may be greater than dimensions along other directions, e.g., directions along axes perpendicular to the longitudinal axis.
Each channel region 140 includes a channel material. The channel material may be composed of semiconductor material systems including, for example, n-type or p-type materials systems. In some embodiments, the channel material may include a high mobility oxide semiconductor material, such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide. In some embodiments, the channel material may include a compound semiconductor with a first sub-lattice of at least one element from Group Ill of the periodic table (e.g., Al, Ga, In), and a second sub-lattice of at least one element of group V of the periodic table (e.g., P, As, Sb). In some embodiments, the channel material may include a compound semiconductor with a first sub-lattice of at least one element from Group II of the periodic table (e.g., Zn, Cd, Hg), and a second sub-lattice of at least one element of Group IV of the periodic table (e.g., C, Si, Ge, Sn, Pb). In some embodiments, the channel material is an epitaxial semiconductor material deposited using an epitaxial deposition process. The epitaxial semiconductor material may have a polycrystalline structure with a grain size between about 2 nm and 100 nm, including all values and ranges therein.
For some example n-type transistor embodiments (i.e., for the embodiments where the transistor 117 is an NMOS (N-type metal-oxide-semiconductor) transistor or an n-type TFET), the channel material may advantageously include a III-V material having a high electron mobility, such as, but not limited to InGaAs, InP, InSb, and InAs. For some such embodiments, the channel material may be a ternary III-V alloy, such as InGaAs, GaAsSb, InAsP, or InPSb. For some InxGa1-xAs fin embodiments, In content (x) may be between 0.6 and 0.9, and may advantageously be at least 0.7 (e.g., In0.7Ga0.3As). In some embodiments with highest mobility, the channel material may be an intrinsic III-V material, i.e., a III-V semiconductor material not intentionally doped with any electrically active impurity. In alternate embodiments, a nominal impurity dopant level may be present within the channel material, for example to further fine-tune a threshold voltage Vt, or to provide HALO pocket implants, etc. Even for impurity-doped embodiments however, impurity dopant level within the channel material 304 may be relatively low, for example below 1015 dopant atoms per cubic centimeter (cm−3), and advantageously below 1013 cm−3. These materials may be amorphous or polycrystalline, e.g., having a crystal grain size between 0.5 nanometers and 100 nanometers.
For some example p-type transistor embodiments (i.e., for the embodiments where the transistor 117 is a PMOS (P-type metal-oxide-semiconductor) transistor or a p-type TFET), the channel material may advantageously be a Group IV material having a high hole mobility, such as, but not limited to Ge or a Ge-rich SiGe alloy. For some example embodiments, the channel material may have a Ge content between 0.6 and 0.9, and advantageously may be at least 0.7. In some embodiments with highest mobility, the channel material may be intrinsic III-V (or IV for P-type devices) material and not intentionally doped with any electrically active impurity. In alternate embodiments, one or more a nominal impurity dopant level may be present within the channel material, for example to further set a threshold voltage (Vt), or to provide HALO pocket implants, etc. Even for impurity-doped embodiments however, impurity dopant level within the channel portion is relatively low, for example below 1015 cm−3, and advantageously below 1013 cm−3. These materials may be amorphous or polycrystalline, e.g., having a crystal grain size between 0.5 nanometers and 100 nanometers.
In some embodiments, the channel material may include a high mobility oxide semiconductor material, such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, indium gallium zinc oxide (IGZO), gallium oxide, titanium oxynitride, ruthenium oxide, aluminum zinc oxide, or tungsten oxide. In general, for a thin-film transistor (TFT), the channel material may include one or more of tin oxide, cobalt oxide, copper oxide, antimony oxide, ruthenium oxide, tungsten oxide, zinc oxide, gallium oxide, titanium oxide, indium oxide, titanium oxynitride, indium tin oxide, indium zinc oxide, nickel oxide, niobium oxide, copper peroxide, IGZO, indium telluride, molybdenite, molybdenum diselenide, tungsten diselenide, tungsten disulfide, molybdenum disulfide, N- or P-type amorphous or polycrystalline silicon, monocrystalline silicon, germanium, indium arsenide, indium gallium arsenide, indium selenide, indium antimonide, zinc antimonide, antimony selenide, silicon germanium, gallium nitride, aluminum gallium nitride, indium phosphite, black phosphorus, zinc sulfide, indium sulfide, gallium sulfide, each of which may possibly be doped with one or more of gallium, indium, aluminum, fluorine, boron, phosphorus, arsenic, nitrogen, tantalum, tungsten, and magnesium, etc. In some embodiments, a thin-film channel material may be deposited at relatively low temperatures, which allows depositing the channel material within the thermal budgets imposed on back-end fabrication to avoid damaging other components, e.g., front end components such as logic devices.
As noted above, the channel material may include IGZO. IGZO-based devices have several desirable electrical and manufacturing properties. IGZO has high electron mobility compared to other semiconductors, e.g., in the range of 20-50 times than amorphous silicon. Furthermore, amorphous IGZO (a-IGZO) transistors are typically characterized by high band gaps, low-temperature process compatibility, and low fabrication cost relative to other semiconductors.
IGZO can be deposited as a uniform amorphous phase while retaining higher carrier mobility than oxide semiconductors such as zinc oxide. Different formulations of IGZO include different ratios of indium oxide, gallium oxide, and zinc oxide. One particular form of IGZO has the chemical formula InGaO3(ZnO)5. Another example form of IGZO has an indium:gallium:zinc ratio of 1:2:1. In various other examples, IGZO may have a gallium to indium ratio of 1:1, a gallium to indium ratio greater than 1 (e.g., 2:1, 3:1, 4:1, 5:1, 6:1, 7:1, 8:1, 9:1, or 10:1), and/or a gallium to indium ratio less than 1 (e.g., 1:2, 1:3, 1:4, 1:5, 1:6, 1:7, 1:8, 1:9, or 1:10). IGZO can also contain tertiary dopants such as aluminum or nitrogen.
In each transistor 117, the source region 143 and the drain region 147 are connected to the channel region 140. The source region 143 and the drain region 147 each includes a semiconductor material with dopants. In some embodiments, the source region 143 and the drain region 147 have the same semiconductor material, which may be the same as the channel material of the channel region 140. A semiconductor material of the source region 143 or the drain region 147 may be a Group IV material, a compound of Group IV materials, a Group III/V material, a compound of Group III/V materials, a Group II/VI material, a compound of Group II/VI materials, or other semiconductor materials. Example Group II materials include zinc (Zn), cadmium (Cd), and so on. Example Group III materials include aluminum (AI), boron (B), indium (In), gallium (Ga), and so on. Example Group IV materials include silicon (Si), germanium (Ge), carbon (C), etc. Example Group V materials include nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), and so on. Example Group VI materials include sulfur (S), selenium (Se), tellurium (Te), oxygen (O), and so on. A compound of Group IV materials can be a binary compound, such as SiC, SiGe, and so on. A compound of Group III/V materials can be a binary, tertiary, or quaternary compound, such as GaN, InN, and so on. A compound of Group II/VI materials can be a binary, tertiary, or quaternary compounds, such as CdSe, CdS, CdTe, ZnO, ZnSe, ZnS, ZnTe, CdZnTe, CZT, HgCdTe, HgZnTe, and so on.
In some embodiments, the dopants in the source region 143 and the drain region 147 are the same type. In other embodiments, the dopants of the source region 143 and the drain region 147 may be different (e.g., opposite) types. In an example, the source region 143 has n-type dopants and the drain region 147 has p-type dopants. In another example, the source region 143 has p-type dopants and the drain region 147 has n-type dopants. Example n-type dopants include Te, S, As, tin (Sn), Si, Ga, Se, S, In, Al, Cd, chlorine (Cl), iodine (I), fluorine (F), and so on. Example p-type dopants include beryllium (Be), Zn, magnesium (Mg), Sn, P, Te, lithium (Li), sodium (Na), Ga, Cd, and so on.
In some embodiments, the source region 143 and the drain region 147 may be highly doped, e.g., with dopant concentrations of about 1·1021 cm−3, in order to advantageously form Ohmic contacts with the respective S/D contacts (also sometimes interchangeably referred to as “S/D electrodes”), although these regions may also have lower dopant concentrations and may form Schottky contacts in some implementations. Irrespective of the exact doping levels, the source region 143 and the drain region 147 may be the regions having dopant concentration higher than in other regions, e.g., higher than a dopant concentration in the channel region 140, and, therefore, may be referred to as “highly doped” (HD) regions.
The channel region 140 may include one or more semiconductor materials with doping concentrations significantly smaller than those of the source region 143 and the drain region 147. For example, in some embodiments, the channel material of the channel region 140 may be an intrinsic (e.g., undoped) semiconductor material or alloy, not intentionally doped with any electrically active impurity. In alternate embodiments, nominal impurity dopant levels may be present within the channel material, for example to set a threshold voltage Vt, or to provide HALO pocket implants, etc. In such impurity-doped embodiments however, impurity dopant level within the channel material is still significantly lower than the dopant level in the source region 143 and the drain region 147, for example below 1015 cm−3 or below 1013 cm−3. Depending on the context, the term “S/D terminal” may refer to a S/D region or a S/D contact or electrode of a transistor.
Each transistor 117 also includes a source contact over the source region 143 and a drain contact over the drain region 147. In the embodiments of
Each transistor 117 also includes a gate that is over or wraps around at least a portion of the channel region 140. The gate of the transistor 117 may include a gate contact (also referred to as “gate electrode”). In the embodiments of
The gate may also include a gate insulator (not show in
The conductive structures 153 are separated by the insulative structures 155 in the layer 150. An insulative structure 155 may include one or more electrical insulators, such as dielectric material, hysteretic material, and so on. In some embodiments, the insulative structures 155 may include the same electrical insulator. In other embodiments, the insulative structures 155 may include different electrical insulators.
As shown in
The metal lines 185 are insulated from each other by the electrical insulator 125. The electrical insulator 125 includes one or more electrically insulative materials. An electrically insulative material may be a dielectric material, hysteretic material, and so on. Example dielectric material includes oxide (e.g., Si based oxides, metal oxides, etc.), nitride (e.g., Si based nitride, etc.), low-k dielectric, high-k dielectric, and so on. Example hysteretic material include ferroelectric materials, antiferroelectric materials, and so on. The electrical insulator 125 may be referred to as ILD of the BEOL section 120.
The vias 170 are connected to the transistor 117 and the metal lines 185. Each via 170 is electrically conductive. A via 170 may include a metal, such as tungsten (W), molybdenum (Mo), ruthenium (Ru), copper (Cu), or other metals. Different vias 170 may include different materials. The vias 170 can provide a conductive channel between the transistor 117s and the metal layer 180. In the embodiments of
Each via 170 has a portion that is between two adjacent insulative spacing structures 160. The insulative spacing structures 160 provides a shorting margin for the vias 170. Two insulative spacing structures 160 surrounding a via 170 can prevent electrical short between the via 170 and one or more conductive structures 153 that are not connected to the via 170. For instance, a via 170 connected to a gate contact of a transistor is separated from the source contact and drain contact of the transistor by the two insulative spacing structures 160 surrounding the via 170. That way, the gate contact is not shorted to the source contact or drain contact. Without the insulative spacing structures 160, the conductive structures 153 functioning as gate contacts may need to be recessed, so become shorter than adjacent conductive structures to provide the necessary shorting margin. The reduction in the height of the conductive structures 153 can result in higher resistance. Also, the recess can cause variations among the conductive structure 153, which can degrade the performance of the IC device 100.
Each insulative spacing structure 160 includes a spacer 163 and a liner 165. Each spacer 163 is over an insulative structure 155 along the Z axis. Each spacer 163 may be electrically insulative and includes one or more electrical insulators. In some embodiments, a length of a spacer 163 along the X axis is the same or similar as the length of the insulative structure 155 along the X axis. One or more edges of the spacer 163 may be aligned with one or more edges of the insulative structure 155 along the Z axis. An edge of the spacer 163 may be aligned with an edge of a conductive structure 153 along the Z axis. For instance, an edge of the space 163 and an edge of the insulative structure 155 or the conductive structure 153 may be in a straight line. The spacers 163 may be formed based on self-assembly of a diblock copolymer.
Each liner 165 surrounds a spacer 163 at least partially. A liner 165 may wrap around the corresponding spacer 163 in a plane perpendicular to the Z axis. I For instance, the liner 165 may wrap around one or more side surfaces of the spacer 163 that are perpendicular to the layer 150 or to the support structure 115. Each liner 165 is over a portion of each of two adjacent conductive structures 153, i.e., the two conductive structures 153 between which the insulative structure 155 over the spacer 163 is arranged. Each liner 165 may be electrically insulative and includes one or more electrical insulators. The liners 165 may be formed by depositing one or more electrical insulators onto the surface of the BEOL layer 170. With the liners 165, there can be more shorting margin for the vias 170. Also, material choice for the insulative spacing structures 160 can be independent from the insulative structures 155. In some embodiments, the insulative spacing structures 160 include one or more different materials from the insulative structures 155. Examples of a material in the insulative spacing structures 160 may include silicon oxide (SiO), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiOxNy, where x and y are integers), and so on. In some embodiments, the spacers 163 may have a different material from the liners 165. The independence in material choice for the insulative spacing structures 160 may enhance the insulation effect of the insulative spacing structures 160, which can be important for IC devices with tight pitches and limited shorting margins. More details regarding formations of the insulative spacing structures 160 are described below in conjunction with
A conductive structure 230 may functions as a contact of a semiconductor device. For instance, a conductive structure 230 be a conductive structure 153 in
In some embodiments, the layer 210 may be formed by forming a conductive layer (such as a layer of a metal), forming openings (e.g., trenches) in the conductive layer (e.g., by etching the metal), and providing (e.g., depositing) one or more electrical insulators into the openings to form the insulative structures 240. In some embodiments, the layer 210 may be formed by forming an insulative layer including one or more electrical insulators, forming openings (e.g., trenches) in the insulative layer, and providing (e.g., depositing) one or more metals into the openings to form the conductive structures 230.
A layer 220 is formed through DSA of the diblock copolymer over the layer 210. The layer 220 has an alternating pattern in which structures 223 (individually referred to as “structure 223”) alternatives with structures 227 (individually referred to as “structure 227”). The alternating pattern of the structures 223 and 237 is also referred to as a DSA pattern. The structures 223 and 237 may include two different polymers, such as polymer A and polymer B, the monomers of which are in a diblock copolymer.
In some embodiments, the diblock copolymer may be deposited onto the top surface of the layer 210. The diblock copolymer may include two types of monomers: A and B. The diblock copolymer may have a phase (e.g., a lamellar phase) that has a periodic distribution of A and B. In the embodiment of
In some embodiments, the DSA of the diblock copolymer may be facilitated by a guiding pattern that can guide microphase separation of the diblock copolymer. The diblock copolymer may self-assembly and form lamellar structures based on the guiding pattern. The guiding pattern may be a topographical guiding pattern, a chemical guiding pattern, or a combination of both. An example topographical guiding pattern may include walls and openings between the walls, and the self-assembly of the diblock copolymer is drive by the physical boundaries.
An example chemical guiding pattern may include sections that have stronger chemical affinity to polymer A than polymer B or sections that have stronger chemical affinity to polymer B than polymer A, and the self-assembly of the diblock copolymer is drive by the differentiated chemical affinities. In an embodiment, the metal in the conductive structures 230 may have stronger chemical affinity to polymer A, and the electrical insulator in the insulative structures 240 may have stronger chemical affinity to polymer A. As a result, the structures 223 are formed on top of the conductive structures 230, and the structures 227 are formed on top of the insulative structures 240.
As shown in
In some embodiments, the spacers 410 may be formed by depositing one or more electrical insulators into the openings 310. Each spacer 410 may fill an opening 310. The spacers 410 may be referred to as interlayer dielectric. As shown in
The vias 710 may be at different electrical potentials from each other. In some embodiments, the vias 710 may be coupled to different components of an IC device. For example, one of the vias 710 may be connected to a semiconductor device (e.g., transistor, capacitor, diode, etc.) versus the other via 720 may be connected to a different semiconductor device. For instance, one of the vias 710 may be connected to an electrode of a semiconductor device (e.g., a gate electrode, a source contact, or a drain contact of a transistor) versus the other via 720 may be connected to a different electrode of the same semiconductor device.
As shown in
The package substrate 2252 may include conductive contacts 2263 that are coupled to conductive pathways 2262 through the package substrate 2252, allowing circuitry within the dies 2256 and/or the interposer 2257 to electrically couple to various ones of the conductive contacts 2264 (or to other devices included in the package substrate 2252, not shown).
The IC package 2200 may include an interposer 2257 coupled to the package substrate 2252 via conductive contacts 2261 of the interposer 2257, first-level interconnects 2265, and the conductive contacts 2263 of the package substrate 2252. The first-level interconnects 2265 illustrated in
The IC package 2200 may include one or more dies 2256 coupled to the interposer 2257 via conductive contacts 2254 of the dies 2256, first-level interconnects 2258, and conductive contacts 2260 of the interposer 2257. The conductive contacts 2260 may be coupled to conductive pathways (not shown) through the interposer 2257, allowing circuitry within the dies 2256 to electrically couple to various ones of the conductive contacts 2261 (or to other devices included in the interposer 2257, not shown). The first-level interconnects 2258 illustrated in
In some embodiments, an underfill material 2266 may be disposed between the package substrate 2252 and the interposer 2257 around the first-level interconnects 2265, and a mold compound 2268 may be disposed around the dies 2256 and the interposer 2257 and in contact with the package substrate 2252. In some embodiments, the underfill material 2266 may be the same as the mold compound 2268. Example materials that may be used for the underfill material 2266 and the mold compound 2268 are epoxy mold materials, as suitable. Second-level interconnects 2270 may be coupled to the conductive contacts 2264. The second-level interconnects 2270 illustrated in
The dies 2256 may take the form of any of the embodiments of the die 2002 discussed herein and may include any of the embodiments of an IC device having DSA-based spacers and liners. In embodiments in which the IC package 2200 includes multiple dies 2256, the IC package 2200 may be referred to as a multi-chip package. Importantly, even in such embodiments of an MCP implementation of the IC package 2200, DSA-based spacers and liners may be provided in a single chip, in accordance with any of the embodiments described herein. The dies 2256 may include circuitry to perform any desired functionality. For example, one or more of the dies 2256 may be ESD protection dies, including DSA-based spacers and liners as described herein, one or more of the dies 2256 may be logic dies (e.g., silicon-based dies), one or more of the dies 2256 may be memory dies (e.g., high bandwidth memory), etc. In some embodiments, any of the dies 2256 may include DSA-based spacers and liners, e.g., metal lines as discussed above; in some embodiments, at least some of the dies 2256 may not include any III-N diodes with n-doped wells and capping layers.
The IC package 2200 illustrated in
In some embodiments, the circuit board 2302 may be a PCB including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 2302. In other embodiments, the circuit board 2302 may be a non-PCB substrate.
The IC device assembly 2300 illustrated in
The package-on-interposer structure 2236 may include an IC package 2320 coupled to an interposer 2304 by coupling components 2318. The coupling components 2318 may take any suitable form for the application, such as the forms discussed above with reference to the coupling components 2316. The IC package 2320 may be or include, for example, a die (the die 2002 of
The interposer 2304 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In some implementations, the interposer 2304 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. The interposer 2304 may include metal interconnects 2308 and vias 2310, including but not limited to TSVs 2306. The interposer 2304 may further include embedded devices 2314, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, ESD protection devices, and memory devices. More complex devices such as further RF devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer 2304. In some embodiments, the IC devices implementing DSA-based spacers and liners as described herein may also be implemented in/on the interposer 2304. The package-on-interposer structure 2236 may take the form of any of the package-on-interposer structures known in the art.
The IC device assembly 2300 may include an IC package 2324 coupled to the first face 2340 of the circuit board 2302 by coupling components 2322. The coupling components 2322 may take the form of any of the embodiments discussed above with reference to the coupling components 2316, and the IC package 2324 may take the form of any of the embodiments discussed above with reference to the IC package 2320.
The IC device assembly 2300 illustrated in
such that the IC package 2326 is disposed between the circuit board 2302 and the IC package 2332. The coupling components 2328 and 2330 may take the form of any of the embodiments of the coupling components 2316 discussed above, and the IC packages 2326 and 2332 may take the form of any of the embodiments of the IC package 2320 discussed above. The package-on-package structure 2234 may be configured in accordance with any of the package-on-package structures known in the art.
A number of components are illustrated in
Additionally, in various embodiments, the computing device 2400 may not include one or more of the components illustrated in
The computing device 2400 may include a processing device 2402 (e.g., one or more processing devices). As used herein, the term “processing device” or “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The processing device 2402 may include one or more digital signal processors (DSPs), application-specific ICs (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices. The computing device 2400 may include a memory 2404, which may itself include one or more memory devices such as volatile memory (e.g., DRAM), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and/or a hard drive. In some embodiments, the memory 2404 may include memory that shares a die with the processing device 2402. This memory may be used as cache memory and may include, e.g., eDRAM, and/or spin transfer torque magnetic random-access memory (STT-MRAM).
In some embodiments, the computing device 2400 may include a communication chip 2412 (e.g., one or more communication chips). For example, the communication chip 2412 may be configured for managing wireless communications for the transfer of data to and from the computing device 2400. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
The communication chip 2412 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultramobile broadband (UMB) project (also referred to as “3GPP2”), etc.). IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE 802.16 standards. The communication chip 2412 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 2412 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 2412 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication chip 2412 may operate in accordance with other wireless protocols in other embodiments. The computing device 2400 may include an antenna 2422 to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions).
In some embodiments, the communication chip 2412 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, the communication chip 2412 may include multiple communication chips. For instance, a first communication chip 2412 may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication chip 2412 may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication chip 2412 may be dedicated to wireless communications, and a second communication chip 2412 may be dedicated to wired communications.
In various embodiments, IC devices as described herein may be particularly advantageous for use as part of ESD circuits protecting power amplifiers, low-noise amplifiers, filters (including arrays of filters and filter banks), switches, or other active components. In some embodiments, IC devices as described herein may be used in PMICs, e.g., as a rectifying diode for large currents. In some embodiments, IC devices as described herein may be used in audio devices and/or in various input/output devices.
The computing device 2400 may include battery/power circuitry 2414. The battery/power circuitry 2414 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the computing device 2400 to an energy source separate from the computing device 2400 (e.g., AC line power).
The computing device 2400 may include a display device 2406 (or corresponding interface circuitry, as discussed above). The display device 2406 may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display, for example.
The computing device 2400 may include an audio output device 2408 (or corresponding interface circuitry, as discussed above). The audio output device 2408 may include any device that generates an audible indicator, such as speakers, headsets, or earbuds, for example.
The computing device 2400 may include an audio input device 2418 (or corresponding interface circuitry, as discussed above). The audio input device 2418 may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output).
The computing device 2400 may include a GPS device 2416 (or corresponding interface circuitry, as discussed above). The GPS device 2416 may be in communication with a satellite-based system and may receive a location of the computing device 2400, as known in the art.
The computing device 2400 may include another output device 2410 (or corresponding interface circuitry, as discussed above). Examples of the other output device 2410 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.
The computing device 2400 may include another input device 2420 (or corresponding interface circuitry, as discussed above). Examples of the other input device 2420 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.
The computing device 2400 may have any desired form factor, such as a handheld or mobile computing device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultramobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device. In some embodiments, the computing device 2400 may be any other electronic device that processes data.
The following paragraphs provide various examples of the embodiments disclosed herein.
Example 1 provides an IC device, including a layer, including a gate contact of a transistor, an additional contact of the transistor, and an electrical insulator between the gate contact and the additional contact; a first via over the layer in a direction, the first via connected to the gate contact; a second via over the layer in the direction, the second via connected to the additional contact; and an insulative structure over the layer in the direction, the insulative structure including a first insulative structure and a second insulative structure at least partially surrounding the first insulative structure, where the gate contact is in parallel with the additional contact, the gate contact is separated from the second via by the insulative structure, and a dimension of gate contact in the direction is the same or substantially the same as a dimension of the additional contact in the direction.
Example 2 provides the IC device according to example 1, where the first insulative structure is over the electrical insulator, and at least a portion of the second insulative structure is over the gate contact or the additional contact.
Example 3 provides the IC device according to example 1 or 2, where an edge of the first insulative structure is aligned with an edge of the gate contact or an edge of the additional contact in the direction.
Example 4 provides the IC device according to any of the preceding examples, where the insulative structure includes an electrical insulator that is different from the electrical insulator between the gate contact and the additional contact.
Example 5 provides the IC device according to any of the preceding examples, where the first insulative structure and the second insulative structure include different materials.
Example 6 provides the IC device according to any of the preceding examples, further including an additional insulative structure over the layer, where the additional contact is separated from the first via by the additional insulative structure.
Example 7 provides the IC device according to any of the preceding examples, where the gate contact is over at least part of a channel region of the transistor, and the additional contact is over at least part of a source region or a drain region of the transistor.
Example 8 provides an IC device, including a first conductive structure; a second conductive structure in parallel with the first conductive structure in a direction, where a dimension of the second conductive structure in the direction is the same or substantially the same as a dimension of the first conductive structure in the direction; an insulative structure including a first portion and a second portion, where the first portion is over the first conductive structure, and a second portion is over the second conductive structure; and a via connected to the first conductive structure, the via separated from the second conductive structure by the insulative structure.
Example 9 provides the IC device according to example 8, where the second conductive structure is separated from the first conductive structure by an electrical insulator, the insulative structure further includes a third portion, and the third portion is over the electrical insulator.
Example 10 provides the IC device according to example 9, where an edge of the third portion is aligned with an edge of the first conductive structure in the direction.
Example 11 provides the IC device according to example 10, where another edge of the third portion is aligned with an edge of the second conductive structure in the direction.
Example 12 provides the IC device according to example 9 or 10, where the insulative structure includes a different material from the electrical insulator.
Example 13 provides the IC device according to any one of examples 9-12, where the third portion includes a different material from the first portion or the second portion.
Example 14 provides the IC device according to any one of examples 8-13, further including an additional insulative structure between the second conductive structure and the first via.
Example 15 provides a method for forming an IC device, including forming a lamellar pattern over a layer, the layer including a first conductive structure and a second conductive structure, the lamellar pattern including first lamellar structures alternating with second lamella structures; forming a plurality of insulative structures based on the lamellar pattern, an individual insulative structure including a first insulative structure and a second insulative structures, the second insulative structure wrapping around at least part of the first insulative structure; providing a first via between two of the plurality of insulative structures, the first via connected to the first conductive structure; and providing a second via between another two of the plurality of insulative structures, the second via connected to the second conductive structure.
Example 16 provides the method according to example 15, where forming a plurality of first insulative structures based on the lamellar pattern includes forming a plurality of first insulative structures, which includes the first insulative structure, over the layer based on the lamellar pattern; and after forming the plurality of first insulative structures, forming a plurality of second insulative structures, which includes the second insulative structure.
Example 17 provides the method according to example 16, where forming the plurality of second insulative structures includes depositing an insulative material onto the layer.
Example 18 provides the method according to any one of examples 15-17, where the first insulative structure and the second conductive structure include different materials.
Example 19 provides the method according to any one of examples 15-18, where the first via is further connected to a gate electrode of a transistor.
Example 20 provides the method according to example 19, where the second via is further connected to a conductive contact of a source region or a drain region of the transistor.
Example 21 provides an IC package, including the IC device according to any one of examples 1-14; and a further IC component, coupled to the device.
Example 22 provides the IC package according to example 21, where the further IC component includes one of a package substrate, an interposer, or a further IC die.
Example 23 provides the IC package according to example 21 or 22, where the IC device according to any one of examples 1-14 may include, or be a part of, at least one of a memory device, a computing device, a wearable device, a handheld electronic device, and a wireless communications device.
Example 24 provides an electronic device, including a carrier substrate; and one or more of the IC devices according to any one of examples 1-14 and the IC package according to any one of examples 21-23, coupled to the carrier substrate.
Example 25 provides the electronic device according to example 24, where the carrier substrate is a motherboard.
Example 26 provides the electronic device according to example 24, where the carrier substrate is a PCB.
Example 27 provides the electronic device according to any one of examples 24-26, where the electronic device is a wearable electronic device or handheld electronic device.
Example 28 provides the electronic device according to any one of examples 24-27, where the electronic device further includes one or more communication chips and an antenna.
Example 29 provides the electronic device according to any one of examples 24-28, where the electronic device is an RF transceiver.
Example 30 provides the electronic device according to any one of examples 24-28, where the electronic device is one of a switch, a power amplifier, a low-noise amplifier, a filter, a filter bank, a duplexer, an upconverter, or a downconverter of an RF communications device, e.g., of an RF transceiver.
Example 31 provides the electronic device according to any one of examples 24-30, where the electronic device is a computing device.
Example 32 provides the electronic device according to any one of examples 24-31, where the electronic device is included in a base station of a wireless communication system.
Example 33 provides the electronic device according to any one of examples 24-31, where the electronic device is included in a user equipment device of a wireless communication system.
Example 34 provides the method according to any one of examples 15-20, further including processes for forming the IC device according to any one of claims 1-14.
Example 35 provides the method according to any one of examples 15-20, further including processes for forming the IC package according to any one of the claims 21-23.
Example 36 provides the method according to any one of examples 15-20, further including processes for forming the electronic device according to any one of the claims 24-33.
The above description of illustrated implementations of the disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. While specific implementations of, and examples for, the disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as those skilled in the relevant art will recognize. These modifications may be made to the disclosure in light of the above detailed description.
