Patent Application
20250219002
Circuit components, e.g., power delivery components such as inductors and capacitors, may be embedded within a core of a package substrate for an integrated circuit package. However, embedding components has proven to be difficult due to various factors, such as thickness mismatches between the core and the component, which can lead to tilting or shifting of the component within the cavity.
Embodiments of the present disclosure relate to processes for embedding interconnect bridge circuitry dies in multi-die integrated circuit packages. More specifically, embodiments herein are directed to techniques for forming surface finishes (SFs) on conductive contacts of a package substrate, e.g., on bumps within a cavity of a package substrate (cavity side bumps or CSBs) that are to connect to a die embedded within the cavity. As used herein, cavity side bumps (CSBs) may refer to conductive contacts of a package substrate that connect to a bottom side of an interconnect bridge circuitry die embedded within the package substrate, e.g., as shown in
Typically, surface finishes may be formed using electroless nickel electroless palladium immersion gold (ENEPIG), i.e., where nickel is deposited via electroless plating, palladium is also deposited via electroless plating, and gold is deposited via immersion plating. In fact, ENEPIG has been used for multiple generations of integrated circuit package designs due to its good solder joint reliability (SJR) and electromigration performance. A surface finish (SF) may refer to one or more material layers (e.g., metal layers) formed at a solderable area on a circuit board, e.g., formed on conductive contacts of an integrated circuit package substrate. Some recent process flows have utilized an electrolytic (e-lytic or elytic) SF (i.e., the SF is deposited using electrolytic plating) that includes palladium and gold formed on cavity side bumps (CSBs) of a package substrate to connect to an embedded interconnect bridge circuitry die with TSVs. However, omitting nickel in the SF for CSBs can lead to SJR concerns, e.g., due to potentially having copper diffused into the palladium and gold layers to form uncontrolled copper-tin inter-metallic compounds (IMCs). Additionally, to ensure minimal oxidation of the copper CSBs, higher thicknesses of palladium and gold may be needed (since there is no layer of nickel), which could lead to formation of PdSn4 and AuSn4 alloys that are highly brittle and cause failures (this may be referred to as palladium/gold embrittlement). Gold-only plating can lead to voids (due to the electrochemistry of copper vs gold), in addition to bath life concerns of gold bath from copper contamination. Similar concerns and effects have been raised and observed for PdAu plating as well.
Embodiments herein implement techniques that can address or avoid such issues. For example, some embodiments may implement a process flow that allows for the use of ENEPIG as a SF in an integrated circuit package substrate, which may avoid potential SJR concerns through the introduction of Ni, as well as concerns related to maximum current (Imax) limits due to the use of an ENEPIG SF. Some embodiments may implement a process flow that allows for the use of an ENEPIG SF with a relatively thin nickel layer. Other embodiments, however, may implement a process flow that allows for the use of immersion gold electroless palladium immersion gold (IGEPIG) as a SF in an integrated circuit package substrate. Other embodiments may implement a process flow that utilizes a SF that includes a layer of indium in addition to layers of palladium and gold, while other embodiments may implement a process flow that utilizes a SF that includes a layer of cobalt-iron in addition to layers of palladium and gold.
Accordingly, embodiments of the present disclosure may provide one or more advantages over existing process flows. As one example, the process flows described herein (e.g., those related to electroless plating) may offer cost reduction opportunities due to the reduction of an additional lithography step related to the deposition of e-lytic SF materials. Moreover, some embodiments may be able to use existing process flow steps and tools, allowing for faster and cheaper implementation of such processes. Further, embodiments herein may provide better SJR and Imax performance due to reductions in the formation of brittle IMCs and reduced IMC formation kinetics. Additionally, embodiments that involve electroless plating herein may have improved wettability due to full coverage of the SF (including the side of the pads), leading to low copper oxidation and uniform tin wicking. Other advantages may be apparent to those of skill in the art, and additional advantages are described below with respect to certain embodiments.
It will be understood that in the examples shown and described further below, the figures may not be drawn to scale and may not include all possible layers and/or circuit components. In addition, it will be understood that although certain figures illustrate designs with boundaries between surfaces being orthogonal (e.g., perpendicular), embodiments herein may implement such boundaries in a substantially orthogonal manner (e.g., within +/−5 or 10 degrees of orthogonality) due to fabrication methods used to create such devices or for other reasons.
Reference is now made to the drawings, which are not necessarily drawn to scale, wherein similar or same numbers may be used to designate the same or similar parts in different figures. The use of similar or same numbers in different figures does not mean all figures including similar or same numbers constitute a single or same embodiment. Like numerals having different letter suffixes may represent different instances of similar components. The drawings illustrate generally, by way of example, but not by way of limitation, various embodiments discussed in the present document.
Referring to
Referring then to
In some embodiments, the layer 302 may be between 5-10 um (e.g., 7 um) thick, the layer 304 may be between 0.01-0.10 um (e.g., 0.04 um) thick, and the layer 306 may be between 0.01-0.10 um (e.g., 0.06 um) thick. Some existing dies 220 have copper pads 221 or 222 that are approximately 15 um thick; however, because the layer 302 in the SF may be relatively thick, e.g., 7 um thick, embodiments herein may instead implement a die 220 having pads 221 or 222 with a reduced thickness, e.g., between 5-12 um, such as approximately 10 um, which can avoid potential chip gap height issues, i.e., issues related to the location of the top surface of the embedded interconnect bridge circuitry die 220 with respect to the top surface of the buildup layers 212. Mismatches in these heights can cause issues with connections to be made with integrated circuit dies above the die 220 or a top metallization layer of the buildup layer 212. Additional concerns of filling the cavity can also be present when attaching the interconnect bridge circuitry die 220 to the cavity 214. Any potential remaining height difference can be adjusted either in additional buildup layers to be formed or through thicker non-conductive film (NCF) around the die 220.
Other embodiments may avoid changes to the pads 221, 222 of the die and may instead incorporate a SF having the layer 302 be less than 500 nm thick, e.g., between 100-200 nm thick (e.g., 150 nm thick), which can avoid SJR issues through the inclusion of nickel, also avoid potential chip gap height concerns.
In other embodiments, the SF 216 may include the material stack shown in
Referring now to
Although a bridge circuitry die is described herein, other types of dies may be embedded within a cavity of a package substrate as described herein. For example, active circuit dies (e.g., an integrated circuit die) or another type of die (e.g., a die with one or more passive circuit components, e.g., capacitors or inductors) may be embedded in accordance with embodiments herein instead of an interconnect bridge circuitry die to interconnect multiple integrated circuit dies.
The example stack 500 includes IMCs 501 that are formed between the CSB pad 215 of the package substrate and solder 510 that is used to electrically connect the pads of a die (e.g., 221) to the pad 215. Although shown in particular layers, the IMCs 501 may be formed differently than shown. For example, the IMCs 501 may be interspersed or other IMCs may be present in the solder joint as well, e.g., Cu—Sn or Cu—Sn—Ni based IMCs.
The IMCs 501 are formed on a first layer 502 that includes nickel and phosphorous (Ni—P). The layer 502 may be the same or similar layer as layer 302 The IMCs 501 includes a first IMC 504 that also includes nickel and phosphorous (Ni3P and Ni), a second IMC 506 that includes tin, nickel and phosphorous (Sn-Ni—P), and a third IMC that includes copper, nickel, tin ((Cu,Ni)6Sn5), and palladium. The layer 502 may include phosphorous at approximately 10-35% by weight, the first IMC 504 may include phosphorous at approximately 15-30% by weight, and the third IMC 506 may include copper at approximately 20-40% by weight, nickel at approximately 20-40% by weight, and tin at approximately 30-50% by weight.
A cross-section and elemental analysis metrology performed on the solder joint might reveal the presence of the (Cu,Ni)6Sn5 IMC (and/or the other IMCs shown) and may reveal the presence of nickel and phosphorous in the nickel and palladium plating layers of the ENEPIG (to ensure use of electroless technique). Additionally, because e-lytic NiPdAu SFs need DFR, they may form stacked cylinder-like shapes with sharp corners (similar to copper bumps/pads like 215). ENEPIG, however, may be plated without DFR and thus may plate conformally on all sides of the copper bump 215 with rounded corners (e.g., similar to the form shown in
The IMCs include a first IMC 602 that includes copper and tin (Cu3Sn) and a second IMC 604 that includes copper, nickel, and tin ((Cu,Ni)6Sn5), and palladium. The first IMC 602 may include copper at approximately 60-75% by weight and tin at approximately 25-40% by weight. The second IMC 604 may include copper at approximately 30-50% by weight, nickel at approximately 10-30% by weight, and tin at approximately 30-50% by weight.
Similar to the previous example, a cross-section and elemental analysis metrology performed on the solder joint might reveal the presence of the (Cu,Ni)6Sn5 IMC, and may also reveal the presence of nickel from the use of the electroless technique for ENEPIG. Also, similar to the previous example, the ENEPIG may plate conformally on all sides of the copper bump 215 with rounded corners (e.g., similar to the form shown in
Similar to the previous examples, a cross-section and elemental analysis metrology performed on the cavity side bumps/package substrate might reveal the absence of nickel, e.g., in Ni—P or Ni6Sn5 IMCs in the solder joint. Also, similar to the previous examples, the IGEPIG may plate conformally on all sides of the copper bump 215 with rounded corners (e.g., similar to the form shown in
Referring to
For example, referring to
A thin indium layer such as 902 may provide a small change in the overall thickness of the SF 808 as compared with current process flows, and thus, might not cause chip gap height issues and can be implemented in current process flows with relatively little impact. In addition, an indium layer such as 902 can act as an active electromigration suppressor by backfilling electron voids created by tin during soldering. Thinner layers 902 (e.g., those closer to the 100 nm thickness) can provide improved Imax characteristics, while thicker layer 902 (e.g., those closer to the lum thickness) can also provide properties of a low temperature solder.
As another example, referring to
A layer having cobalt and iron, such as 1002, may have little to no change in properties with dopants, and thus, may be compatible with the palladium and gold deposited on it as in the examples shown in
Referring now to
Referring now to
Although a bridge circuitry die is described herein, other types of dies may be embedded within a cavity of a package substrate as described herein. For example, active circuit dies (e.g., an integrated circuit die) or another type of die (e.g., a die with one or more passive circuit components, e.g., capacitors or inductors) may be embedded in accordance with embodiments herein instead of an interconnect bridge circuitry die to interconnect multiple integrated circuit dies.
The example system 1300 of
Similar to the system 1300, the system 1310 also includes a circuit board 1312, which may be implemented as a motherboard or main board of a computer system in some embodiments. The system 1310 also includes a multi-die package 1314, which includes multiple integrated circuits/dies (e.g., 1306), and interconnections between the dies in one or more metallization layers. The multi-die package 1314 may include, for example, one or more silicon interposers, one or more silicon bridges embedded in the package substrate. For example, the package 1314 may include an embedded interconnect bridge circuitry die (e.g., an Intel® embedded multi-die interconnect bridge (EMIB) as described above.
The main circuit boards 1302, 1312 may provide electrical connections to other components of a computer system, e.g., memory, storage, network interfaces, peripheral devices, power supplies, etc. The main circuit board may include one or more traces and circuit components to provide interconnects between such computer system components.
The integrated circuit device 1500 may include one or more device layers 1504 disposed on the die substrate 1502. The device layer 1504 may include features of one or more transistors 1540 (e.g., metal oxide semiconductor field-effect transistors (MOSFETs) or ferroelectric field-effect transistors (FeFETs), e.g., those described herein) formed on the die substrate 1502. The transistors 1540 may include, for example, one or more source and/or drain (S/D) regions 1520, a gate 1522 to control current flow between the S/D regions 1520, and one or more S/D contacts 1524 to route electrical signals to/from the S/D regions 1520. The transistors 1540 may include additional features not depicted for the sake of clarity, such as device isolation regions, gate contacts, and the like. The transistors 1540 are not limited to the type and configuration depicted in
Returning to
The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric to improve its quality when a high-k material is used.
The gate electrode may be formed on the gate dielectric and may include at least one p-type work function metal or n-type work function metal, depending on whether the transistor 1540 is to be a p-type metal oxide semiconductor (PMOS) or an n-type metal oxide semiconductor (NMOS) transistor. In some implementations, the gate electrode may consist of a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer.
For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any of the metals discussed below with reference to an NMOS transistor (e.g., for work function tuning). For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals discussed above with reference to a PMOS transistor (e.g., for work function tuning).
In some embodiments, when viewed as a cross-section of the transistor 1540 along the source-channel-drain direction, the gate electrode may consist of a U-shaped structure that includes a bottom portion substantially parallel to the surface of the die substrate 1502 and two sidewall portions that are substantially perpendicular to the top surface of the die substrate 1502. In other embodiments, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the die substrate 1502 and does not include sidewall portions substantially perpendicular to the top surface of the die substrate 1502. In other embodiments, the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.
In some embodiments, a pair of sidewall spacers may be formed on opposing sides of the gate stack to bracket the gate stack. The sidewall spacers may be formed from materials such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In some embodiments, a plurality of spacer pairs may be used; for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.
The S/D regions 1520 may be formed within the die substrate 1502 adjacent to the gate 1522 of individual transistors 1540. The S/D regions 1520 may be formed using an implantation/diffusion process or an etching/deposition process, for example. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the die substrate 1502 to form the S/D regions 1520. An annealing process that activates the dopants and causes them to diffuse farther into the die substrate 1502 may follow the ion-implantation process. In the latter process, the die substrate 1502 may first be etched to form recesses at the locations of the S/D regions 1520. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the S/D regions 1520. In some implementations, the S/D regions 1520 may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In some embodiments, the S/D regions 1520 may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. In further embodiments, one or more layers of metal and/or metal alloys may be used to form the S/D regions 1520.
Electrical signals, such as power and/or input/output (I/O) signals, may be routed to and/or from the devices (e.g., transistors 1540) of the device layer 1504 through one or more interconnect layers disposed on the device layer 1504 (illustrated in
The interconnect structures 1528 may be arranged within the interconnect layers 1506-1510 to route electrical signals according to a wide variety of designs; in particular, the arrangement is not limited to the particular configuration of interconnect structures 1528 depicted in
In some embodiments, the interconnect structures 1528 may include lines 1528a and/or vias 1528b filled with an electrically conductive material such as a metal. The lines 1528a may be arranged to route electrical signals in a direction of a plane that is substantially parallel with a surface of the die substrate 1502 upon which the device layer 1504 is formed. For example, the lines 1528a may route electrical signals in a direction in and out of the page and/or in a direction across the page from the perspective of
The interconnect layers 1506-1510 may include a dielectric material 1526 disposed between the interconnect structures 1528, as shown in
A first interconnect layer 1506 (referred to as Metal 1 or “M1”) may be formed directly on the device layer 1504. In some embodiments, the first interconnect layer 1506 may include lines 1528a and/or vias 1528b, as shown. The lines 1528a of the first interconnect layer 1506 may be coupled with contacts (e.g., the S/D contacts 1524) of the device layer 1504. The vias 1528b of the first interconnect layer 1506 may be coupled with the lines 1528a of a second interconnect layer 1508.
The second interconnect layer 1508 (referred to as Metal 2 or “M2”) may be formed directly on the first interconnect layer 1506. In some embodiments, the second interconnect layer 1508 may include via 1528b to couple the lines 1528 of the second interconnect layer 1508 with the lines 1528a of a third interconnect layer 1510. Although the lines 1528a and the vias 1528b are structurally delineated with a line within individual interconnect layers for the sake of clarity, the lines 1528a and the vias 1528b may be structurally and/or materially contiguous (e.g., simultaneously filled during a dual-damascene process) in some embodiments.
The third interconnect layer 1510 (referred to as Metal 3 or “M3”) (and additional interconnect layers, as desired) may be formed in succession on the second interconnect layer 1508 according to similar techniques and configurations described in connection with the second interconnect layer 1508 or the first interconnect layer 1506. In some embodiments, the interconnect layers that are “higher up” in the metallization stack 1519 in the integrated circuit device 1500 (i.e., farther away from the device layer 1504) may be thicker that the interconnect layers that are lower in the metallization stack 1519, with lines 1528a and vias 1528b in the higher interconnect layers being thicker than those in the lower interconnect layers.
The integrated circuit device 1500 may include a solder resist material 1534 (e.g., polyimide or similar material) and one or more conductive contacts 1536 formed on the interconnect layers 1506-1510. In
In some embodiments in which the integrated circuit device 1500 is a double-sided die, the integrated circuit device 1500 may include another metallization stack (not shown) on the opposite side of the device layer(s) 1504. This metallization stack may include multiple interconnect layers as discussed above with reference to the interconnect layers 1506-1510, to provide conductive pathways (e.g., including conductive lines and vias) between the device layer(s) 1504 and additional conductive contacts (not shown) on the opposite side of the integrated circuit device 1500 from the conductive contacts 1536.
In other embodiments in which the integrated circuit device 1500 is a double-sided die, the integrated circuit device 1500 may include one or more through silicon vias (TSVs) through the die substrate 1502; these TSVs may make contact with the device layer(s) 1504, and may provide conductive pathways between the device layer(s) 1504 and additional conductive contacts (not shown) on the opposite side of the integrated circuit device 1500 from the conductive contacts 1536. In some embodiments, TSVs extending through the substrate can be used for routing power and ground signals from conductive contacts on the opposite side of the integrated circuit device 1500 from the conductive contacts 1536 to the transistors 1540 and any other components integrated into the die 1500, and the metallization stack 1519 can be used to route I/O signals from the conductive contacts 1536 to transistors 1540 and any other components integrated into the die 1500.
Multiple integrated circuit devices 1500 may be stacked with one or more TSVs in the individual stacked devices providing connection between one of the devices to any of the other devices in the stack. For example, one or more high-bandwidth memory (HBM) integrated circuit dies can be stacked on top of a base integrated circuit die and TSVs in the HBM dies can provide connection between the individual HBM and the base integrated circuit die. Conductive contacts can provide additional connections between adjacent integrated circuit dies in the stack. In some embodiments, the conductive contacts can be fine-pitch solder bumps (microbumps).
Additionally, in various embodiments, the electrical device 1600 may not include one or more of the components illustrated in
The electrical device 1600 may include one or more processor units 1602 (e.g., one or more processor units). As used herein, the terms “processor unit”, “processing unit” or “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The processor unit 1602 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), general-purpose GPUs (GPGPUs), accelerated processing units (APUs), field-programmable gate arrays (FPGAs), neural network processing units (NPUs), data processor units (DPUs), accelerators (e.g., graphics accelerator, compression accelerator, artificial intelligence accelerator), controller cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, controllers, or any other suitable type of processor units. As such, the processor unit can be referred to as an XPU (or xPU).
The electrical device 1600 may include a memory 1604, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM), static random-access memory (SRAM)), non-volatile memory (e.g., read-only memory (ROM), flash memory, chalcogenide-based phase-change non-voltage memories), solid state memory, and/or a hard drive. In some embodiments, the memory 1604 may include memory that is located on the same integrated circuit die as the processor unit 1602. This memory may be used as cache memory (e.g., Level 1 (L1), Level 2 (L2), Level 3 (L3), Level 4 (L4), Last Level Cache (LLC)) and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM).
In some embodiments, the electrical device 1600 can comprise one or more processor units 1602 that are heterogeneous or asymmetric to another processor unit 1602 in the electrical device 1600. There can be a variety of differences between the processing units 1602 in a system in terms of a spectrum of metrics of merit including architectural, microarchitectural, thermal, power consumption characteristics, and the like. These differences can effectively manifest themselves as asymmetry and heterogeneity among the processor units 1602 in the electrical device 1600.
In some embodiments, the electrical device 1600 may include a communication component 1612 (e.g., one or more communication components). For example, the communication component 1612 can manage wireless communications for the transfer of data to and from the electrical device 1600. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term “wireless” does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
The communication component 1612 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultra mobile broadband (UMB) project (also referred to as “3GPP2”), etc.). IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE 802.16 standards. The communication component 1612 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication component 1612 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication component 1612 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication component 1612 may operate in accordance with other wireless protocols in other embodiments. The electrical device 1600 may include an antenna 1622 to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions).
In some embodiments, the communication component 1612 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., IEEE 802.3 Ethernet standards). As noted above, the communication component 1612 may include multiple communication components. For instance, a first communication component 1612 may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication component 1612 may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication component 1612 may be dedicated to wireless communications, and a second communication component 1612 may be dedicated to wired communications.
The electrical device 1600 may include battery/power circuitry 1614. The battery/power circuitry 1614 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the electrical device 1600 to an energy source separate from the electrical device 1600 (e.g., AC line power).
The electrical device 1600 may include a display device 1606 (or corresponding interface circuitry, as discussed above). The display device 1606 may include one or more embedded or wired or wirelessly connected external visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.
The electrical device 1600 may include an audio output device 1608 (or corresponding interface circuitry, as discussed above). The audio output device 1608 may include any embedded or wired or wirelessly connected external device that generates an audible indicator, such speakers, headsets, or earbuds.
The electrical device 1600 may include an audio input device 1624 (or corresponding interface circuitry, as discussed above). The audio input device 1624 may include any embedded or wired or wirelessly connected device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output). The electrical device 1600 may include a Global Navigation Satellite System (GNSS) device 1618 (or corresponding interface circuitry, as discussed above), such as a Global Positioning System (GPS) device. The GNSS device 1618 may be in communication with a satellite-based system and may determine a geolocation of the electrical device 1600 based on information received from one or more GNSS satellites, as known in the art.
The electrical device 1600 may include an other output device 1610 (or corresponding interface circuitry, as discussed above). Examples of the other output device 1610 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.
The electrical device 1600 may include another input device 1620 (or corresponding interface circuitry, as discussed above). Examples of the other input device 1620 may include an accelerometer, a gyroscope, a compass, an image capture device (e.g., monoscopic or stereoscopic camera), a trackball, a trackpad, a touchpad, a keyboard, a cursor control device such as a mouse, a stylus, a touchscreen, proximity sensor, microphone, a bar code reader, a Quick Response (QR) code reader, electrocardiogram (ECG) sensor, PPG (photoplethysmogram) sensor, galvanic skin response sensor, any other sensor, or a radio frequency identification (RFID) reader.
The electrical device 1600 may have any desired form factor, such as a hand-held or mobile electrical device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a 2-in-1 convertible computer, a portable all-in-one computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra mobile personal computer, a portable gaming console, etc.), a desktop electrical device, a server, a rack-level computing solution (e.g., blade, tray or sled computing systems), a workstation or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a stationary gaming console, smart television, a vehicle control unit, a digital camera, a digital video recorder, a wearable electrical device or an embedded computing system (e.g., computing systems that are part of a vehicle, smart home appliance, consumer electronics product or equipment, manufacturing equipment). In some embodiments, the electrical device 1600 may be any other electronic device that processes data. In some embodiments, the electrical device 1600 may comprise multiple discrete physical components. Given the range of devices that the electrical device 1600 can be manifested as in various embodiments, in some embodiments, the electrical device 1600 can be referred to as a computing device or a computing system.
Illustrative examples of the technologies described throughout this disclosure are provided below. Embodiments of these technologies may include any one or more, and any combination of, the examples described below. In some embodiments, at least one of the systems or components set forth in one or more of the preceding figures may be configured to perform one or more operations, techniques, processes, and/or methods as set forth in the following examples.
Example A1 is an integrated circuit package substrate comprising: a plurality of metallization layers in dielectric buildup layers; a die within the buildup layers, the die comprising a conductive contact in electrical connection with a conductive contact of a metallization layer; and conductive materials between the conductive contact of the die and the conductive contact of the metallization layer, the conductive materials comprising nickel, phosphorous, tin, and palladium.
Example A2 includes the subject matter of Example A1, wherein the conductive materials comprise an intermetallic compound comprising nickel and phosphorous.
Example A3 includes the subject matter of Example A2, wherein the intermetallic compound comprises phosphorous at between 15-30% by weight.
Example A4 includes the subject matter of any one of Examples A1-A3, wherein the conductive materials comprise an intermetallic compound comprising copper, nickel, tin, and palladium.
Example A5 includes the subject matter of Example A4, wherein the intermetallic compound comprises copper at between 20-40% by weight, nickel at between 20-40% by weight, and tin at between 30-50% by weight.
Example A6 includes the subject matter of any one of Examples A1-A5, wherein the conductive materials comprise an intermetallic compound comprising nickel, tin, and phosphorous.
Example A7 includes the subject matter of any one of Examples A1-A6, wherein the conductive materials comprise a layer on the conductive pads of the metallization layer comprising nickel and phosphorous.
Example A8 includes the subject matter of any one of Examples A1-A7, wherein the die is an interconnect bridge circuitry die.
Example A9 includes the subject matter of Example A8, wherein the interconnect bridge circuitry die comprises a through silicon via (TSV) connected to the conductive contact of the die.
Example A10 includes the subject matter of any one of Examples A1-A9, wherein the die is encapsulated in a cavity or opening in the buildup layers.
Example A11 is an integrated circuit package comprising: an integrated circuit package substrate comprising: a plurality of metallization layers in dielectric buildup layers; an interconnect bridge circuitry die embedded in the buildup layers, the interconnect bridge circuitry die comprising a via connected between a first conductive contact on a first side of the interconnect bridge circuitry die and a second conductive contact on a second side of the interconnect bridge circuitry die opposite the first side, the second conductive contact in electrical connection with a conductive contact of a metallization layer; and conductive materials between the second conductive contact of the interconnect bridge circuitry die and the conductive contact of the metallization layer, the conductive materials comprising nickel, phosphorous, tin, and palladium; and integrated circuit dies coupled to the package substrate, at least two integrated circuit dies interconnected by the interconnect bridge circuitry die.
Example A12 includes the subject matter of Example A11, wherein the conductive materials comprise an intermetallic compound comprising nickel and phosphorous.
Example A13 includes the subject matter of Example A12, wherein the intermetallic compound comprises phosphorous at between 15-30% by weight.
Example A14 includes the subject matter of any one of Examples A11-A13, wherein the conductive materials comprise an intermetallic compound comprising copper, nickel, tin, and palladium.
Example A15 includes the subject matter of Example A14, wherein the intermetallic compound comprises copper at between 20-40% by weight, nickel at between 20-40% by weight, and tin at between 30-50% by weight.
Example A16 includes the subject matter of any one of Examples A11-A15, wherein the conductive materials comprise an intermetallic compound comprising nickel, tin, and phosphorous.
Example A17 includes the subject matter of any one of Examples A11-A16, wherein the conductive materials comprise a layer on the conductive pads of the metallization layer comprising nickel and phosphorous.
Example A18 is an method of forming an integrated circuit package substrate comprising: forming buildup layers on a core layer, the buildup layers comprising a plurality of metallization layers; forming a cavity in the buildup layers to expose a subset of conductive contacts of a metallization layer; forming a first surface finish layer on the subset of conductive contacts, the first surface finish layer comprising nickel and having a thickness that is greater than 5 um; forming a second surface finish layer on the first surface finish layer, the second surface finish layer comprising palladium; forming a third surface finish layer on the second surface finish layer, the second surface finish layer comprising gold; placing a die within the cavity such that conductive contacts of the die are in electrical connection with the subset of conductive contacts.
Example A19 includes the subject matter of Example A18, wherein the first surface finish layer is formed using electroless plating, the second surface finish layer is formed using electroless plating, and the third surface finish layer is formed using immersion plating.
Example A20 includes the subject matter of Example A18 or A19, wherein the first surface finish layer is between 5-10 um thick, the second surface finish layer is between 0.01-0.10 um thick, and the third surface finish layer is between 0.01-0.10 um thick.
Example B1 is an integrated circuit package substrate comprising: a plurality of metallization layers in dielectric buildup layers; a die within the buildup layers, the die comprising a conductive contact in electrical connection with a conductive contact of a metallization layer; and conductive materials between the conductive contact of the die and the conductive contact of the metallization layer, the conductive materials comprising copper, nickel, tin, and palladium.
Example B2 includes the subject matter of Example B1, wherein the conductive materials comprise an intermetallic compound comprising copper and tin.
Example B3 includes the subject matter of Example B2, wherein the intermetallic compound comprises copper at between 60-75% by weight and tin at between 25-40% by weight.
Example B4 includes the subject matter of any one of Examples B1-B3, wherein the conductive materials comprise an intermetallic compound comprising copper, nickel, tin, and palladium.
Example B5 includes the subject matter of Example B4, wherein the intermetallic compound comprises copper at between 30-50% by weight, nickel at between 10-30% by weight, and tin at between 30-50% by weight.
Example B6 includes the subject matter of any one of Examples B1-B5, wherein the die is an interconnect bridge circuitry die.
Example B7 includes the subject matter of Example B6, wherein the interconnect bridge circuitry die comprises a through silicon via (TSV) connected to the conductive contact of the die.
Example B8 includes the subject matter of any one of Examples B1-B7, wherein the conductive materials are conformally around the conductive contact of the metallization layer.
Example B9 is an integrated circuit package comprising: an integrated circuit package substrate comprising: a plurality of metallization layers in dielectric buildup layers; an interconnect bridge circuitry die embedded in the buildup layers, the interconnect bridge circuitry die comprising a via connected between a first conductive contact on a first side of the interconnect bridge circuitry die and a second conductive contact on a second side of the interconnect bridge circuitry die opposite the first side, the second conductive contact in electrical connection with a conductive contact of a metallization layer; and conductive materials between the second conductive contact of the interconnect bridge circuitry die and the conductive contact of the metallization layer, the conductive materials comprising copper, nickel, tin, and palladium; and integrated circuit dies coupled to the package substrate, at least two integrated circuit dies interconnected by the interconnect bridge circuitry die.
Example B10 includes the subject matter of Example B9, wherein the conductive materials comprise an intermetallic compound comprising copper and tin.
Example B11 includes the subject matter of Example B10, wherein the intermetallic compound comprises copper at between 60-75% by weight and tin at between 25-40% by weight.
Example B12 includes the subject matter of any one of Examples B9-B11, wherein the conductive materials comprise an intermetallic compound comprising copper, nickel, tin, and palladium.
Example B13 includes the subject matter of Example B12, wherein the intermetallic compound comprises copper at between 30-50% by weight, nickel at between 10-30% by weight, and tin at between 30-50% by weight.
Example B14 includes the subject matter of any one of Examples B9-B13, wherein the second conductive contact of the interconnect bridge circuitry die has a thickness greater than 12 um.
Example B15 includes the subject matter of any one of Examples B9-B14, wherein the conductive materials are conformally around the conductive contact of the metallization layer.
Example B16 is a method of forming an integrated circuit package substrate comprising: forming buildup layers on a core layer, the buildup layers comprising a plurality of metallization layers; forming a cavity in the buildup layers to expose a subset of conductive contacts of a metallization layer; forming a first surface finish layer on the subset of conductive contacts, the first surface finish layer comprising nickel and having a thickness that is less than 500 nm; forming a second surface finish layer on the first surface finish layer, the second surface finish layer comprising palladium; forming a third surface finish layer on the second surface finish layer, the second surface finish layer comprising gold; placing a die within the cavity such that conductive contacts of the die are in electrical connection with the subset of conductive contacts.
Example B17 includes the subject matter of Example B16, wherein the first surface finish layer is formed using electroless plating, the second surface finish layer is formed using electroless plating, and the third surface finish layer is formed using immersion plating.
Example B18 includes the subject matter of Example B16 or B17, wherein the first surface finish layer is between 100-200 nm thick, the second surface finish layer is between 0.01-0.10 um thick, and the third surface finish layer is between 0.01-0.10 um thick.
Example B19 includes the subject matter of Example B18, wherein the first surface finish layer is approximately 150 nm thick, the second surface finish layer is approximately 0.04 um thick, and the third surface finish layer is approximately 0.06 um thick.
Example B20 includes the subject matter of any one of Examples B16-B19, wherein the first surface finish layer is formed conformally around each conductive contact of the subset of conductive contacts.
Example C1 is an integrated circuit package substrate comprising: a plurality of metallization layers in dielectric buildup layers; a die within the buildup layers, the die comprising a conductive contact in electrical connection with a conductive contact of a metallization layer; and conductive materials between the conductive contact of the die and the conductive contact of the metallization layer, the conductive materials comprising copper and tin.
Example C2 includes the subject matter of Example C1, wherein the conductive materials comprise an intermetallic compound comprising copper and tin.
Example C3 includes the subject matter of Example C2, wherein the intermetallic compound comprises copper at between 60-75% by weight and tin at between 25-40% by weight.
Example C4 includes the subject matter of Example C2, wherein the intermetallic compound is a first intermetallic compound, and the conductive materials further comprise a second intermetallic compound comprising copper and tin.
Example C5 includes the subject matter of Example C4, wherein the second intermetallic compound comprises copper at between 50-70% by weight and tin at between 30-50% by weight.
Example C6 includes the subject matter of any one of Examples C1-C5, wherein the conductive materials do not include nickel.
Example C7 includes the subject matter of any one of Examples C1-C6, wherein the die is an interconnect bridge circuitry die.
Example C8 includes the subject matter of Example C7, wherein the interconnect bridge circuitry die comprises a through silicon via (TSV) connected to the conductive contact of the die.
Example C9 is an integrated circuit package comprising: an integrated circuit package substrate comprising: a plurality of metallization layers in dielectric buildup layers; an interconnect bridge circuitry die embedded in the buildup layers, the interconnect bridge circuitry die comprising a via connected between a first conductive contact on a first side of the interconnect bridge circuitry die and a second conductive contact on a second side of the interconnect bridge circuitry die opposite the first side, the second conductive contact in electrical connection with a conductive contact of a metallization layer; and conductive materials between the second conductive contact of the interconnect bridge circuitry die and the conductive contact of the metallization layer, the conductive materials comprising copper and tin; and integrated circuit dies coupled to the package substrate, at least two integrated circuit dies interconnected by the interconnect bridge circuitry die.
Example C10 includes the subject matter of Example C9, wherein the conductive materials comprise an intermetallic compound comprising copper and tin.
Example C11 includes the subject matter of Example C10, wherein the intermetallic compound comprises copper at between 60-75% by weight and tin at between 25-40% by weight.
Example C12 includes the subject matter of Example C10, wherein the intermetallic compound is a first intermetallic compound, and the conductive materials further comprise a second intermetallic compound comprising copper and tin.
Example C13 includes the subject matter of Example C12, wherein the second intermetallic compound comprises copper at between 50-70% by weight and tin at between 30-50% by weight.
Example C14 includes the subject matter of any one of Examples C9-C13, wherein the conductive materials do not include nickel.
Example C15 is a method of forming an integrated circuit package substrate comprising: forming buildup layers on a core layer, the buildup layers comprising a plurality of metallization layers; forming a cavity in the buildup layers to expose a subset of conductive contacts of a metallization layer; forming a first surface finish layer on the subset of conductive contacts, the first surface finish layer comprising gold; forming a second surface finish layer on the first surface finish layer, the second surface finish layer comprising palladium; forming a third surface finish layer on the second surface finish layer, the second surface finish layer comprising gold; placing a die within the cavity such that conductive contacts of the die are in electrical connection with the subset of conductive contacts.
Example C16 includes the subject matter of Example C15, wherein the first surface finish layer is formed using immersion plating, the second surface finish layer is formed using electroless plating, and the third surface finish layer is formed using immersion plating.
Example C17 includes the subject matter of Example C15 or C16, wherein the first surface finish layer is between 0.01-0.04 um thick, the second surface finish layer is between 0.02-0.15 um thick, and the third surface finish layer is between 0.03-0.10 um thick.
Example C18 includes the subject matter of Example C17, wherein the first surface finish layer is approximately 0.02 um thick, the second surface finish layer is approximately 0.10 um thick, and the third surface finish layer is approximately 0.08 um thick.
Example C19 includes the subject matter of any one of Examples C15-C18, wherein none of the first surface finish layer, the second finish layer, and the third surface finish layer include nickel.
Example C20 includes the subject matter of any one of Examples C15-C18, wherein the first surface finish layer is formed conformally around each conductive contact of the subset of conductive contacts.
Example D1 is an integrated circuit package substrate comprising: a plurality of metallization layers in dielectric buildup layers; a die within the buildup layers, the die comprising a conductive contact in electrical connection with a conductive contact of a metallization layer; and conductive materials between the conductive contact of the die and the conductive contact of the metallization layer, the conductive materials comprising indium and tin.
Example D2 includes the subject matter of Example D1, wherein the conductive materials comprise an intermetallic compound comprising indium and tin.
Example D3 includes the subject matter of Example D2, wherein the intermetallic compound comprises indium at between 1-5% by weight and tin at between 95-99% by weight.
Example D4 includes the subject matter of Example D2 or D3, wherein the conductive materials further comprise a layer comprising indium between the conductive contact of the metallization layer and the intermetallic compound.
Example D5 includes the subject matter of any one of Examples D1-D4, wherein the die is an interconnect bridge circuitry die.
Example D6 includes the subject matter of Example D5, wherein the interconnect bridge circuitry die comprises a through silicon via (TSV) connected to the conductive contact of the die.
Example D7 includes the subject matter of any one of Examples D1-D6, wherein the conductive materials are not conformally around the conductive contact of the metallization layer.
Example D8 includes the subject matter of any one of Examples D1-D7, wherein the conductive materials do not include nickel.
Example D9 is an integrated circuit package comprising: an integrated circuit package substrate comprising: a plurality of metallization layers in dielectric buildup layers; an interconnect bridge circuitry die embedded in the buildup layers, the interconnect bridge circuitry die comprising a via connected between a first conductive contact on a first side of the interconnect bridge circuitry die and a second conductive contact on a second side of the interconnect bridge circuitry die opposite the first side, the second conductive contact in electrical connection with a conductive contact of a metallization layer; and conductive materials between the second conductive contact of the interconnect bridge circuitry die and the conductive contact of the metallization layer, the conductive materials comprising indium and tin; and integrated circuit dies coupled to the package substrate, at least two integrated circuit dies interconnected by the interconnect bridge circuitry die.
Example D10 includes the subject matter of Example D9, wherein the conductive materials comprise an intermetallic compound comprising indium and tin.
Example D11 includes the subject matter of Example D10, wherein the intermetallic compound comprises indium at between 1-5% by weight and tin at between 95-99% by weight.
Example D12 includes the subject matter of Example D10 or D11, wherein the conductive materials further comprise a layer comprising indium between the conductive contact of the metallization layer and the intermetallic compound.
Example D13 includes the subject matter of any one of Examples D10-D12, wherein the conductive materials are not conformally around the conductive contact of the metallization layer.
Example D14 includes the subject matter of any one of Examples D10-D13, wherein the second conductive contact of the interconnect bridge circuitry die has a thickness greater than 12 um.
Example D15 includes the subject matter of any one of Examples D10-D14, wherein the conductive materials do not include nickel.
Example D16 is a method of forming an integrated circuit package substrate comprising: forming first buildup layers on a core layer, the first buildup layers comprising a plurality of metallization layers; forming a first surface finish layer on a subset of conductive contacts of a metallization layer of the first buildup layers, the first surface finish layer comprising indium; forming a second surface finish layer on the first surface finish layer, the second surface finish layer comprising palladium; forming a third surface finish layer on the second surface finish layer, the second surface finish layer comprising gold; forming second buildup layers on the first buildup layers; forming a cavity in the second buildup layers above the subset of conductive contacts; and placing a die within the cavity such that conductive contacts of the die are in electrical connection with the subset of conductive contacts.
Example D17 includes the subject matter of Example D16, wherein the first surface finish layer is formed via electrolytic plating, the second surface finish layer is formed via electrolytic plating, and the third surface finish layer is formed via electrolytic plating.
Example D18 includes the subject matter of Example D16 or D17, wherein the first surface finish layer is between 0.10-1 um thick, the second surface finish layer is between 0.01-0.10 um thick, and the third surface finish layer is between 0.01-0.10 um thick.
Example D19 includes the subject matter of Example D18, wherein the first surface finish layer is approximately 1 um thick, the second surface finish layer is approximately 0.04 um thick, and the third surface finish layer is approximately 0.06 um thick.
Example D20 includes the subject matter of any one of Examples D16-D19, wherein the first surface finish layer is not formed conformally around each conductive contact of the subset of conductive contacts.
Example E1 is an integrated circuit package substrate comprising: a plurality of metallization layers in dielectric buildup layers; a die within the buildup layers, the die comprising a conductive contact in electrical connection with a conductive contact of a metallization layer; and conductive materials between the conductive contact of the die and the conductive contact of the metallization layer, the conductive materials comprising cobalt, iron, and tin.
Example E2 includes the subject matter of Example E1, wherein the conductive materials comprise an intermetallic compound comprising cobalt, iron, and tin.
Example E3 includes the subject matter of Example E2, wherein the intermetallic compound comprises cobalt at between 20-35% by weight, iron at between 10-30% by weight, and tin at between 65-85% by weight.
Example E4 includes the subject matter of Example E2 or E3, wherein the conductive materials further comprise a layer comprising cobalt and iron between the conductive contact of the metallization layer and the intermetallic compound.
Example E5 includes the subject matter of any one of Examples E1-E4, wherein the die is an interconnect bridge circuitry die.
Example E6 includes the subject matter of Example E5, wherein the interconnect bridge circuitry die comprises a through silicon via (TSV) connected to the conductive contact of the die.
Example E7 includes the subject matter of any one of Examples E1-E6, wherein the conductive materials are not conformally around the conductive contact of the metallization layer.
Example E8 includes the subject matter of any one of Examples E1-E7, wherein the conductive materials do not include nickel.
Example E9 is an integrated circuit package comprising: an integrated circuit package substrate comprising: a plurality of metallization layers in dielectric buildup layers; an interconnect bridge circuitry die embedded in the buildup layers, the interconnect bridge circuitry die comprising a via connected between a first conductive contact on a first side of the interconnect bridge circuitry die and a second conductive contact on a second side of the interconnect bridge circuitry die opposite the first side, the second conductive contact in electrical connection with a conductive contact of a metallization layer; and conductive materials between the second conductive contact of the interconnect bridge circuitry die and the conductive contact of the metallization layer, the conductive materials comprising cobalt, iron, and tin; and integrated circuit dies coupled to the package substrate, at least two integrated circuit dies interconnected by the interconnect bridge circuitry die.
Example E10 includes the subject matter of Example E9, wherein the conductive materials comprise an intermetallic compound comprising cobalt, iron, and tin.
Example E11 includes the subject matter of Example E10, wherein the intermetallic compound comprises cobalt at between 20-35% by weight, iron at between 10-30% by weight, and tin at between 65-85% by weight.
Example E12 includes the subject matter of Example E10 or E11, wherein the conductive materials further comprise a layer comprising cobalt and iron between the conductive contact of the metallization layer and the intermetallic compound.
Example E13 includes the subject matter of any one of Examples E10-E12, wherein the conductive materials are not conformally around the conductive contact of the metallization layer.
Example E14 includes the subject matter of any one of Examples E10-E13, wherein the second conductive contact of the interconnect bridge circuitry die has a thickness greater than 12 um.
Example E15 includes the subject matter of any one of Examples E10-E14, wherein the conductive materials do not include nickel.
Example E16 is a method of forming an integrated circuit package substrate comprising: forming first buildup layers on a core layer, the first buildup layers comprising a plurality of metallization layers; forming a first surface finish layer on a subset of conductive contacts of a metallization layer of the first buildup layers, the first surface finish layer comprising cobalt and iron; forming a second surface finish layer on the first surface finish layer, the second surface finish layer comprising palladium; forming a third surface finish layer on the second surface finish layer, the second surface finish layer comprising gold; forming second buildup layers on the first buildup layers; forming a cavity in the second buildup layers above the subset of conductive contacts; and placing a die within the cavity such that conductive contacts of the die are in electrical connection with the subset of conductive contacts.
Example E17 includes the subject matter of Example E16, wherein the first surface finish layer is formed via electrolytic plating, the second surface finish layer is formed via electrolytic plating, and the third surface finish layer is formed via electrolytic plating.
Example E18 includes the subject matter of Example E16 or E17, wherein the first surface finish layer is between 2-4 um thick, the second surface finish layer is between 0.01-0.10 um thick, and the third surface finish layer is between 0.01-0.10 um thick.
Example E19 includes the subject matter of Example E18, wherein the first surface finish layer is approximately 3.3 um thick, the second surface finish layer is approximately 0.04 um thick, and the third surface finish layer is approximately 0.06 um thick.
Example E20 includes the subject matter of any one of Examples E16-E19, wherein the first surface finish layer is not formed conformally around each conductive contact of the subset of conductive contacts.
In the above description, various aspects of the illustrative implementations have been described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. However, it will be apparent to those skilled in the art that the present disclosure may be practiced with only some of the described aspects. For purposes of explanation, specific numbers, materials, and configurations have been set forth to provide a thorough understanding of the illustrative implementations. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without all of the specific details. In other instances, well-known features have been omitted or simplified in order not to obscure the illustrative implementations.
For the purposes of the present disclosure, the phrase “A and/or B” means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).
The terms “over,” “under,” “between,” “above,” and “on” as used herein may refer to a relative position of one material layer or component with respect to other layers or components. For example, one layer disposed over or under another layer may be directly in contact with the other layer or may have one or more intervening layers. Moreover, one layer disposed between two layers may be directly in contact with the two layers or may have one or more intervening layers. In contrast, a first layer “on” a second layer is in direct contact with that second layer. Similarly, unless explicitly stated otherwise, one feature disposed between two features may be in direct contact with the adjacent features or may have one or more intervening features.
The above description may use the phrases “in an embodiment,” or “in embodiments,” which may each refer to one or more of the same or different embodiments. Furthermore, the terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present disclosure, are synonymous.
The term “coupled with,” along with its derivatives, may be used herein. “Coupled” may mean one or more of the following. “Coupled” may mean that two or more elements are in direct physical or electrical contact. However, “coupled” may also mean that two or more elements indirectly contact each other, but yet still cooperate or interact with each other, and may mean that one or more other elements are coupled or connected between the elements that are said to be coupled with each other. The term “directly coupled” may mean that two or more elements are in direct contact.
In various embodiments, the phrase “a first feature formed, deposited, or otherwise disposed on a second feature” may mean that the first feature is formed, deposited, or disposed over the second feature, and at least a part of the first feature may be in direct contact (e.g., direct physical and/or electrical contact) or indirect contact (e.g., having one or more other features between the first feature and the second feature) with at least a part of the second feature.
In various embodiments, the phrase “located on” in the context of a first layer or component located on a second layer or component refers to the first layer or component being directly physically attached to the second part or component (no layers or components between the first and second layers or components) or physically attached to the second layer or component with one or more intervening layers or components.
In various embodiments, the term “adjacent” refers to layers or components that are in physical contact with each other. That is, there is no layer or component between the stated adjacent layers or components. For example, a layer X that is adjacent to a layer Y refers to a layer that is in physical contact with layer Y.
Where the disclosure recites “a” or “a first” element or the equivalent thereof, such disclosure includes one or more such elements, neither requiring nor excluding two or more such elements. Further, ordinal indicators (e.g., first, second, or third) for identified elements are used to distinguish between the elements, and do not indicate or imply a required or limited number of such elements, nor do they indicate a particular position or order of such elements unless otherwise specifically stated.
