Patent Application
20180240738
The present invention generally relates to an electronic package that incorporates an electronic component such as a discrete passive device. More particularly, the invention relates to structures and methods for fabricating a substrate-less electronic package that incorporates a metal shielding layer against electromagnetic interference.
As known in the art, an electronic package typically comprises a package substrate (or a printed wiring board), an electronic component that is mechanically and electrically connected to the package substrate (or a printed circuit board), a molding compound that encapsulates the electronic component and the package substrate.
The molding compound protects the electronic component and the electrical connections between the electronic component and the package substrate from mechanical and environmental damage. The RF shielding housing is often required for electronic packages, to protect the device from electromagnetic interference (EMI) which degrades device performance.
The electronic component is typically attached to the package substrate by using solder and surface mount technique (SMT). The package substrate generally includes dielectric layers and metal layers such as copper traces. The RF shielding housing is electrically connected to one of the metal layers of the package substrate.
However, the above-described electronic package has several drawbacks. For example, during a reflow soldering process or a moisture sensitivity level (MSL) test, the solder between the electronic component and the package substrate may be melted and the volume of the solder may change, which may cause extra stress to the electronic component, resulting in solder extrusion, delamination of the packaging materials, broken of the electronic component, or bond damage.
In addition to the need to improve the structural strength of the miniaturized electronic package, how to incorporate the EMI protection at the bottom of the electronic package, to avoid interference by the EMI below the electronic package, is currently one of the problems to be solved.
According to one aspect of the invention, an electronic package includes an electronic component, a leadframe surrounding at least one sidewall surface of the electronic component, a molding compound encapsulating the leadframe and the electronic component, and a metal shielding layer conformally covering the molding compound. The metal shielding layer is electrically connected with the leadframe. The leadframe comprises at least one opening for accommodating the electronic component. A lower portion of the electronic component is situated in the opening and a bottom surface of the electronic component is exposed from the opening.
According to another aspect of the invention, a method for fabricating an electronic package is disclosed. A carrier substrate having a release film thereon is provided. A leadframe is formed on the release film. An electronic component is mounted on the release film. The leadframe surrounds the electronic component. The leadframe comprises at least one opening for accommodating the electronic component, wherein a lower portion of the electronic component is situated in the opening and a bottom surface of the electronic component is exposed from the opening. A molding process is performed to form a molding compound encapsulating the electronic component and the leadframe. The carrier substrate and the release film are removed. A metal shielding layer is coated on the molding compound.
According to still another aspect of the invention, an electronic package includes an electronic component. A leadframe surrounds at least one sidewall surface of the electronic component. The leadframe comprises at least one opening for accommodating the electronic component, wherein a lower portion of the electronic component is situated in the opening and a bottom surface of the electronic component is exposed from the opening. A molding compound encapsulates the leadframe and the electronic component. A re-distribution layer is disposed on the molding compound and on the bottom surface of the electronic component. The re-distribution layer comprises at least a dielectric layer and at least a metal layer. A metal shielding layer conformally covers the molding compound and is electrically connected with the metal layer of the re-distribution layer.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
The accompanying drawings are included to provide a further understanding of the embodiments, and are incorporated in and constitute apart of this specification. The drawings illustrate some of the embodiments and, together with the description, serve to explain their principles. In the drawings:
In the following detailed description of the disclosure, reference is made to the accompanying drawings, which form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural changes may be made without departing from the scope of the present disclosure.
The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, along with the full scope of equivalents to which such claims are entitled.
One or more implementations of the present invention will now be described with reference to the attached drawings, wherein like reference numerals are used to refer to like elements throughout, and wherein the illustrated structures are not necessarily drawn to scale. The terms “die”, “chip”, “semiconductor chip”, and “semiconductor die” are used interchangeable throughout the specification.
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Subsequently, a leadframe 14 is disposed on a top surface of the release film 12. The leadframe 14 may be a metal leadframe and may comprise openings 201-205. Each of the openings 201-205 exposes a portion of the top surface of the release film 12. Each of the openings 201-205 is used to accommodate an electronic component. According to another embodiment, the leadframe 14 may comprise only one opening that accommodates multiple electronic components.
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According to the embodiment, the leadframe 14 surrounds each of the electronic components 21-25. In some embodiments, when viewed from the above, some of the leadframe openings may comprise discontinuity along the edge of the module, for example, U shaped leadframe openings, such that the internal stress of the module may be released at the edge of the module (the open end of the U shaped leadframe opening), and therefore the cracking of the module may be avoided. In a case that an electrode is disposed on a sidewall and a bottom of each of the electronic components 21-25 extending from the sidewall to bottom. The leadframe 14 is not in direct contact with non-ground type electrodes or each of the electronic components 21-25 on sidewall such that the leadframe 14 is not electrically connected to non-ground type electrodes or the electrode of each of the electronic components 21-25. By providing such configuration (i.e. the leadframe is not electrically connected to the device electrodes), a better shielding effect can be achieved. However, in some embodiments, the leadframe may be electrically connected to a grounded electrode of the electronic components 21-25. According to the embodiment, the electrodes 21a-25a of the electronic components 21-25 may be copper electrodes with soldering interface, for example, plated nickel, copper-tin alloy and/or tin. According to the embodiment, the leadframe 14 is a layer of metal such as copper that is substantially coplanar with the electrodes 21a-25a of the electronic components 21-25.
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The electronic package 1 may comprise recessed trenches at its bottom surface. The recessed trenches are directly under the electronic components. In
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The molding compound 30 covers the top surface TS and four sidewall surfaces SS, but does not covers the bottom surface BS of each of the electronic components 21-25. The recessed trench (only recessed trenches 21b, 23b can be seen in the sectional view) is situated at the bottom surface BS between the two electrodes of each of the electronic components 21-25.
According to the embodiment, the electrodes 21a-25a of the electronic components 21-25 in the electronic package 1 are directly used as pin out pads that may be directly connected to bond pads on a circuit board or a system board. The leadframe can be a piece of metal or in a form of a printed circuit board (PCB). In a case that the leadframe is made from a piece of metal, the production cost can be reduced. In a case that the leadframe is made from a piece of metal, the heat dissipating performance of the electronic package 1 can be improved. Further, no package substrate is required under the electronic components 21-25.
The electronic component of the electronic package of the present invention, such as inductor, which has a lower stressed level (fragile electronic component), is located at the leadframe opening and its corresponding electrode is not soldered to the leadframe. In other words, the solder on the electrode of the electronic component with lower stressed level at the leadframe opening is not sealed inside the molding compound 30. Therefore, the electronic package 1 of the present invention does not cause the element to be cracked and broken when it is heated and welded to the system board. In addition, the invention can reduce the overall height of the electronic package.
According to the embodiment, the leadframe 14 may be electrically connected to a ground plane of the system board or mother board and the metal shielding layer 40 is therefore grounded and is able to provide electromagnetic interference (EMI) shielding. The leadframe 14 can not only avoid interference of EMI under the electronic package, but also increase the structural strength of the electronic package, and is suitable for the miniaturization of the electronic package.
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Optionally, integrated circuit chips 70 may be mounted on the release film 12. According to the embodiment, the integrated circuit chips 70 may be flip chips and each may be mounted directly under the electronic component 22. For example, the electronic component 22 may be a choke and the integrated circuit chips 70 may be power control units (PCUs). The electronic component 22 caps the integrated circuit chip 70. The electronic component 22 may include a cavity 221 that accommodates each of the integrated circuit chips 70 under the electronic component 22.
According to one embodiment, each of the integrated circuit chips 70 has an active surface directly facing downward to the release film 12. According to one embodiment, each of the integrated circuit chips 70 has an inactive surface that is opposite to the active surface, and the inactive surface may be in direct contact with a bottom surface of the electronic component 22.
According to another embodiment, each of the integrated circuit chips 70 may be in contact with the bottom surface of the electronic component 22 through a thermal conductive material such as silver paste or the like. It is understood that an additional device, semiconductor chip or die having particular function may be mounted on the release film 12 between the electronic components 21-23. It is advantageous because the heat dissipating performance of the device can be improved.
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Subsequently, a plurality of via holes 510a is formed in the dielectric layer 510. The via holes 510a exposes the electrodes 21a-23a, respectively. According to the embodiment, the via holes 510a may be formed by using laser ablation, etching or any suitable methods known in the art. In a case that the integrated circuit chips 70 is incorporated, the input/output (I/O) pads on the active surface of each of the integrated circuit chips 70 may be exposed by the corresponding via holes 510a.
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The metal layer 520 may be formed by methods known in the art. For example, a barrier and a seed layer are deposited on the entire surface of the dielectric layer 510 and within the via openings 510a. A photoresist pattern having openings defining the metal layer 520 is formed on the seed layer. A plating process is then performed to form the metal layer 520 in the openings of the photoresist pattern. Thereafter, the photoresist pattern and the underlying portions of the barrier and the seed layer are removed.
After forming the metal layer 520, a solder mask 530 may be formed on the metal layer 520 and on the dielectric layer 510. The solder mask 530 may comprise a plurality of solder mask openings 530a that expose portions (pinout pads) of the metal layer 520. Solder bumps 60 are then formed within the solder mask openings 530a. According to the embodiment, the dielectric layer 510, the metal layer 520 including the ground trace 522, ground pads and pinout pads, and the plated vias 520a and the solder mask 530 constitute a RDL structure 50.
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As previously described, the prior art has several drawbacks. For example, during a reflow soldering process or a moisture sensitivity level (MSL) test, the solder between the electronic component and the package substrate may be melted and the volume of the solder may change, which may cause extra stress to the electronic component, resulting in solder extrusion, delamination of the packaging materials, broken of the electronic component, or bond damage.
In addition to the need to improve the structural strength of the miniaturized electronic package, how to incorporate the EMI protection at the bottom of the electronic package, to avoid interference by the EMI below the electronic package, is currently one of the problems to be solved. The present invention electronic package is capable of solving at least one of the above-described prior art problems.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
