Patent Application
20230230958
The present disclosure relates to electronic devices comprising transistors, for example constructed using micro-transfer printing.
Electronic circuits are widely used in communication, control, and sensing systems. In particular, transistors such as power transistors, are found in many electronic devices. Such transistors are typically larger than those typically found in logic circuits, have different frequency requirements, are typically used in analog circuits, can conduct relatively large currents compared to logic circuits, and can comprise compound semiconductor materials. Because such transistors can switch relatively large currents, they are provided with an extensive interface between the source and drain portions controlled by the gate of the transistor so as to reduce the current density of the transistor. A reduction in current density reduces local heating and damage to the transistor materials, thereby increasing device lifetime and functionality.
Large-current-transistor heating is often a limiting factor in the practical application of such devices and the heating is in part due to resistive heating in the transistor materials, including resistive heating in the gate, the source, and the drain of the transistor. The extensive interface between source and drain portions of a power transistor requires that electrical current physically travels along the interface, creating resistive heat. Moreover, because the source and drain materials are not perfectly conductive, current will be unevenly distributed over the source-drain interface, with a greater current density near the external connections of the power transistor, further exacerbating transistor heating and material breakdown.
U.S. Pat. No. 10,037,985 entitled Compound Micro-Transfer-Printed Power Transistor Device dated Jul. 31, 2018, and filed May 16, 2017, discloses a compound power transistor device comprising a power transistor made in one material (e.g., GaN) disposed on a control circuit made in a different material (e.g., silicon). The disclosure teaches an embodiment in which two power transistors are made in a common substrate or two power transistors are made in separate substrates. In
There is a need, therefore, for improved structures and methods of integration for large-current transistors and for reducing or managing the heat generated by large-current transistors.
Embodiments of the present disclosure, among other things, comprise a multi-component transistor structure comprising components electrically connected in parallel, each of the components comprising one or more component transistors each having one or more transistor elements each having a respective transistor element resistance. One or more component connections each have a respective connection resistance, and each is electrically connected to respective transistor elements of the components. The connection resistance is less than, less than an average of, or less than a sum of the transistor element resistances of the respective transistor elements of each of the components and at least one component is disposed on, directly on, or over another component in a component stack. The components are functionally similar and provide the same function, even if the components differ in size or performance. In some embodiments of the present disclosure, the components are disposed directly on and in contact with or over a support substrate. Adjacent ones of the components can be separated by a distance that is less than a width of each of the adjacent components.
The component stack can be an aligned stack of components with aligned component edges or an offset stack of components with at least one component with an unaligned component edge. An offset component stack can expose at least a portion of the transistor element of a component and the component connection can be disposed at least partly along and in electrical contact with the exposed portion of the transistor element. In some embodiments, the component connection is disposed at least partly through component vias in the components in the component stack. The component connection in the component via can have a cross section aspect ratio greater than one taken in a plane parallel to a surface of the support substrate forming a wall that can provide electromagnetic interference protection to the component transistors.
In some embodiments, the components are disposed in a component stack comprising a first lower row (layer) and a second upper row (layer) comprising the same number of components as the first lower row disposed on the first lower row. In some embodiments, the components are disposed in in an offset component stack comprising a first lower row and a second upper row disposed on the first lower row comprising fewer components than the first lower row. In some embodiments, at least some of the components in an offset component stack have different sizes and are disposed in a component stack with at least one relatively smaller component disposed on at least one relatively larger component or at least one larger component disposed on multiple smaller components. At least one edge of a component on which another component is disposed can be exposed and a component connection can be electrically connected on the exposed edge to a transistor element. The component connection can be electrically connected to a transistor element along the exposed edge.
In some embodiments, a multi-component transistor structure comprises a component substrate comprising a component material. The support substrate comprises a support material. One or more of the components is disposed on or in the component substrate, and the component material can be different from the support material. The component substrate can be disposed directly on and in contact with or over the support substrate.
In some embodiments, a heat conductor is disposed on the support substrate that extends beneath one or more of the components.
In some embodiments, the components are substantially identical, are substantially identical in size, or are substantially identical in materials.
In some embodiments, each component comprises a separate, discrete, distinct, different, and individual component substrate. Some embodiments comprise a common component substrate, and some components are formed in or disposed directly on and in contact with the common component substrate.
The components can comprise a compound semiconductor substrate. Each of the components can be a chiplet or bare die (e.g., an unpackaged die without bond wires), groups of the components can be each a chiplet or bare die, or all of the components comprise a chiplet or bare die. Bare dies can have a thickness no greater than fifty microns, no greater than twenty microns, no greater than ten microns, or no greater than five microns.
In some embodiments, one or more of the components comprises a connection post electrically connected to a transistor element.
At least one of the components can comprise one or more transistor elements that are linear or serpentine. In some embodiments, for at least one of the components, at least one of the multiple transistor elements is interdigitated with another different one of the multiple transistor elements, e.g., forming sub-transistors.
Each of the components can comprise a fractured component tether or the multi-component transistor structure can comprise a fractured component tether.
In some embodiments, the connection resistance(s) is less than the transistor element resistance(s) of one or more, an average of, or a sum of the respective corresponding transistor element(s). A length of each of the component connection(s) can be less than a length of the transistor element in a component or a sum of the lengths of the respective corresponding transistor elements in each of the components. Each of the component connection(s) can have a lower resolution than a resolution of the components. Each of the component connection(s) can be external to the components or pass through the components.
In some embodiments of the present disclosure, each of the components is a transistor, the one or more transistor elements of the component transistor comprise a source, a gate, and a drain, and the one or more component connections comprise (i) a component source connection electrically connected to the source of each of the component transistors, (ii) a component gate connection electrically connected to the gate of each of the component transistors, and (iii) a component drain connection electrically connected to the drain of each of the component transistors. The respective connection resistance of the component source connection can be less than a sum of the respective transistor element resistances of the source of each of the component transistors, the respective connection resistance of the component gate connection can be less than a sum of each of the respective transistor element resistances of the gate of each of the component transistors, and the respective connection resistance of the component drain connection can be less than a sum of the respective transistor element resistances of the drain of each of the component transistors.
In some embodiments, (i) the component gate connection has a greater conductivity than a conductivity of the gate or gate electrode of any of the component transistors, (ii) the component source connection has a greater conductivity than a conductivity of the source or source electrode of any of the component transistors, or (iii) the component drain connection has a greater conductivity than a conductivity of the drain or drain electrode of any of the individual component transistors, or (iv) any combination of (i)-(iii).
According to some embodiments, at least two of the components in the multi-component transistor structure are mutually non-native. In some embodiments all of the components are mutually non-native. For example, the components can be printed to a destination substrate and/or onto each other.
In some embodiments, a multi-component transistor structure comprises a silicon support substrate comprising an electronic circuit that is electrically connected to any one or more of the component gate connection, the component source connection, and the component drain connection. The component transistors can be disposed directly on and in contact with or over the support substrate. In some embodiments, the component gate connection, the component source connection, and the component drain connection are respectively a first component gate connection, a first component source connection, and a first component drain connection and the multi-component transistor structure comprises a second component gate connection, a second component source connection, and a second component drain connection electrically connected to the gate, source, and drain, respectively. A material, material width, or material thickness of the component connection can be different from a material, material width, or material thickness of the respective transistor elements.
In some embodiments, a multi-component transistor structure comprises components electrically connected in parallel, each of the components comprising at least a transistor element having a length and a component connection electrically connected to the transistor element of each of the components. A length of the component connection is less than a sum of the lengths of the transistor elements of each of the components and at least one component is disposed on another component, for example in an offset component stack.
In some embodiments, a multi-component transistor structure comprises components electrically connected in parallel, each of the components comprising at least a transistor element having a transistor element resistance and a component connection electrically connected to the transistor element of each of the components and having a connection resistance. Each one of the multiple transistor elements in the components can be electrically connected in parallel with a different and separate component connection each having a connection resistance. The connection resistance is less than at least one of the transistor element resistances.
At least one component can be disposed on another component, for example in an offset or an aligned component stack. An integral of a connection resistance function taken over a length of the component connection is less than an integral of a transistor element resistance function taken over a sum of the lengths of the transistor elements, where the connection resistance function is f(x)=CRX where CR=(the connection resistance divided by a length of the component connection), and the transistor element resistance function is f(x)=ERX where ER=(the transistor element resistance divided by a length of the transistor element).
In some embodiments, a multi-component transistor structure comprises a plurality of component transistors electrically connected in parallel, each component transistor comprising at least a gate having a gate resistance, a source having a source resistance, and a drain having a drain resistance. Each component transistor comprises a die comprising a separate and individual substrate, a component gate connection electrically connected to the gates of each of the component transistors, a component source connection electrically connected to the source of each of the component transistors, and a component drain connection electrically connected to the drain of each of the component transistors. At least one component is disposed on another component, for example in an offset or aligned component stack. In embodiments,
According to some embodiments of the present disclosure, any one or combination of a material, material width, or material thickness of the component source connection is different from a material, material width, or material thickness of the source, a material, material width, or material thickness of the component gate connection is different from a material, material width, or material thickness of the gate, and a material, material width, or material thickness of the component drain connection is different from a material, material width, or material thickness of the drain.
Component transistors of the present disclosure can be power transistors, for example power field effect transistors (FETs) or radio frequency (RF) transistors and can be made in a compound semiconductor material, for example a III/V compound semiconductor such as GaAs, GaN, or InP or a II/VI compound semiconductor.
In some embodiments, one or more electrically conductive connection posts protrude from a side of the transistor substrate and are electrically connected to the component transistor. One or more electrical contact pads can be disposed on a support substrate and each transistor connection post can be electrically connected to a contact pad. Likewise, an electronic circuit can be formed in or on the support substrate and the one or more electrically conductive connection posts can be electrically connected to the electronic circuit through the contact pads. The electronic circuit disposed in the support substrate can be, for example and not limited to, an integrated circuit, an active electronic circuit, a control circuit, or a CMOS electronic circuit. In some embodiments, the support substrate comprises silicon and the transistor substrate comprises a different transistor material, for example a compound semiconductor, a III-V semiconductor, or a GaAs semiconductor.
According to some embodiments of the present disclosure, a semiconductor structure comprises a semiconductor substrate (e.g., a component substrate) having a first side and a second side, the second side on an opposite side of the semiconductor substrate from the first side, and a high-aspect-ratio via (e.g., a component via) formed in the semiconductor substrate that extends from the first side to the second side through the semiconductor substrate. The high-aspect-ratio via can have a high aspect ratio in a cross section of the high-aspect-ratio via parallel to the first side. The high-aspect-ratio via can comprise a dielectric surrounding a via conductor that can be a component connection. Some embodiments comprise a circuit (e.g., a component transistor) formed in or on the first side of the semiconductor substrate and the via conductor can be electrically connected to the circuit. The high-aspect-ratio via can extend at least along a side of the circuit, for example no less than halfway along a side of the circuit, no less than halfway along two sides of the circuit, no less than halfway along three sides of the circuit, or no less than halfway along four sides of the circuit. In some embodiments, the high-aspect ratio via can extend three quarters or all of the way along a side of the circuit. Some embodiments comprise a plurality of separate high-aspect-ratio vias in one semiconductor substrate that can be disposed along one or more sides of the circuit, that are not in contact with each other, and can extend completely along each side of the circuit. Some embodiments comprise a plurality of separate semiconductor substrates disposed in a component stack, each of the semiconductor substrates comprising a via conductor, and the via conductors of the separate semiconductor substrates are electrically connected. The via conductors can be vertically aligned in a direction orthogonal to the first side. The via conductors can extend between at least two semiconductor substrates beyond the high-aspect-ratio via.
According to embodiments of the present disclosure, an embedded component stack includes or comprises a first conductive layer, a first dielectric layer disposed on the first conductive layer, a second conductive layer disposed on the first dielectric layer, a first component embedded entirely within the first dielectric layer and entirely between the first conductive layer and the second conductive layer, a second dielectric layer disposed on the second conductive layer, and a second component disposed on or embedded entirely within the second dielectric layer. A conductive layer can be a metal layer. The first conductive layer can be a first metal layer. The second conductive layer can be a second metal layer.
Each of the first component and the second component can be a self-supporting structure comprising a component substrate that is independent, distinct, individual, and separate of any other component or substrate, for example a support substrate on which the embedded component stack can be disposed. Each of the first component and the second component can be or comprise an integrated circuit that is an unpackaged bare die. Each of the first component and the second component can be a micro-transfer-printed component and can comprise a fractured or separated component tether. A component can be a micro-component and a component stack can be a micro-component stack. According to some embodiments, each of the first component and the second component has (i) a length, a width, or both a length and a width of no greater than 200 microns (e.g., no greater than 100 microns, 50 microns, or 20 microns) and (ii) a thickness no greater than 50 microns (e.g., no greater than 20 microns, 10 microns, 5 microns, or 2 microns).
According to some embodiments, the first component and the second component are functionally similar, are structurally similar, or are substantially identical. Electrical component connections to the components can be made to a same side of the components. The first component can be rotated with respect to the second component so that the component connections of the rotated components are likewise rotated with respect to each other and can be disposed in different locations and extend in different directions over the conductive layers. The rotation can be 45, 90, 135, 180, 225, 270, or 315 degrees.
Some embodiments of the present disclosure comprise a support substrate and the first conductive layer is disposed on or over the support substrate or on or over a layer disposed on the support substrate.
According to some embodiments, no portion of the second component is directly above or directly below the first component in the stack. The first component can be spatially offset in a horizontal direction (e.g., parallel to the extent of a surface of the support substrate or conductive layer over which the first component is disposed) with respect to the second component. According to some embodiments, no portion of the second component is directly above or directly below the first component.
In some embodiments, the embedded component stack comprises a third conductive layer disposed on the second dielectric layer and the second component is embedded entirely within the second dielectric layer and entirely between the second conductive layer and the third conductive layer. The third conductive layer can be a third metal layer. Some embodiments comprise a third dielectric layer disposed on the third conductive layer and a third component disposed on or embedded entirely within the third dielectric layer.
According to some embodiments of the present disclosure, the first component is electrically connected to the first conductive layer, the first component is electrically connected to the second conductive layer, or the first component is electrically connected to the first conductive layer and the second conductive layer.
According to some embodiments of the present disclosure, the first conductive layer is patterned, the second conductive layer is patterned, or both the first conductive layer and the second conductive layer are patterned. The patterned first layer can be a single electrically conductive conductor and the patterned second layer can be a single electrically conductive conductor. The patterned first or second conductive layers can be electrically connected to a component connection. In some embodiments, either or both of the first and second patterned conductive layers can form multiple electrically separate conductors. The electrically separate conductors can be electrically connected to different transistor electrodes.
In some embodiments, an electrically conductive via is disposed in and passes through the first dielectric layer. The component can be electrically connected to the via, the first conductive layer can be electrically connected to the via, or the second conductive layer can be electrically connected to the via. An electrically conductive via can be disposed in and pass through the first component or the second component, or both the first component and the second component. The electrically conductive via can be electrically connected to the first conductive layer, the second conductive layer, or both the first conductive layer and the second conductive layer.
The embedded component stack can be an offset stack or an aligned stack. The offset stack can comprise components in different layers that are only partially directly above or below each other or are not at least partially directly above or below each other.
According to some embodiments of the present disclosure, multiple first components are disposed in the first dielectric layer, multiple second components are disposed in the second dielectric layer, or both.
According to some embodiments of the present disclosure, a multi-component system comprises components (e.g., micro-components) disposed in a stack and a conductive layer (e.g., a metal layer) disposed between adjacent components in the stack. The conductive layer can be electrically connected to one or more of the components. Each component can be or comprise an integrated circuit that is an unpackaged bare die. At least one of the components can be a micro-transfer printed component that comprises a fractured or separated component tether. The components can be functionally similar, can be substantially similar or identical, or can be functionally similar but have different sizes or shapes.
According to some embodiments, at least one of the components is rotated with respect to a different component in the stack or a component above or below it in the stack. At least a portion of each component in the stack can be disposed over, on, or beneath another component, for example either directly or offset. At least a portion of each conductive layer in the stack can be disposed over, on, or beneath a component.
The components in the stack can be embedded in a dielectric layer disposed between the conductive layers. In some embodiments, the stack is an offset stack or an aligned stack.
In some embodiments, at least one of the components comprises a component via through which a conductive layer above the component and a conductive layer below the component are electrically connected or a component is electrically connected to a conductive layer or another component.
The present disclosure provides advantages over transistor assemblies of the prior art, in particular for power transistors or those components whose performance can be limited by resistive heating. According to embodiments of the present disclosure, a plurality of smaller high-performance components (such as transistors) is connected in parallel to reduce resistive heating, spatially distribute unwanted heat generation, and improve electrical operating efficiency. Such a disaggregation of a single large component into multiple smaller components electrically connected in parallel reduces resistive losses, thereby distributing electrical current more evenly and reducing maximum current density. Furthermore, by micro-transfer printing the component transistors, made in a semiconductor material optimized for transistors such as a compound semiconductor, onto a substrate of different semiconductor material, for example a silicon semiconductor optimized for control logic or integrated circuits, an integrated structure with materials chosen to optimize different tasks is provided. Embodiments of the present disclosure therefore enable an improved transistor structure. By micro-transfer printing multiple component transistors onto a substrate having logic or control circuits, manufacturing cycle time and costs are reduced, and higher performance enabled in a more highly integrated device with a smaller size.
The foregoing and other objects, aspects, features, and advantages of the present disclosure will become more apparent and better understood by referring to the following description taken in conjunction with the accompanying drawings, in which:
Features and advantages of the present disclosure will become more apparent from the detailed description set forth below when taken in conjunction with the drawings, in which like reference characters identify corresponding elements throughout. In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The figures are not drawn to scale since the variation in size of various elements in the Figures is too great to permit depiction to scale.
Embodiments of the present disclosure provide, among other things, a disaggregated multi-component transistor structure comprising one or more stacks of components electrically connected in parallel with component connections. Stacks of parallel-connected components can have a performance superior to a single larger component providing the same function and having the same structure and size. In some embodiments, the components are integrated circuits comprising transistors. In some embodiments, the components are micro-assemblies comprising a component substrate, bare die (e.g., unpackaged integrated circuits comprising one or more transistors), and electrical connections. Each transistor can comprise a gate controlling current flow through an interface (shown as a gate in the figures) between a source and drain. The interfaces of all of the transistors, taken together, can have an aggregated area or length equivalent to an interface area or length of a single, larger transistor, thus providing the same function and having substantially the same total structure and size. The disaggregated multiple components and component connections can have reduced resistive heating and improved conductivity and therefore can be more efficient and can operate at higher power levels and switching speeds than the single, larger transistor. The multiple components can each be a power transistor. To enable shorter component connections and reduced resistance in the parallel electrical connection connecting the components, the components can be provided in a stacked configuration of bare die with at least one component disposed on another component in a component stack, for example disposed on a support substrate.
According to embodiments of the present disclosure and as shown in
In some embodiments, the connection resistance is less than a sum of the transistor element resistances of components 20. In some embodiments, the connection resistance is less than an average of the transistor element resistances of components 20. In some embodiments, the connection resistance is less than at least one of the transistor element resistances (e.g., all of the transistor element resistances) of components 20. In some embodiments, a resistivity (e.g., resistance per length or ohms per square) of connection resistance is less than a resistivity of the transistor element resistances of components 20. In some embodiments, a length of component connection 30 (component connection length LC as shown in
In some embodiments and as shown in
Each component 20 can have a separate, discrete, and individual component substrate 56, for example micro-transfer printed from a component source wafer onto support substrate 10 or onto other components 20 or layers (e.g., encapsulation or planarization layers 70 such as dielectric structures 58) disposed on and insulating components 20 from electrical conductors such as component connections 30 or stacked component substrates 56. As a consequence of micro-transfer printing, each component 20 can comprise a fractured component tether 52. Each component 20 can be a singular, separate, distinct, and different unpackaged die 98. The dies 98 can have a small thickness, for example from 2 to 20 microns, thereby enabling a dense configuration, efficient components 20 stacking, and short, low-resistance component connections 30 between components 20 in component stack 28. Component transistor 21 can be a power transistor.
As shown in
Components 20 in component stack 28 can be spatially offset with respect to one component edge, two component edges, three component edges, or four component edges (e.g., as shown in
In some embodiments, as shown in
According to some embodiments, and as shown in
In some embodiments, as shown in
Component vias 54 can have a cross section aspect ratio taken in a plane parallel to a surface of support substrate 10 that is 1:1 (length to width). In some embodiments, and as shown in
Thus, according to some embodiments of the present disclosure, a semiconductor structure comprises a semiconductor substrate (e.g., component substrate 56) having a first side and a second side, the second side on an opposite side of the semiconductor substrate from the first side, and a high-aspect-ratio via (e.g., component via 54) formed in the semiconductor substrate that extends from the first side to the second side through the semiconductor substrate. The high-aspect-ratio via can have a high aspect ratio in a cross section of the high-aspect-ratio via parallel to the first side. The high-aspect-ratio via can comprise a dielectric surrounding a via conductor that can be a component connection 30. Some embodiments comprise a circuit (e.g., component transistor 21) formed in or on the first side of the semiconductor substrate and the via conductor can be electrically connected to the circuit. The high-aspect-ratio via can extend at least along a side of the circuit, for example no less than one half, one quarter, one eighth, or one sixteenth of the way along a side of the circuit, no less than one half, one quarter, one eighth, or one sixteenth of the way along two sides of the circuit, no less than one half, one quarter, one eighth, or one sixteenth of the way along three sides of the circuit, or no less than one half, one quarter, one eighth, or one sixteenth of the way along four sides of the circuit. In some embodiments, the high-aspect ratio via can extend three quarters or all of the way along a side of the circuit. Some embodiments comprise a plurality of separate high-aspect-ratio vias in one semiconductor substrate that can be disposed along one or more sides of the circuit, that are not in contact with each other, and can extend completely along each side of the circuit. Some embodiments comprise a plurality of separate semiconductor substrates disposed in a component stack 28, each of the semiconductor substrates comprising a via conductor, and the via conductors of the separate semiconductor substrates are electrically connected. The via conductors can be vertically aligned in a direction orthogonal to the first side. The via conductors can extend between at least two semiconductor substrates beyond the high-aspect-ratio via and can provide additional shielding.
Each component 20 can comprise a transistor element 40 having a transistor element resistance, for example, but not necessarily, an ohmic resistance to the conduction of electrical current. Transistor element 40 can be a conductor, for example a wire or conductive area, for example comprising patterned metal, metal particles, or conductive polymers or conductive oxides, such as transparent conductive oxides, including ITO. Transistor element 40 can be a semiconductor, for example a doped semiconductor, such as a p-doped semiconductor or an n-doped semiconductor. Transistor element 40 can be a semiconductor in combination with a conductor disposed in electrical contact with the semiconductor. Transistor element 40 has a transistor element resistance, that is an electrical resistance to a flow of current (e.g., electrons or holes) along the extent of transistor element 40.
Components 20 can comprise a bulk layer of a semiconductor (for example a compound semiconductor such as GaAs, GaN, InP or various binary, trinary, or quaternary compound semiconductors) comprising component substrate 56 and a doped or implanted portion of the bulk layer forming component transistor 21 and transistor elements 40. (For clarity, in the Figures the bulk semiconductor comprising component substrate 56 is shown as thinner or smaller than transistor elements 40, but in practice can be much thicker or larger than transistor elements 40.) Transistor electrodes 41 can be metal or semiconductor materials (e.g., doped semiconductor materials) or combinations thereof in transistor element 40 for conducting electrical current to source, gate, or drain 22, 24, 26. Gate 24 can be a gate electrode 44 (e.g., a transistor electrode 41). Components 20, component transistors 21, transistor elements 40, transistor electrodes 41, and component connection 30 can be constructed using photolithographic methods and materials.
In some embodiments, a thickness or width of component connection 30 is greater than a thickness or width of transistor elements 40 or transistor electrodes 41 of component transistor 21 of components 20. Component connection 30 can comprise different materials than transistor elements 40 or transistor electrodes 41 of component transistor 21 of components 20. In some embodiments, component connection 30 has a lower resolution than a resolution of transistor element 40 and can be made in a different process or with different process limitations, for example transistor element 40 can have a finer resolution with smaller features or feature separation than component connection 30.
Component connections 30 are electrically connected to respective transistor elements 40 of each component 20 in parallel. Thus, if component 20 comprises first, second, and third transistor elements 40 (e.g., source, gate, and drain 22, 24, 26), a first component connection 30 is electrically connected in parallel to first transistor element 40 of all of components 20 in multi-component transistor structure 99 so that first component connection 30 is electrically connected in parallel to every first transistor element 40 in multi-component transistor structure 99, a second component connection 30 is electrically connected in parallel to second transistor element 40 of all of components 20 in multi-component transistor structure 99 so that second component connection 30 is electrically connected in parallel to every second transistor element 40 in multi-component transistor structure 99, and a third component connection 30 is electrically connected in parallel to third transistor element 40 of all of components 20 in multi-component transistor structure 99 so that third component connection 30 is electrically connected in parallel to every third transistor element 40 in multi-component transistor structure 99. First, second, and third component connections 30 are separate and distinct electrical conductors.
In some embodiments, a respective connection resistance of each component connection 30 (e.g., the resistance of component connection 30) is less than the corresponding transistor element resistance of at least one component transistor 21, less than an average of the corresponding transistor element resistances of component transistor 21 of components 20, or less than a sum of the corresponding transistor element resistances of component transistor 21 of each of components 20. A resistivity of the component connection 30 can be less than a resistivity of the transistor element 40 of components 20. Resistivity can be a resistance per length or ohms per square of connection resistance and transistor element resistance. Thus, using the example above, the connection resistance of first component connection 30 can be less than, less than an average of, or less than a sum of the transistor element resistances of first transistor elements 40 of all of components 20 connected by first component connection 30, the connection resistance of second component connection 30 can be less than, less than an average of, or less than of a sum of the transistor element resistances of second transistor elements 40 of all of the components 20 connected by second component connection 30, and the connection resistance of third component connection 30 can be less than, less than an average of, or less than a sum of the transistor element resistances of third transistor elements 40 of all of the components 20 connected by third component connection 30.
A material, material thickness, or material width of component connection 30 can be different from a material or material thickness of transistor element 40. In some embodiments, the material of component connection 30 is more conductive (e.g., has a greater conductivity) than a material of respective transistor element 40 to which component connection 30 is electrically connected. In some embodiments, a material thickness of component connection 30 is greater than a material thickness of transistor element 40 to which component connection 30 is electrically connected. In some embodiments, a material width of component connection 30 is greater than a material width of transistor element 40 to which component connection 30 is electrically connected. Thus, in some embodiments, component connections 30 are more conductive than transistor elements 40, e.g., have a lower resistivity per length or ohms per square.
Component connection 30 has a connection resistance, for example but not necessarily, an ohmic resistance that is an electrical resistance to a flow of current (e.g., electrons or holes). Component connection 30 includes only those portions of a conductor that electrically connect transistor elements 40 of components 20 in common (e.g., see conductor 80 in
In some embodiments of the present disclosure, a length of component connection 30 is less than a length of the transistor element 40 in a component 20, is less than an average of the lengths of the respective corresponding transistor elements 40 in the components 20, or is less than a sum of the lengths of the respective corresponding transistor elements 40 in the components 20, e.g., the corresponding transistor elements 40 in the components 20 to which the component connection 30 is connected.
As shown in
A multi-component structure 99 can comprise a plurality of component 20 groups sharing a common component substrate 57 and interconnected with component connections 30 (e.g., as shown in
According to some embodiments of the present disclosure, a connection resistance of component connection 30 is less than, less than the average of, or less than the sum of the transistor element resistances of the same transistor elements 40 of components 20 (e.g., taken from connection points R1 to R2 in
According to some embodiments of the present disclosure, component connection 30 comprises a different material or has a different material thickness than transistor element 40. For example, transistor element 40 can be or include a doped semiconductor or an aluminum conductor. As an example, component connection 30 can be copper. For example, transistor element 40 can have a thickness less than two microns and component connection 30 can have a thickness greater than two microns.
As shown in
Comparing the electrical current flow and resistance of
Since component connection 30 can be constructed externally to component 20 or transistor element 40, it can be made, in various embodiments, with more conductive materials, wider materials, or thicker materials, or have a shorter length, as illustrated, all of which provide reduced resistance, reduced heating, improved switching rates, and reduced parasitics (e.g., resistive, capacitive or inductive parasitics) in multi-component transistor structure 99. Component connection 30 can also be constructed at a lower resolution than component 20, saving manufacturing costs. A device resolution is the smallest dimension parallel to a substrate surface (e.g., x and y dimensions but not z dimension) of the device or the smallest separation between devices, whichever is smaller. The resolution of component 20 is the resolution of a transistor element 40 in component 20. Component connection 30 can also be constructed separately from component 20, in a different process, with different materials, at a separate time, and disposed externally to component 20.
For ease of understanding, the examples of
The multi-component transistor structure 99 of
Following this illustrative example, the performance of multi-component transistor structure 99 can be modeled as:
Multi-component resistance M=(N×E)+C; and
For the example above, LT=4, N=4, LC=LE=1, R=2, so that:
P=(½(2)2)/((4×½×2)+½(1)2=16/(4+½)=16/4.5=3.56.
In general, the performance factor P is improved by increasing N (the number of components 20 and thereby decreasing the length LE of each transistor element 40 in components 20), by decreasing LC (the length of component connection 30 length), and by decreasing R (the resistance of component connection 30). However, as N is increased, it is likely that LC will also increase, so that an actual performance factor P will be a matter of design choice. It is helpful to pack components 20 as closely together as is possible to meet design goals since a dense arrangement of components 20 can also reduce LC, for example by reducing component separation distance S with respect to component width W. R can be reduced by improving the conductivity of component connection 30, for example by using thick and conductive materials such as copper or gold. In embodiments in which component 20 comprises multiple transistor elements 40, a performance factor P can be obtained for each transistor element 40 in component 20, further improving the overall performance of multi-component transistor structure 99.
Thus, according to some embodiments of the present disclosure, a multi-component transistor structure 99 comprises stacked components 20 having component transistors 21 electrically connected in parallel, each of component transistors 21 comprising at least a transistor element 40 having a transistor element resistance, and a component connection 30 electrically connected to transistor element 40 of each component 20. A material, material width, or material thickness of component connection 30 can be different from a material, material width, or material thickness of transistor element 40. Component connection 30 has a connection resistance and transistor element 40 has a transistor element resistance. An integral of a connection resistance function taken over a length of component connection 30 is less than an integral of a transistor element resistance function taken over a sum of the lengths of transistor elements 40, the connection resistance function is f(x)=CRX where CR=(the connection resistance divided by a length of component connection 30), and the transistor element resistance function is f(x)=ERX where ER=(the transistor element resistance divided by a transistor length LT).
In some embodiments, components 20 can be disposed closely together, for example separated by a separation distance S that is less than a width W of components 20 (as shown in
The length of component connection 30 can be less than transistor length LT times the number of components 20. Thus, in some embodiments of a multi-component transistor structure 99, a length of component connection 30 is less than a sum of the lengths of transistor elements 40 of components 20, is less than an average of the lengths of transistor elements 40 of components 20, is less than the longest length of any transistor element 40 of components 20, or is less than the shortest length of any transistor element 40 of components 20. A shorter component connection 30 has reduced resistive and parasitic losses in multi-component transistor structure 99 providing improved efficiency.
Groups of multi-component transistor structures 99 can be provided and electrically connected together. In some embodiments, the group itself is a multi-component transistor structure 99, for example where a group component connection 30 comprises a combination of each of component connections 30 of each multi-component transistor structure 99 together and the connection resistance is the resistance of the group component connection 30 and the sum of the transistor element resistances is the sum of all of transistor elements 40 of components 20 in each of the multi-component transistor structures 99. In other embodiments, the group of multi-component transistor structures 99 is not itself a multi-component transistor structure 99.
As discussed above, each of components 20 can include one or more component transistors 21, for example field-effect transistors (FETs), power transistors, or radio frequency (RF) transistors, or any one or combination thereof, and can be applied, for example, in power amplifiers in mobile devices or in automotive applications. Component transistors 21 can have multiple transistor elements 40, e.g., a source 22, gate 24, and drain 26, each with an electrically separate component connection 30, e.g., a component source connection 32 electrically connected to source 22 of components 20, a component gate connection 34 electrically connected to gate 24 of components 20, and a component drain connection 36 electrically connected to drain 26 of components 20. In some embodiments, component gate connection 34 is more conductive than a conductivity of gate 24 of any of component transistors 21, component source connection 32 is more conductive than a conductivity of source 22 of any of component transistors 21, or component drain connection 36 is more conductive than a conductivity of drain 26 of any of component transistors 21, or any combination thereof. In some embodiments, component gate connection 34 is shorter than a gate 24 length of any of component transistors 21, component source connection 32 is shorter than a source 22 length of any of component transistors 21, or component drain connection 36 is shorter than a drain 26 length of any of component transistors 21, or any combination thereof. In some embodiments, component gate connection 34 is shorter than a sum of gate 24 lengths of component transistors 21, component source connection 32 is shorter than a sum of source 22 lengths of component transistors 21, or component drain connection 36 is shorter than a sum of drain 26 length of component transistors 21, or any combination thereof.
In some embodiments, source 22 of each component transistor 21 comprises a source material and component source connection 32 comprises an electrical conductor material that is different from the source material, drain 26 of each component transistor 21 comprises a drain material and component drain connection 36 comprises an electrical conductor material that is different from the drain material, or both. In some embodiments, component source, gate, and drain connections 32, 34, 36 are first component source, gate, and drain connections 32, 34, 36 and components 20 comprise second component source, gate, and drain connections 32, 34, 36, for example as shown in
Thus, according to embodiments of the present disclosure, a multi-transistor structure 99 comprises a plurality of stacked component transistors 21 electrically connected in parallel, each component transistor 21 comprising at least a gate 24 having a gate resistance, a source 22 having a source resistance, and a drain 26 having a drain resistance. A component gate connection 34 is electrically connected to gates 24 of each component transistor 21 at two or more locations, a component source connection 32 is electrically connected to source 22 of each component transistor 21 at two or more locations, and a component drain connection 36 is electrically connected to drain 26 of each component transistor 21 at two or more locations. Any one or combination of a material, material width, or material thickness of component source connection 32 can be different from a material, material width, or material thickness of source 22 or source electrode 42, a material, material width, or material thickness of component gate connection 34 can be different from a material or material thickness of gate electrode 44, and a material, material width, or material thickness of component drain connection 36 can be different from a material or material thickness of drain 26 or drain electrode 46.
In some embodiments, the resistance of component source connection 32 is less than, less than the average of, or less than the sum of the source resistances of the component transistors 21, the resistance of the component drain connection 36 is less than, less than the average of, or less than the sum of the drain resistances of component transistors 21, the resistance of component gate connection 34 is less than, less than the average of, or less than the sum of the gate resistances of component transistors 21, or any combination thereof. In some embodiments, an integral of the connection resistance of component source connection 32, taken over the length of component source connection 32 is less than an integral of the source resistance taken over a length of source 22, an integral of the connection resistance of component gate connection 34 taken over the length of component gate connection 34 is less than an integral of the gate resistance taken over a length of gate 24, or an integral of the connection resistance of component drain connection 36 taken over the length of component drain connection 36 is less than an integral of the drain resistance taken over a length of drain 26, or any combination thereof. For example, an integral of a source connection resistance function taken over a length of component source connection 32 can be less than an integral of a source resistance function taken over a sum of the lengths of sources 22; the source connection resistance function can be f(x)=CRX where CR=(a resistance of component source connection 32 divided by a length of component source connection 32), and the source resistance function is f(x)=ERX where ER=(source resistance divided by a length of source 22). An integral of a gate connection resistance function taken over a length of component gate connection 34 can be less than an integral of a gate resistance function taken over a sum of the lengths of gates 24; the gate connection resistance function can be f(x)=CRX where CR=(a resistance of component gate connection 34 divided by a length of component gate connection 34), and the gate resistance function is f(x)=ERX where ER=(gate resistance divided by a length of gate 24). An integral of a drain connection resistance function taken over a length of component drain connection 36 can be less than an integral of a drain resistance function taken over a sum of the lengths of drains 26; the drain connection resistance function can be f(x)=CRX where CR=(a resistance of component drain connection 36 divided by a length of component drain connection 36), and the drain resistance function is f(x)=ERX where ER=(drain resistance divided by a length of drain 26).
As illustrated in
As illustrated in
Components 20 can each be individually disposed on support substrate 10 by micro-transfer printing, for example as individual die 98 or units. In some embodiments, multiple components 20 are disposed on support substrate 10 as a single die 98 and transfer printed as a single die 98 to form each row (or a portion of a row) within a stacked structure on support substrate 10. Where a multi-component transistor structure 99 comprises stacked components 20 or rows of components 20, either components 20 comprising individual dies 98 or multiple components 20 comprising a single die 98 can be micro-transfer printed on top of pre-disposed components 20 to form component stack 28 (or a portion thereof).
As shown in
As is also shown in
Although component substrates 56 can have a common origin and materials (e.g., component source wafer 60), when transferred to support substrate 10 (e.g., by micro-transfer printing from component source wafer 60 and forming fractured or separated component tethers 52), component substrates 56 are completely separated, discrete, distinct, and individual and are separated on support substrate 10 by separation distance S (shown in
Components 20 can be made in or comprise a substrate such as a semiconductor substrate or compound semiconductor substrate, for example a III/V compound semiconductor such as GaN or GaAs or a II/VI compound semiconductor. Thus, each of components 20 can comprise a component substrate 56 comprising a component material (e.g., GaN or GaAs) that is different from a support substrate 10 material (e.g., silicon or glass). Components 20 can be substantially identical in function, size, and shape, or have different sizes or shapes. By substantially identical is meant designed to be and operate the same within the constraints of a manufacturing process. Components 20 can be chiplets or micro-chiplets and can comprise bare die 98 that are not provided in a package with additional electrical connections to transistor elements 40 in components 20 (e.g., bond wires connected to pins). Such bare die 98 components 20 reduce costs and improve performance, as well as component density. Bare die 98 can be processed on support substrate 10, for example using photolithographic materials and methods, to provide, for example insulating dielectric structures 58, conductors such as component connections 30, or other useful circuit structures.
In some embodiments and as shown in
As shown in
As shown in the detail of
As shown in
In some methods of the present disclosure illustrated in
In some embodiments, and as shown in
In some embodiments, component connections 30 are constructed at a different (e.g., lower) resolution from structures in components 20 or transistor elements 40, for example using different process methods or materials, or both, (e.g., at a lower cost). In optional step 130, multi-component transistor structure 99 can be removed from the common semiconductor wafer, for example by dicing, or by micro-transfer printing into an external structure, such as a desired product or system, thereby forming fractured component tethers 52 for support substrate 10. In such multi-component transistor structures 99, component substrate 56 can comprise at least a portion of and common materials with component source wafer 60 and can support one component (e.g., as shown in
For a discussion of micro-transfer printing techniques see U.S. Pat. Nos. 8,722,458, 7,622,367 and 8,506,867, each of which is hereby incorporated by reference in their entirety. Micro-transfer printing using compound micro-assembly structures and methods can also be used with the present disclosure, for example as described in U.S. patent application Ser. No. 14/822,868, filed Aug. 10, 2015, entitled Compound Micro Assembly Strategies and Devices, which is hereby incorporated by reference in its entirety. U.S. Pat. 9,520,537, filed Jun. 18, 2015, entitled Micro Assembled LED Displays and Lighting Elements, incorporated herein by reference describes micro-transfer printing structures and processes useful with the present disclosure.
Thus, according to some embodiments of the present disclosure, a multi-component transistor structure 99 comprises components 20 electrically connected in parallel. Each component 20 comprises one or more transistor elements 40. Each transistor element 40 has a respective transistor element resistance. One or more component connections 30 each have a respective connection resistance, and each electrically connects to respective transistor elements 40 of components 20. The connection resistance is less than, less than an average of, or less than a sum of the transistor element resistances of the respective transistor elements 40 of each component 20. At least one component 20 is disposed on another component 20, for example in an aligned component stack 28 or an offset component stack 28. In some embodiments, all of components 20 are the same size. In some embodiments, components 20 in component stack 28 are successively smaller and the largest component 20 is disposed on support substrate 10 forming an offset component stack 28. In some embodiments, components 20 have a length and a width smaller than a length and electrical connections to transistor elements 40 that experience the greatest current (e.g., source 22 or drain 26) are disposed along an edge of component 20 in the length direction. Successive components 20 can be smaller in length, smaller in width, or smaller in both length and width. Relatively smaller components 20 can be disposed entirely over relatively larger components 20 so that no portion of the smaller component 20 extends beyond the larger component 20 or extends over an edge of the larger component 20. Components 20 can be, but are not necessarily, rectangular and can have other shapes, for example any polygon, and including curved shapes. Thus, one, two, three, four, or more edges of the larger components 20 in component stack 28 can be exposed.
In some embodiments, electrical connections to one or more transistor elements 40 are disposed on an exposed edge of a component 20. The electrical connection can be a component connection 30 that electrically connects transistor elements 40 in components 20 in a component stack 28 such as an offset component stack 28, for example as shown in
According to some embodiments of the present disclosure and as illustrated in
First, second, and third dielectric layers 59A, 59B, 59C are generically referred to as dielectric layers 59. First, second, and third conductive layers 82A, 82B, 82C are collectively conductive layers 82. First, second, and third conductive layers 82A, 82B, 82C can be first, second, and third metal layers 82A, 82B, 82C referred to collectively as metal layers 82. First, second, and third components 20A, 20B, 20C are components 20 and are described herein collectively as components 20 to emphasize that first, second, and third components 20A, 20B, 20C are small (for example no greater than 200 microns, 100 microns, 50 microns, or 20 microns in length or width and no greater than 50, 20, 10, 5, or 2 microns in thickness) and can be unpackaged bare die micro-transfer printed integrated circuits assembled into component stack 28 that each comprise a broken (e.g., fractured or separated) component tether 52. Metal layers 82 provide improved current dissipation with reduced resistance as well as improved thermal dissipation.
Components 20 can be self-supporting structures and can comprise an electrically insulating component substrate 56 (e.g., an oxide or a nitride separate, discrete, and independent from support substrate 10) on which component transistors 21 are disposed that insulates transistor elements 40 from metal layers 82, as shown in
In some embodiments and as illustrated in
Components 20 (e.g., first, second, and third components 20A, 20B, 20C) can be functionally similar and perform the same function, can be substantially identical, can be structurally similar, or can be substantially similar but have different sizes. Substantially can mean within manufacturing or design tolerances or limits.
According to some embodiments of the present disclosure, components 20 in adjacent separate levels or rows of component stack 28 are rotated with respect to each other, for example rotated about an axis perpendicular to a surface of support substrate 10 on which components 20 are disposed. Such a rotation can distribute electrical connections about component stack 28 and facilitate wiring interconnections. Rotated components 20 can have a similar structure and component connection 30 arrangements and the component connections 30 can be rotated with components 20 so that component connections 30 are disposed in different locations and at different angles to each other and can extend in different directions over support substrate 10 and metal layers 82. Such a rotation can also reduce unwanted reinforcing of magnetic or electrical fields, e.g., reduce unwanted constructive interactions, interference, or noise generated by components 20 in component stack 28. Such a rotation is illustrated in
Component stack 28 of embedded components 20 can be disposed on support substrate 10, for example first metal layer 82A can be disposed on support substrate 10 or a layer disposed on support substrate 10.
According to some embodiments, metal layers 82 can be electrically connected through connections on an edge of components 20 (e.g., as in
As shown in
In some embodiments, an embedded component stack 28 comprises multiple components 20 in one or more dielectric layers 59. For example, a first plurality of first components 20A can be disposed in first dielectric layer 59A comprising a second plurality of second components 20B disposed in the second dielectric layer 59B, or both, as shown, for example, in the offset embedded component stack 28 of
According to embodiments of the present disclosure, by providing embedded component 20 stacks 28 with metal layers 82 between components 20, greater amounts of electrical current can be distributed to components 20 with less resistance, improved efficiency, reduced electromagnetic interference, and improved thermal dissipation. Furthermore, the use of micro-transfer printed components 20 can reduce the thickness of components 20 and therefore the thickness of dielectric layers 59, reducing the topography of each layer in a stack 28 and improving the planarization of each layer and facilitating electrical connections between components 20 in each layer by reducing the step height of each component 20.
As shown in
Electronic circuit 12 can be a circuit that includes active or passive (or both) components or elements. For example, an active electronic circuit 12 can include a transistor, an amplifier, or a switch and, in some embodiments, can provide control functions to components 20. Electronic circuit 12 can be a silicon circuit in a silicon support substrate 10 for compound semiconductor components 20, such as GaN, GaAs, or InP, for example useful for power or radio frequency applications. Passive components such as conductors, resistors, capacitors, and inductors can also be included in electronic circuit 12. Portions of electronic circuit 12 can be electrically connected to circuit contact pads 16. Circuit contact pads 16 can be portions of electronic circuit 12 that are available to make electrical connections with electrical devices external to electronic circuit 12, for example such as controllers, power supplies, ground, or signal connections. Circuit contact pads 16 can be, for example, rectangular areas of electrically conductive materials accessible or exposed to external elements such as wires or conductors or component transistor 21 or any one or all of the component source, gate, and drain connections 32, 34, 36 and component connections 30. Electrical connections to the circuit contact pads 16 can be made using solder and solder methods, photolithographic processes, or by contacting and possibly penetrating the contact pads 16 with electrically conductive protrusions or spikes (e.g., connection posts 50) formed in or on a device with another substrate separate, distinct, and independent from support substrate 10 and connected to component transistors 21, for example as described in U.S. Pat. No. 10,468,363 entitled Chiplets with Connection Posts, whose contents are incorporated by reference in their entirety. Alternatively, the component transistor 21 can include connection posts 50 that are printed onto contact pads 16 of a support substrate 10.
Support substrate 10 and component transistors 21 can take a variety of forms, shapes, sizes, and materials. In some embodiments, component transistor 21 is thinner than support substrate 10. In some embodiments, support substrate 10 can have a thickness no greater than 500 microns (e.g., no greater than 100 microns, no greater than 50 microns, or no greater than 20 microns). In some embodiments, components 20 are chiplets, small integrated structures, for example bare die 98, that are micro-transfer printed to support substrate 10 and electrically connected using photolithographic materials and methods, or with connection posts 50 and contact pads 16. In various embodiments, component 20 has at least one of a width, a length, and a height from 2 to 50 μm (e.g., 2 to 5 μm, 5 to 10 μm, 10 to 20 μm, or 20 to 50 μm). In some embodiments, components 20 can have a thickness no greater than 20 microns (e.g., no greater than 10 microns, no greater than 5 microns, no greater than 2 microns, no greater than 1 micron, or no greater than 0.5 micron). Such a variety of sizes and small component substrates 56 can enable highly integrated and small structures useful in a corresponding variety of electronic systems and can provide a high degree of integration and material utilization and consequently reduced manufacturing costs and improved performance. Assemblies of integrated components 20 (e.g., multi-component transistor structure 99) can be subsequently packaged. Broken (e.g., fractured) or separated component tethers 52 can have a thickness of several nm (e.g., no more than 50, 100, 200, 500, 700, or 800 nm) to a few μm (e.g., no more than 1-5 μm), for example from 600 nm to 1.5 μm. The integrated assembly (e.g., multi-component transistor structure 99) can be a surface-mount device.
As is understood by those skilled in the art, the terms “over”, “under”, “above”, “below”, “beneath”, and “on” are relative terms and can be interchanged in reference to different orientations of the layers, elements, and substrates included in the present disclosure. For example, a first layer on a second layer, in some embodiments means a first layer directly on and in contact with a second layer. In other embodiments, a first layer on a second layer can include another layer there between. Additionally, “on” can mean “on” or “in.” As additional non-limiting examples, a patterned sacrificial layer 68 or sacrificial portion 66 is considered “on” a substrate when a layer of sacrificial material or sacrificial portion 66 is on top of the substrate, when a portion of the substrate itself is the patterned sacrificial layer 68, or when the patterned sacrificial layer 68 or sacrificial portion 66 comprises material on top of the substrate or a portion of the substrate itself.
Having described certain embodiments, it will now become apparent to one of skill in the art that other embodiments incorporating the concepts of the disclosure may be used. Therefore, the disclosure should not be limited to the described embodiments, but rather should be limited only by the spirit and scope of the following claims.
Throughout the description, where apparatus and systems are described as having, including, or comprising specific components, or where processes and methods are described as having, including, or comprising specific steps, it is contemplated that, additionally, there are apparatus, and systems of the disclosed technology that consist essentially of, or consist of, the recited components, and that there are processes and methods according to the disclosed technology that consist essentially of, or consist of, the recited processing steps.
It should be understood that the order of steps or order for performing certain action is immaterial so long as the disclosed technology remains operable. Moreover, two or more steps or actions in some circumstances can be conducted simultaneously. The disclosure has been described in detail with particular reference to certain embodiments thereof, but it will be understood that variations and modifications can be effected within the spirit and scope of the disclosure.
Reference is made to U.S. patent application Ser. No. 17/526,874, filed on Nov. 15, 2021, entitled Disaggregated Transistor Devices by Batchelor et al.
