Patent Grant
11810861
The disclosure relates to a field-effect transistor (FET) suitable for, for example but not limited to, a switch device of a radio-frequency device, and a method of manufacturing the same, and a radio-frequency device including the field-effect transistor.
Radio-frequency switches (RF-SW) configured to turn on and off a radio frequency (RF) are used for front ends of portable communication terminals such as mobile phones. In such radio-frequency switches, a low loss of a radio frequency passing therethrough is an important characteristic. For such a low loss, it is important to reduce a resistance (on-resistance) of an FET in an on state or a capacitance (off-capacitance) of the FET in an off state, i.e., to reduce the product (Ron*Coff) of the on-resistance and the off-capacitance.
The off-capacitance includes a component (an intrinsic component) generated in, for example but not limited to, a diffusion layer and a substrate, and a component (an extrinsic component) generated in, for example but not limited to, a gate electrode, a contact plug, and a wiring line on the contact plug. For example, in the field of ultra-small MOSFETs, it is proposed to have an air gap around a gate electrode to reduce a parasitic capacitance between the gate electrode and a contact plug, thereby reducing an extrinsic component (for example, refer to Patent Literature 1).
Patent Literature 1: Japanese Unexamined Patent Application Publication No. 2002-359369
In a configuration in Patent Literature 1, it is difficult to sufficiently reduce a parasitic capacitance between the gate electrode and a wiring line on the contact plug, a capacitance (an inter-wiring capacitance) generated between wiring lines on the contact plug, or any other capacitance, and there is still room for improvement.
It is desirable to provide a field-effect transistor that makes it possible to reduce an extrinsic component of an off-capacitance, and a method of manufacturing the same, and a radio-frequency device including the field-effect transistor.
A field-effect transistor according to an embodiment of the disclosure includes the following components (A) to (E).
In the field-effect transistor according to the embodiment of the disclosure, the low-dielectric constant region is provided at least in the first region below the bottom surfaces of the first metals along the stacking direction in the region between the first metals along the in-plane direction of the semiconductor layer. This makes it possible to reduce a parasitic capacitance between the gate electrode and the contact plug, or a parasitic capacitance between the gate electrode and the first metal, thereby reducing an extrinsic component of an off capacitance.
A radio-frequency device according to an embodiment of the disclosure is provided with a field-effect transistor, and the field-effect transistor includes the following components (A) to (E).
A method of manufacturing a field-effect transistor according to an embodiment of the disclosure includes the following (A) to (E).
According to the field-effect transistor of the embodiment of the disclosure, the ratio-frequency device of the embodiment of the disclosure, and the method of manufacturing the field-effect transistor of the embodiment of the disclosure, the low-dielectric constant region is provided at least in the first region below the bottom surfaces of the first metals along the stacking direction in the region between the first metals along the in-plane direction of the semiconductor layer, which makes it possible to reduce the extrinsic component of the off-capacitance.
It is to be noted that effects of the embodiments of the disclosure are not limited to effects described here, and may include any effect described in the disclosure.
Some embodiments of the disclosure will be described in detail below with reference to the accompanying drawings. It is to be noted that description will be given in the following order.
In the SPST switch 1A, on-off control is performed by application of control voltages Vc1 and Vc2, respectively, to gates of the first switching device FET1 and the second switching device FET2 through resistors. In an on state, as illustrated in
On-resistances and off-capacitances of the first switching device FET1 and the second switching device FET2 are respectively represented by Ron/Wg1, Ron/Wg2, Coff*Wg1, and Coff*Wg2 using values Ron [Ωmm] and Coff [fF/mm] per unit length of an FET, and gate widths Wg1 and Wg2 [mm]. The on-resistances are inversely proportional to the gate widths Wg1 and Wg2, and the off-capacitances are proportional to the gate widths Wg1 and Wg2.
Another characteristic of the on-resistance and the off-capacitance is that a loss by the on-resistance is not dependent on frequency, whereas a capacitance loss increases with an increase in frequency. When a gate width Wg is increased in order to reduce a loss, a radio-frequency loss by an input capacitance is caused. For this reason, in order to reduce the loss with use of the largest possible gate width Wg, it is important to reduce both the values Ron and Coff per unit length, i.e., to minimize Ron*Coff (product).
The gate electrode 20 may have a multi-finger structure including a plurality of finger sections 21 that extend along a same direction (for example, a Y direction) and a coupling section (a gate routing wiring line) 22 configured to couple the plurality of finger sections 21 to one another. It is to be noted that the gate width Wg of the field-effect transistor 10 used for the radio-frequency switch 1 is much larger than that of a field-effect transistor used for, for example but not limited to, a logic in order to achieve a reduction in loss, and may be several hundreds of um to several mm. A length (finger length) L21 of the finger section 21 may be, for example, several tens of um. The coupling section 22 is coupled to a gate contact (not illustrated in
It is to be noted that, in the following description and drawings, a length direction of the finger section 21 of the gate electrode 20 is the Y direction, a length direction of the coupling section 22 is an X direction, and a direction (a stacking direction) orthogonal to these directions is a Z direction.
As with the gate electrode 20, the source electrode 30S may include a plurality of finger sections 31S that extend along a same direction (for example, the Y direction) and a coupling section (a source routing wiring line) 32S configured to couple the plurality of finger section 31S to one another. The coupling section 32S is coupled to a source contact (not illustrated).
As with the gate electrode 20, the drain electrode 30D may include a plurality of finger sections 31D that extend along a same direction (for example, the Y direction) and a coupling section (drain routing wiring line) 32D configured to couple the plurality of finger sections 31D to one another. The coupling section 32D is coupled to a drain contact (not illustrated).
The finger sections 31S of the source electrode 30S and the finger sections 31D of the drain electrode 30D are alternately provided in gaps between the finger sections 21 of the gate electrode 20. The finger sections 21 of the gate electrode 20 and the finger sections 31S of the source electrode 30S are disposed inside an active region AA. The coupling section 22 of the gate electrode 20, the coupling section 32S of the source electrode 30S, and the coupling section 32D of the drain electrode 30D are disposed in a device isolation region AB (not illustrated in
The gate electrode 20 may be provided on the semiconductor layer 50 with a gate oxide film 23 in between. The gate electrode 20 may have, for example, a thickness of 150 nm to 200 nm both inclusive, and may be made of, for example, polysilicon. The gate oxide film 23 may have, for example, a thickness of about 5 nm to about 10 nm both inclusive, and may be made of, for example, silicon oxide (SiO2).
The semiconductor layer 50 may be made of, for example, silicon (Si). The semiconductor layer 50 has a source region 50S and a drain region 50D both made of n-type (n+) silicon with the gate electrode 20 in between. Low resistance regions 51S and 51D made of high-concentration n-type (n++) silicon or silicide may be respectively provided on surfaces of the source region 50S and the drain region 50D for connection with the contact plugs 60S and 60D. Extension regions 52S and 52D made of low-concentration n-type (n−) silicon may be respectively provided between the source region 50S and the gate electrode 20 and between the drain region 50D and the gate electrode 20.
The semiconductor layer 50 may be provided on a supporting substrate 53 with an embedded oxide film 54 in between. In other words, the supporting substrate 53, the embedded oxide film 54, and the semiconductor layer 50 configure a SOI (Silicon on Insulator) substrate 55. The supporting substrate 53 may be configured of, for example, a high-resistance silicon substrate. The embedded oxide film 54 may be made of, for example, SiO2.
The contact plugs 60S and 60D are respectively coupled to the low-resistance regions 51S and 51D of the source region 50S. The contact plugs 60S and 60D may each have, for example, a laminate configuration (not illustrated) including a titanium (Ti) layer, a titanium nitride (TiN) layer, and a tungsten (W) layer. The titanium layer is a film configured to reduce contact resistance with a layer below the contact plugs 60S and 60D. The titanium nitride layer is a barrier metal configured to suppress diffusion of the tungsten layer provided inside the titanium nitride layer into silicon.
The first metals M1 may each include, for example, the source electrode 30S stacked on the contact plug 60S and the drain electrode 30D stacked on the contact plug 60D. The first metals M1 may each have, for example, a thickness from 500 nm to 1000 nm both inclusive, and may be made of, for example, aluminum (Al).
The low-dielectric constant region 70 is provided in a region between the first metals M1 along an XY-plane direction of the semiconductor layer 50, i.e., a region between the source electrode 30S and the drain electrode 30D (above the finger section 21 of the gate electrode 20). The low-dielectric constant region 70 is also provided at least in a first region A1 below bottom surfaces of the first metals M1 along a stacking direction Z. This makes it possible to reduce the extrinsic component of the off-capacitance in the field-effect transistor 10.
In other words, as illustrated in
The intrinsic component Cin may include, for example, the following capacitances. The capacitances may include a capacitance Cssub or Cdsub generated between the source region 50S or the drain region 50D and the supporting substrate 53, a capacitance Csg or Cdg generated between the source region 50S or the drain region 50D and the gate electrode 20, a capacitance Cds generated between the source region 50S and the drain region 50D, and a capacitance Csb or Cdb generated between the source region 50S or the drain region 50D and a bottom (a body) of the semiconductor layer 50.
The extrinsic component Cex may include, for example, the following capacitances. The capacitances may include a capacitance between the gate electrode 20 and the contact plug 60S or 60D or a capacitance CgM between the gate electrode 20 and each of the first metals M1, and a capacitance (inter-wiring capacitance) CMM1 generated between the first metals M1.
It is to be noted that
In order to reduce the off-capacitance, it is specifically effective to reduce the extrinsic component Cex. In this embodiment, the low-dielectric constant region 70 is provided in the foregoing regions along the XY-plane direction and the stacking direction Z to reduce the extrinsic component Cex. This makes it possible to reduce the product (Ron*Coff) of the on-resistance and the off-capacitance, thereby achieving a reduction in loss in the radio-frequency switch 1.
More specifically, as illustrated in
Alternatively, the low-dielectric constant region 70 may be provided in the first region A1 and the second region A2 along the stacking direction Z, as illustrated in
Moreover, the low-dielectric constant region 70 may be provided in the first region A1 along the stacking direction Z as illustrated in
(Simulation Results)
As can be seen from
Moreover, the field-effect transistor 10 illustrated in
The one or more insulating films 80 may preferably include a plurality of insulating films with different etching rates. This makes it possible to control a stop position of etching for the opening P with high accuracy with use of a difference in etching rate between the plurality of insulating films in a manufacturing process to be described later. Such control makes it possible to suppress a dose loss of an Si surface caused in a case where a surface of the gate electrode 20 is cut or a side surface of the gate electrode 20 is cut to cause etching to reach the Si surface, variation in gate length by side etching of the gate oxide film 23, an increase in variation in threshold voltage caused by the variation in gate length, thereby stably manufacturing the field-effect transistor 10 and improving reliability of the field-effect transistor 10.
More specifically, the one or more insulating films 80 may preferably include, for example, a first insulating film 81, a second insulating film 82, and a third insulating film 83. The surface (including the top surface and the side surface) of the gate electrode 20 and a top surface of the semiconductor layer 50 are covered with the first insulating film 81. A surface of the first insulating film 81 is covered with the second insulating film 82. The third insulating film 83 is provided between a surface of the second insulating film 82 and the bottom surface of the first metal M1. The second insulating film 82 may be preferably made of a material with a different etching rate from the etching rates of the first insulating film 81 and the third insulating film 83. For example, each of the first insulating film 81 and the third insulating film 83 may be preferably configured of, for example, a silicon oxide (SiO2) film, and the second insulating film 82 may be configured of, for example, a silicon nitride (SiN) film. This allows the second insulating film 82 to have a function as an etching stopper layer. The opening P may be preferably opened to the top surface of the second insulating film 82 through at least the third insulating film 83.
Moreover, the one or more insulating films 80 may further include a fourth insulating film 84. A top surface of the third insulating film 83 and a surface (including the top surface and a side surface) of each of the first metals M1 are covered with the fourth insulating film 84. The opening P may be preferably opened from a top surface of the fourth insulating film 84 to the top surface of the second insulating film 82 through the fourth insulating film 84 and the third insulating film 83. The fourth insulating film 84 may be preferably configured of, for example, a silicon oxide (SiO2) film.
The one or more insulating films 80 may further include a fifth insulating film 85 on the fourth insulating film 84. The low-dielectric constant region 70 may include an air gap AG provided at least in a part of the opening P. The configuration of the low-dielectric constant region 70 or the air gap AG is not specifically limited as long as the low-dielectric constant region 70 or the air gap AG has a lower dielectric constant than the dielectric constant of the silicon oxide (SiO2 with a dielectric constant of 3.9) film forming the third insulating film 83 and the fourth insulating film 84, and the air gap AG may contain air (with a dielectric constant of 1.0), or may be in a vacuum. A top of the air gap AG may be preferably blocked by the fifth insulating film 85. Thus, the air gap AG is hermetically sealed by the fifth insulating film 85. A side surface and a bottom surface of the opening P may be covered with the fifth insulating film 85. The fifth insulating film 85 may be configured of, for example, a silicon oxide (SiO2) film. It is to be noted that a sixth insulating film 86 made of, for example, silicon oxide (SiO2) may be provided above the fifth insulating film 85 as necessary.
The low-dielectric constant region 70 may be preferably provided with, for example, a width W70 equal to or smaller than a width W82 of a region where the surface of the gate electrode 20 is covered with the first insulating film 81 and the second insulating film 82.
The multilayer wiring section 90 may include, for example, a first wiring layer 91 and a second wiring layer 92. The first wiring layer 91 may be disposed, for example, in the same layer as the source electrode 30S and the drain electrode 30D, i.e., the first metals M1. The second wiring layer 92 may serve as, for example, a second metal M2 above the first metal M1. The first wiring layer 91 and the second wiring layer 92 may be coupled to each other by, for example, a contact plug 93.
The low-dielectric constant region 70 is not provided between the first wiring layers 91 or between the second wiring layers 92 in the multilayer wiring section 90. In other words, the low-dielectric constant region 70 is provided inside the field-effect transistor 10 in the device region AA1 of the active region AA.
The finger sections 21 of the gate electrode 20, the finger sections 31S of the source electrode 30S, and the finger sections 31D of the drain electrode 30D are provided in the active region AA. The finger sections 21 of the gate electrode 20 extend along one direction (for example, the Y direction). The finger sections 31S of the source electrode 30S and the finger sections 31D of the drain electrode 30D extend in parallel with the finger sections 21 of the gate electrode 20 on both sides of the finger sections 21 of the gate electrode 20. The contact plugs 60S and 60D are respectively provided below the finger sections 31S of the source electrode 30S and the finger sections 31D of the drain electrode 30D, and extend in parallel with the finger sections 21 of the gate electrode 20. The low-dielectric constant region 70 is provided on the finger sections 21 of the gate electrode 20, and extends in parallel with the finger section 21 of the gate electrode 20. In other words, the low-dielectric constant region 70 is provided in a position superimposed on each of the finger sections 21 of the gate electrode 20 along the XY-plane direction.
The coupling section 22 of the gate electrode 20, the coupling section 32S of the source electrode 30S, the coupling section 32D of the drain electrode 30D are provided in the device isolation region AB. The coupling section 22 of the gate electrode 20 is coupled to the gate contact GC. The coupling section 32S of the source electrode 30S is coupled to the source contact (not illustrated). The coupling section 32D of the drain electrode 30D is coupled to the drain contact (not illustrated).
As illustrated in
Moreover, the gate contact GC may be preferably covered with the one or more insulating films 80, i.e., the first to the sixth insulating films 81 to 86 as with the gate electrode 20 in the field-effect transistor 10. Reliability of the gate contact GC is maintained by covering the gate contact GC with the one or more insulating films 80.
For example, the field-effect transistor 10 may be manufactured as follows.
Subsequently, a silicon oxide film is formed as an implantation through film (not illustrated) by, for example, a thermal oxidation method, and well implantation and channel implantation are performed on the active region AA, and thereafter the implantation through film is removed. Subsequently, as illustrated in
After the gate electrode 20 is formed, as illustrated in
After the source region 50S and the drain region 50D are formed, as illustrated in
After the first insulating film 81 is formed, as illustrated in
After the second insulating film 82 is formed, as illustrated in
After the third insulating film 83 is formed, as illustrated in
After the contact holes H1 are formed, as illustrated in
After the low-resistance regions 51S and 51D are formed, as illustrated in
After the contact plugs 60S and 60D are formed, as illustrated in
After the source electrode 30S and the drain electrode 30D are formed, as illustrated in
After the fourth insulating film 84 is formed, as illustrated in
After the opening P is formed, as illustrated in
Thereafter, as illustrated in
In the field-effect transistor 10, the low-dielectric constant region 70 is provided, along the stacking direction Z, in the first region A1 below the bottom surface of the first metal M1, the second region A2 between the bottom surface and the top surface of the first metal M1, and the third region A3 above the top surface of the first metal M1 in a region between the first metals M1 along the XY-plane direction of the semiconductor layer 50. Thus, the capacitance between the gate electrode 20 and the contact plug 60S or 60D or the capacitance CgM between the gate electrode 20 and each of the first metals M1, or the capacitance (inter-wiring capacitance) CMM1 generated between the first metals M1, or any other capacitance are reduced to reduce the extrinsic component Cex of the off-capacitance.
In this embodiment, the low-dielectric constant region 70 is provided at least in the first region A1 below the bottom surface of the first metal M1 along the stacking direction Z in a region between the first metals M1 along the XY-plane direction of the semiconductor layer 50. This makes it possible to reduce the extrinsic component Cex of the off-capacitance and reduce the product (Ron*Coff) of the on-resistance and the off-capacitance, thereby facilitating a reduction in loss that is an important characteristic of the radio-frequency switch 1.
Moreover, the low-dielectric constant region 70 is provided throughout the foregoing first region A1, the foregoing second region A2, and the foregoing third region A3 along the stacking direction Z. This makes it possible to reduce the capacitance between the gate electrode 20 and the contact plug 60S or 60D or the capacitance CgM between the gate electrode 20 and each of the first metals M1, the capacitance (inter-wiring capacitance) CMM1 generated between the first metals M1, and any other capacitance, thereby reducing the extrinsic component Cex of the off-capacitance.
Further, the one or more insulating films 80 including a plurality of insulating films with different etching rates are provided on the semiconductor layer 50. This makes it possible to control the stop position of etching for the opening P with high accuracy with use of a difference in etching rate between the plurality of insulating films. Such control makes it possible to suppress a dose loss of an Si surface caused in a case where the surface of the gate electrode 20 is cut or the side surface of the gate electrode 20 is cut to cause etching to reach the Si surface, variation in gate length by side etching of the gate oxide film 23, an increase in variation in threshold voltage caused by the variation in gate length, thereby stably manufacturing the field-effect transistor 10 and improving reliability of the field-effect transistor 10.
In addition, the opening P is opened from the top surface of the one or more insulating films 80 toward the top surface of the gate electrode 20, and the low-dielectric constant region 70 is provided in the opening P. This makes it possible to have a wide width WP of the opening P. This solves an issue that, when an air gap is provided in proximity to the gate electrode 20 by wet etching, it is difficult for an etching solution to enter a narrow air gap. Thus, it is possible to improve etching uniformity in a wafer plane of the SOI substrate 55 and uniformity of characteristics of the field-effect transistor 10.
In the foregoing first embodiment, description is given of the case where only the first metals M1 are respectively stacked on the contact plugs 60S and 60D. However, the disclosure is applicable to a case where the second metals M2 are stacked on the first metals M1 such as a field-effect transistor 10A illustrated in
The second metals M2 are provided between the fourth insulating film 84 and the fifth insulating film 85. Each of the first metals M1 and corresponding one of the second metals M2 are coupled to each other by a contact plug 94. Moreover, the one or more insulating films 80 may further include a seventh insulating film 87 covering the top surface of the fourth insulating film 84 and surfaces of the second metals M2. The opening P is opened from a top surface of the seventh insulating film 87 to the top surface of the second insulating film 82 through the seventh insulating film 87, the fourth insulating film, and the third insulating film 83. The air gap AG similar to that in the first embodiment is provided as the low-dielectric constant region 70 in the opening P.
The air gap AG is provided in the first region A1 below the bottom surface of the first metal M1, the second region A2 between the bottom surface and the top surface of the first metal M1, and the third region A3 above the top surface of the first metal M1 along the stacking direction Z. In the third region A3, the air gap AG is provided between the first metals M1 and between the second metals M2. Accordingly, in this embodiment, as with the foregoing first embodiment, in addition to reducing the capacitance between the gate electrode 20 and the contact plug 60S or 60D or the capacitance CgM between the gate electrode 20 and each of the first metals M1, or the capacitance (inter-wiring capacitance) CMM1 generated between the first metals M1, the capacitance (inter-wiring capacitance) CMM2 generated between the second metals M2 is reduced to reduce the extrinsic component Cex of the off-resistance.
Moreover, in the foregoing first embodiment, description is given of the case where the low-dielectric constant region 70 is provided with the width W70 equal to or smaller than the width W82 of the region where the surface of the gate electrode 20 is covered with the first insulating film 81 and the second insulating film 82. However, in a case where the width of the finger section 21 of the gate electrode 20 is reduced, as with a field-effect transistor 10B illustrated in
Further, in the foregoing first embodiment, description is given of the case where the air gap AG hermetically sealed in the opening P is provided as the low-dielectric constant region 70. However, the low-dielectric constant region 70 is not limited to the air gap AG, and may be made of a material with a lower dielectric constant than the dielectric constants of the third insulating film 83 and the fourth insulating film 84 (insulating films penetrated by the opening P). More specifically, for example, in a case where the third insulating film 83 and the fourth insulating film 84 are silicon oxide (SiO2 with a dielectric constant of 3.9) films, the fifth insulating film 85 may be made of SiOC (carbon-doped silicon oxide with a dielectric constant of 2.9), and at least a part of the opening P may be filled with the fifth insulating film 85. For example, as with a field-effect transistor 10C illustrated in
In addition, in the foregoing first embodiment, description is given of the case where the low-dielectric constant region 70 extends in parallel with the finger sections 21 of the gate electrode 20. However, as with a field-effect transistor 10D illustrated in
First, as illustrated in
Subsequently, as illustrated in
Subsequently, the resist film R1 is removed, and as illustrated in
Furthermore, in the foregoing first embodiment, description is given of the case where the low-dielectric constant region 70 (such as the air gap AG) is provided above the finger sections 21 of the gate electrode 20 in the active region AA as illustrated in
In the radio communication unit 3, upon transmission, i.e., in a case where a transmission signal is outputted from a transmission system of the radio communication unit 3 to the antenna ANT, the transmission signal outputted from the baseband section BB is outputted to the antenna ANT through the radio frequency integrated circuit RFIC, the high power amplifier HPA, and the radio-frequency switch 1.
Upon reception, i.e., in a case where the signal received by the antenna is inputted to a reception system of the radio communication unit 3, the received signal is inputted to the baseband section BB through the radio-frequency switch 1 and the radio frequency integrated circuit RFIC. The signal processed by the baseband section BB is outputted from an output section such as the audio output section MIC, the data output section DT, and the interface section I/F.
Although the disclosure is described referring to the foregoing embodiments, the disclosure is not limited thereto, and may be variously modified.
Moreover, for example, in the foregoing embodiments, the specific configurations of the radio-frequency switch 1, the field-effect transistor 10, the radio communication unit 3 are described; however, they are not limited to configurations including all the components illustrated in the drawings. Moreover, some of the components may be replaced by other components.
In addition, in the foregoing embodiments, description is given of the case where the field-effect transistor 10 is applied to the radio-frequency switch 1 of the radio communication unit 3; however, the field-effect transistor 10 is applicable to other radio frequency devices such as a PA (Power Amplifier) in addition to the radio-frequency switch (RF-SW).
Moreover, the shape, the material, and thickness of each layer, the film formation method, or any other condition are not limited to those described in the foregoing embodiments, and any other shape, any other material, any other thickness, or any other film formation method may be employed.
Furthermore, for example, in the foregoing embodiments, description is given of the case where the supporting substrate 53 of the SOI substrate 55 is a high-resistance silicon substrate. However, the SOI substrate 55 may be a so-called SOS (Silicon on Sapphire) substrate including the supporting substrate 53 made of sapphire. Since the supporting substrate 53 made of sapphire has insulating properties, the field-effect transistor 10 formed on the SOS substrate exhibits characteristics similar to those of a compound-based FET such as a GaAs-based FET. It is to be noted that the disclosure is not limited to the SOI substrate or the SOS substrate, and the disclosure is applicable to a case where the field-effect transistor 10 is formed on a bulk substrate.
It is to be noted that the effects described in this description are non-limiting examples, and any other effects may be included.
It is to be noted that the technology may have following configurations.
This application claims the benefit of Japanese Priority Patent Application JP 2014-86805 filed on Apr. 18, 2014, the entire contents of which are incorporated herein by reference.
It should be understood by those skilled in the art that various modifications, combinations, sub-combinations, and alterations may occur depending on design requirements and other factors insofar as they are within the scope of the appended claims or the equivalents thereof.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2014-086805 | Apr 2014 | JP | national |
This application is a continuation application of application Ser. No. 17/064,112, filed Oct. 6, 2020, which is a continuation application of application Ser. No. 16/700,703, filed Dec. 2, 2019, and issued as U.S. Pat. No. 10,847,466 on Nov. 24, 2020, which is a continuation application of application Ser. No. 16,050,815, filed Jul. 31, 2018, which issued as U.S. Pat. No. 10,535,607 on Jan. 14, 2020, which is a continuation application of application Ser. No. 15/499,195, filed Apr. 27, 2017, which issued as U.S. Pat. No. 10,074,610 on Sep. 11, 2018, which is a continuation application of application Ser. No. 14/897,867, filed Dec. 11, 2015, which issued as U.S. Pat. No. 9,695,865 on May 23, 2016, which is a national stage of PCT/JP2015/059126, filed Mar. 25, 2015, which claims the benefit of Japanese Patent Application JP 2014-86805 filed on Apr. 18, 2014, the contents of which are incorporated herein by reference in their entirety.
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| Number | Date | Country | |
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| 20220384349 A1 | Dec 2022 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 17064112 | Oct 2020 | US |
| Child | 17846241 | US | |
| Parent | 16700703 | Dec 2019 | US |
| Child | 17064112 | US | |
| Parent | 16050815 | Jul 2018 | US |
| Child | 16700703 | US | |
| Parent | 15499195 | Apr 2017 | US |
| Child | 16050815 | US | |
| Parent | 14897867 | US | |
| Child | 15499195 | US |
