Patent Application
20190198313
None.
Semiconductors, including III-V semiconductor materials, are considered as an alternative to Si-based semiconductors. Recently, the semiconductor technology further relies on the newly-developed III-V materials driven by the demands for unique and advanced properties in the new applications. However, the materials and device technology in such applications face both technical and economic challenges for the next-generation applications. The efficiencies and performances need to be further improved while the product prices need to be reduced. In addition, the application locations and functionality of the semiconductor devices are to be expanded. To address the challenges in the next-generation high-efficiency, flexible, and multifunctional electronic and photonic devices and to reduce manufacturing costs, a whole new technology platform is needed, instead of incremental improvement of characteristics at marginally reduced costs using the current platform. The development can begin from the substrate of the semiconductor materials structures, which is one of the most dominant limiting factors in terms of device mechanical flexibility and manufacturing costs.
In an embodiment, a method of fabricating a semiconductor device comprising: directly forming, via chemical vapor deposition, a 2D material on a substrate, wherein the substrate comprises Si (100), a metallic foil, or an inorganic flexible substrate, and the 2D material comprises black phosphorous, hexagonal boron nitride (BN), or graphene. In an embodiment, the method further comprises directly forming a c-axis AlN layer on the 2D material layer, wherein the AlN layer comprises the same crystallographic structure as the 2D material layer, directly forming a GaN layer on the AlN layer via chemical vapor deposition (CVD). In an embodiment, the method further comprises forming the GaN layer to comprise a wurtzite structure, wherein the AlN layer does not comprise a wurtzite structure.
In an embodiment, a method of fabricating a semiconductor structure comprising: directly forming a catalyst layer in contact with a substrate; forming a 2D material layer on the catalyst layer; forming an AlN layer on the 2D material layer; forming a buffer layer on the AlN layer; and forming at least one semiconductor layer on the buffer layer. In one example, the at least one semiconductor layer comprises GaN, InxGa1-xN, or InxAlyGa1-x-yN, and 0≤x≤1 for AlxGa1-xN, wherein 0≤x≤1 for InxGa1-xN, wherein 0≤x≤1 for InxAlyGa1-x-yN, and wherein for InxAlyGa1-x-yN. In an embodiment, the method further comprises forming an adhesion layer on the substrate prior to forming the catalyst layer, wherein the adhesion layer comprises titanium (Ti), chromium (Cr), or nickel (Ni), or combinations thereof and the catalyst layer is formed by electroplating, physical vapor deposition (PVD), or electron beam (e-beam) evaporation
In an embodiment, a semiconductor structure comprising: a substrate; a layer of 2D material formed in contact with the substrate; a first buffer layer formed on the 2D material layer; a second buffer layer formed on the first buffer layer; and a plurality of semiconductor layers grown epitaxially on the second buffer layer. In an embodiment, the structure further comprises a catalyst layer formed on the substrate layer, wherein the 2D material layer is formed directly on the catalyst layer and the thickness of the catalyst layer is from about 1 nm to about 1 mm and an adhesion layer formed between the substrate layer and the catalyst layer. In an embodiment, the adhesion layer comprises titanium (Ti), chromium (Cr), or nickel (Ni), or combinations thereof and has a thickness of 0.1 nm-1 μm. In one example, the first buffer layer comprises AlN, the second buffer layer comprises GaN, and substrate comprises one of a polycrystalline structure; a single-crystalline structure; and an amorphous structure. Further in this embodiment, the first buffer layer comprises a substantially similar crystallographic structure to a crystallographic structure of the 2D material layer and the first buffer layer comprises a different crystallographic structure than the second buffer layer.
For a detailed description of the exemplary embodiments disclosed herein, reference will now be made to the accompanying drawings in which:
The following discussion is directed to various exemplary embodiments. However, one of ordinary skill in the art will understand that the examples disclosed herein have broad application, and that the discussion of any embodiment is meant only to be exemplary of that embodiment, and not intended to suggest that the scope of the disclosure, including the claims, is limited to that embodiment.
The drawing figures are not necessarily to scale. Certain features and components herein may be shown exaggerated in scale or in somewhat schematic form and some details of conventional elements may not be shown in interest of clarity and conciseness.
In the following discussion and in the claims, the terms “including” and “comprising” are used in an open-ended fashion, and thus should be interpreted to mean “including, but not limited to . . . .”
This application incorporates by reference in its entirety PCT Patent Application PCT/US16/26707, “Externally-Strain-Engineered Semiconductor Photonic and Electronic Devices and Assemblies and Methods of Making Thereof,” filed Apr. 8, 2016.
Discussed herein are methods for the direct growth of nearly-single-crystalline III-nitride (III-N) semiconductor materials on amorphous-, polycrystalline-, and other foreign-single-crystalline substrates including flexible substrates. “Nearly” single crystalline material may have a dislocation density of about 109 cm2 whereas as single crystalline material has a dislocation density of less than about 108 cm2. As used herein, a “flexible” substrate or device comprises a substrate or device that is able, while in a first state to be put under tension, compression, torsion, and other strain in one or more directions for a sustained period of time or for a predetermined number of cycles of application and removal of force in a second, force-application state. Once the period of time or number of cycles (or a combination thereof) is reached, the flexible substrate or device returns to its first state. The flexible inorganic photonic and electronic devices fabricated using the systems and methods discussed herein can be used for next-generation solid-state lighting, electronic, electro-mechanic, and photonic applications. Furthermore, embodiments of the systems, structures and methods discussed herein are applicable for monolithic integration of well-matured Si-based devices and emerging III-N-based devices.
Graphene and other 2-dimensional materials may be grown directly on different substrates by inserting a catalyst film. As discussed herein, the “direct growth” or formation of a first component on or partially on a second component (e.g., layers) is used to indicate that there is no transfer process involved in the fabrication of these devices, the layers are formed directly on other layers, in place and in order, in contrast with devices and methods of fabrication of those devices where various layers are formed and then transferred to the semiconductor structure.
These 2D materials may thus serve as an intermediate layer for III-N material deposition to achieve the flexible material heterostructure with single crystalline properties in active device region. In particular, the present disclosure comprises: (1) systems, structures and methods for the direct growth of graphene or other 2-dimensional material, such as hexagonal BN on various different types substrates via a chemical vapor deposition (CVD) method to serve as an intermediate layer for the next III-N layers' growth; (2) the deposition of III-N layers with preferred crystalline axes (nearly-single-crystalline device-quality layers) on Si substrates with a native oxide on grown on top; (3) a method of monolithic integration of wide-band gap III-N devices with Si-based devices is proposed; (4) the direct formation (deposition) of industrially-viable, high-quality III-N layers on the flexible substrate by direct growth is suggested; (5) the fabrication of III-N-based devices on flexible substrates. The embodiments of direct deposition methods and resultant structures discussed herein for high-quality flexible materials and devices is aimed to provide high-performance flexible devices with high durability, roll-to-roll continuous fabrication, low production costs, and high materials quality. “Direct” deposition comprises the formation of a second layer in contact, which may or may not include patterning, etching, and other steps. Current challenges associated with the manufacture of expensive fragile substrates may be addressed through the systems, structures and methods herein. As used herein, a “high-quality” III-N layers are those layers associated with a threading dislocation density from about 103 to 1011 per/cm2.
In various examples, III-V semiconductor materials may be employed as an alternative to Si-based semiconductors. Among III-V materials, III-nitride (III-N) materials have commercially viable electronic and photonic properties. III-N materials, including gallium nitride (GaN) and its related materials such as aluminum gallium nitride (AlxGa1-xN, 0≤x≤1), indium gallium nitride (InxGa1-xN, 0≤x≤1) and indium aluminum gallium nitride (InxAlyGa1-x-yN, 0≤x≤1 and) with wurtzite crystal structures (based on hexagonal lattice), may be employed for solid-state lighting (SSL) and high-power switching- and conversion-applications.
Among different deposition and epitaxial growth techniques of III-N semiconductor materials, metalorganic chemical vapor deposition (MOCDV) method may be used due to its high deposition rate, high throughput, growth parameter controllability, and superb material quality of the products. For the epitaxial growth of MOCVD of III-N materials, single-crystalline sapphire, silicon carbide (SiC), Si (111) wafers are the most widely used substrates. Some limiting factors of the single-crystalline substrates, including high cost, limited size, and non-mechanical flexibility have motivated the search for reliable substrates to use for fabrication of semiconductors.
The methods, structures and systems discussed herein are at least: (1) low cost in substrate materials and material processing and (2) have a comparable or superior quality of III-N material structures as compared to those formed on single-crystalline substrates.
For low cost in substrate materials, polycrystalline or amorphous materials are generally less expensive than single-crystalline materials. Also, scaling-up of the size is easier for polycrystalline or amorphous materials, because precisely controlled bulk solidification process is omitted. In addition, mechanical flexibility can be achieved from substrates in the form of tape/foil instead of wafers. The tape substrate enables the continuous deposition of materials by roll-to-roll growth, which is expected to offer low production cost in material deposition process. Inexpensive substrates such as metal, ceramic, or glass tapes with polycrystalline or amorphous structures may be employed to reduce the substrate cost, low material processing cost, and mechanical flexibility. The substrates discussed herein provide the high structural quality of the III-N materials comparable to the single-crystalline substrates. Discussed herein is a technique to grow buffer layers on the substrates to obtain device-quality III-N materials on low-cost non-single-crystalline substrates. Developing desired buffer layers with low-cost method and implementing intermediate layer on the flexible substrates will result in a novel platform for MOCVD growth of III-N materials. Using the systems and methods discussed herein, there is improved affordability and functionality of III-N-based devices with high quality of the epitaxial layers.
In an embodiment, III-N-based devices are integrated with Si technology on the same (shared) substrate. The Si technology uses Si (100) wafers (single-crystalline Si wafer with cubic atomic configuration on the plane of surface), not Si (111) wafers which may be used in GaN epitaxial growth. The epitaxial growth of III-N wurtzite on Si (100) wafers is technically challenging due to dissimilarity in their crystal structures and atomic configurations. Obtaining device-quality III-N material on Si (100) enables the expanded monolithic integration of Si technology.
Direct Growth of 2D Structures on a Substrate
Graphene and similar materials with honeycomb atomic configurations are 2-dimensionally-structured materials may experience weak atomic bonding to underlying material and strong in-plane atomic bonding. Graphene has a honeycomb structure and is used herein as a template for the epitaxial growth of GaN with a hexagonal wurtzite structure. In contrast to currently employed methods where graphene is grown on a metal foil and transferred to another substrate for GaN growth, the systems and methods used herein employ graphene grown directly on, for example, single crystalline, polycrystalline, and amorphous substrates, as well as on adhesion layers and catalyst layers. Thus, embodiments of methods discussed herein are directed towards the growth of III-N materials on graphene, in contrast to currently employed transfer methods. To achieve the high-quality epitaxially grown III-N materials on different amorphous and polycrystalline flexible substrates, a multi-step direct deposition method (transfer-free) is discussed.
In some embodiments, for the growth of graphene, catalyst materials may be employed. In some examples, Cu and Ni are used for growth of graphene in the form of either thin films or foils that may range in thickness from about 1 nm to about 1 mm thick. The deposition of a thin film catalyst material such as Cu and Ni on the desired substrate may enable the direct growth of graphene via chemical vapor deposition (CVD) on the thin film catalyst. Hence, by taking advantage of the graphene or other 2-d material structure, high-quality III-N materials are achievable independent of the choice of the substrate since the semiconductor material is not formed directly on the substrate. That is, there is no transfer process of the semiconductor involved in the formation of the semiconductor devices discussed herein. Rather, the graphene transferring step is omitted, which simplifies the process, reduces manufacturing costs, and avoids the technical challenges associated with organic material residuals.
The systems and methods herein are aimed at producing device-quality GaN on any given inorganic rigid or flexible substrate regardless of its amorphous, polycrystalline, or single-crystalline structure. The systems and methods discussed herein may extend to applications for devices such as lasers, LEDs including deep ultra violet (DUV) LED and visible LEDs, photodetectors (PDs), and high electron mobility transistors (HEMT). Furthermore, the described growth process is applicable to Si wafer especially Si (100), the most widely used in silicon industry, which deliveries III-N-based device integration with Si-based devices. Integrated circuit (IC) technology will take the advantage of integrating devices such as HEMTs, PDs, LEDs, etc. with available Si-based devices on the same Si substrate during the fabrication process.
Various embodiments discussed herein are associated with (a) The growth of single-crystal semiconductor materials such as III-N materials on inorganic flexible substrates; (b) delivering roll-to-roll continues growth of high quality III-N materials; (c) Reducing fabrication and production cost; (d) High-performance flexible and bendable electronic and photonic devices with broad applications; (e) Single-crystal III-N materials on both amorphous or polycrystalline substrates; (f) Integrating Si-based semiconductor technology with III-N materials industry by suggesting the multi-step deposition methods which are applicable for the same substrate; (g) High-performance electronic and photonic devices with versatile applications; and (h) Extension of multifunctioning devices with relying on simple growth method.
Design and Process: Methods Expanding Flexible Device- and Si-Based-Technology
Discussed herein are methods of growing single-crystalline GaN on substrates by direct deposition of multiple layers to grow single-crystalline GaN. The substrates used for the embodiments discussed herein may be those with amorphous structures such as glass or Si wafer with native oxide (SiO2); or, polycrystalline structures such as ceramics or metals. This method is applicable for both rigid and flexible substrates with either polycrystalline or amorphous structure.
In an embodiment, AlN may be employed as the buffer layer when GaN is grown, owing to its similar material system to GaN. A sputtering process is one the most convenient deposition methods for the AlN deposition as a buffer layer for GaN growth, as it is a low-cost and easily-accessible method comparing to other deposition methods. It is to be understood that the GaN layer may also serve as a buffer layer in various embodiments, and that the use of the term “buffer” may be used to describe a variety of layers in various layer configurations where layer Y is deposited on layer X prior to the deposition of layer Z. In that high level example, layer Y would be the buffer layer, but layer Z may also be a buffer layer is a subsequent layer Q is deposited on layer Y. In some embodiments discussed herein, the methods and structures may also employ directly grown graphene as an intermediate layer for AlN layer.
In various embodiments, different processes may be employed for graphene growth: (1) using direct growth on metal foil (copper (Cu), nickel (Ni), etc.); and (2) growth on any substrate (polycrystalline, single crystal, and amorphous) with an adhesion layer of, for example, a Cu or Ni film. These different platforms may be employed for suggests various types of applications for the next-generation electronic and photonic devices that may include flexible devices.
The structure in
The example in
The layers 602, 604, 606, and 608 are shown in
In another embodiment, using a method applicable to the most of inorganic substrates regardless of their (poly/single/amorphous) crystal structure as long as the substrates can be used in a typical I GaN MOCVD growth temperature (˜1000° C.). As such, the fabrication methods discussed herein can be conducted on rigid and flexible substrates with amorphous, polycrystalline, single-crystalline (with different crystal structure) structure. In this example, a graphene layer is inserted by taking advantage of a catalyst material for graphene growth which makes this method widely applicable for most of inorganic substrates.
In an embodiment, multiple deposition steps are used to fabricate the semiconductor structures and graphene is grown directly on the substrate, in contrast to growing the graphene on another substrate and transferring the graphene to the desired substrate. This example enables direct growth of device-quality GaN on inorganic flexible substrates and Si (100) wafer with and without native amorphous oxide on top. Hence, high-quality semi-conductor layers including AlxInyGa1-x-yN are achievable by taking advantage of device-quality GaN for further device fabrication such as HEMTs, LEDs, lasers, and photodetectors.
The AlN layer 602 may comprise a thickness from about 0.1 nm to about 100 micrometers, the thickness T606 of the flexible substrate 606 may be from about 1 nm to about 1 mm, the graphene layer 604 may comprise a thickness T604 that may range from a single monolayer 604 that may be a self-assembled monolayer 604 of about 1 Angstrom to about 10 nm, and the GaN layer 608 may comprise a thickness T608 of the GaN layer 608 may be from about 0.1 nm to about 100 micrometers. In some embodiments, the thicknesses T608 and T602 may be equal, and in alternate embodiments, T608 may be greater than T602 or T608 may be greater than T602.
In some embodiments, for example, to improve the adhesion of catalyst layer 906 to substrate 902, an adhesion layer 904 such as titanium (Ti), chromium (Cr), or Ni may be inserted between catalyst layer 906 and substrate 902. The adhesion layer 904 may comprise a thickness T904 from about 1 Angstrom to about 1 microns. The catalyst layer 906 can be deposited by different methods including solution electroplating, physical vapor deposition (PVD), e.g. sputtering, or electron beam (e-beam) evaporation. The thickness of the catalyst layer 906 can be in the range of 1 nm to 1 mm. The adhesion layers 904 can also be deposited by similar methods to a thickness of 0.1 nm-1 μm.
In contrast to the bulk nature of the Cu foil substrate discussed in
After the epitaxial growth by MOCVD method, a high-quality buffer layer GaN 912 with c-axis preferred orientation is grown using the high-quality deposited c-axis AlN layer 910. Once the GaN buffer layer 912 is grown, for example, to a thickness T912 from about 0.1 nm to about 100 micrometers, subsequent layers including AlxInyGa1-x-yN layers (0≤x≤1 and 0≤y≤1) 914 and their heterostructures can be grown epitaxially by MOCVD. The AlxInyGa1-x-yN layers (0≤x≤1 and 0≤y≤1) 914 and their heterostructures can be also be grown on GaN with other embodiments, such as GaN 608 with AlN 602 and other layers shown in 600. In one example, a thickness of the epitaxially grown semiconductor layer or layers 914 may be formed to a thickness T914 of 5 nm to about 100 microns. Various thicknesses and compositions may be used for the layers discussed in
In one example of another embodiment of the structure 900 in
Exemplary embodiments have been disclosed. Variations and alternate embodiments that result from combining, integrating, and/or omitting features of the exemplary embodiment(s) are also within the scope of the disclosure. Where numerical ranges or limitations are expressly stated, such express ranges or limitations should be understood to include iterative ranges or limitations of like magnitude falling within the expressly stated ranges or limitations (e.g., from about 1 to about 10 includes, 2, 3, 4, etc.; greater than 0.10 includes 0.11, 0.12, 0.13, etc.). For example, whenever a numerical range with a lower limit, Rl, and an upper limit, Ru, is disclosed, any number falling within the range is specifically disclosed. In particular, the following numbers within the range are specifically disclosed: R=Rl+k*(Ru−Rl), wherein k is a variable ranging from 1 percent to 100 percent with a 1 percent increment, i.e., k is 1 percent, 2 percent, 3 percent, 4 percent, 5 percent, . . . , 50 percent, 51 percent, 52 percent, . . . , 95 percent, 96 percent, 97 percent, 98 percent, 99 percent, or 100 percent. Moreover, any numerical range defined by two R numbers as defined in the above is also specifically disclosed. Use of broader terms such as “comprises,” “includes,” and “having” should be understood to provide support for narrower terms such as “consisting of,” “consisting essentially of,” and “comprised substantially of.” Each and every claim is incorporated into the specification as further disclosure, and the claims are exemplary embodiment(s) of the present invention.
While exemplary embodiments of the invention have been shown and described, modifications thereof can be made by one skilled in the art without departing from the scope or teachings herein. The embodiments described herein are exemplary only and are not limiting. Many variations and modifications of the compositions, systems, apparatus, and methods described herein are possible and are within the scope of the invention. Accordingly, the scope of protection is not limited to the embodiments described herein, but is only limited by the claims that follow, the scope of which shall include all equivalents of the subject matter of the claims. Unless expressly stated otherwise, the steps in a method claim may be performed in any order and with any suitable combination of materials and processing conditions.
This application is a 35 U.S.C. § 371 national stage application of PCT/US2017/050844 filed Sep. 8, 2017, which claims priority to U.S. Application No. 62/393,165 titled, “Flexible Single-Crystal Semiconductor Heterostructures by Direct Growth and Methods of Making Thereof,” filed Sep. 12, 2016, each of which is incorporated by reference herein in their entirety for all purposes.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/US2017/050844 | 9/8/2017 | WO | 00 |
| Number | Date | Country | |
|---|---|---|---|
| 62393165 | Sep 2016 | US |
